Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Ingenic JZ47xx KMS driver - Register definitions and private API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define JZ_REG_LCD_CFG				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define JZ_REG_LCD_VSYNC			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define JZ_REG_LCD_HSYNC			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define JZ_REG_LCD_VAT				0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define JZ_REG_LCD_DAH				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define JZ_REG_LCD_DAV				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define JZ_REG_LCD_PS				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define JZ_REG_LCD_CLS				0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define JZ_REG_LCD_SPL				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define JZ_REG_LCD_REV				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define JZ_REG_LCD_CTRL				0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define JZ_REG_LCD_STATE			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define JZ_REG_LCD_IID				0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define JZ_REG_LCD_DA0				0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define JZ_REG_LCD_SA0				0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define JZ_REG_LCD_FID0				0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define JZ_REG_LCD_CMD0				0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define JZ_REG_LCD_DA1				0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define JZ_REG_LCD_SA1				0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define JZ_REG_LCD_FID1				0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define JZ_REG_LCD_CMD1				0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define JZ_REG_LCD_OSDC				0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define JZ_REG_LCD_OSDCTRL			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define JZ_REG_LCD_OSDS				0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define JZ_REG_LCD_BGC				0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define JZ_REG_LCD_KEY0				0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define JZ_REG_LCD_KEY1				0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define JZ_REG_LCD_ALPHA			0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define JZ_REG_LCD_IPUR				0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define JZ_REG_LCD_XYP0				0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define JZ_REG_LCD_XYP1				0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define JZ_REG_LCD_SIZE0			0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define JZ_REG_LCD_SIZE1			0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define JZ_LCD_CFG_SLCD				BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define JZ_LCD_CFG_PS_DISABLE			BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define JZ_LCD_CFG_CLS_DISABLE			BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define JZ_LCD_CFG_SPL_DISABLE			BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define JZ_LCD_CFG_REV_DISABLE			BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define JZ_LCD_CFG_HSYNCM			BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define JZ_LCD_CFG_PCLKM			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define JZ_LCD_CFG_INV				BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define JZ_LCD_CFG_SYNC_DIR			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define JZ_LCD_CFG_PS_POLARITY			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define JZ_LCD_CFG_CLS_POLARITY			BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define JZ_LCD_CFG_SPL_POLARITY			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define JZ_LCD_CFG_REV_POLARITY			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define JZ_LCD_CFG_PCLK_FALLING_EDGE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define JZ_LCD_CFG_DE_ACTIVE_LOW		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define JZ_LCD_CFG_18_BIT			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define JZ_LCD_CFG_PDW				(BIT(5) | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define JZ_LCD_CFG_MODE_GENERIC_16BIT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define JZ_LCD_CFG_MODE_GENERIC_18BIT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define JZ_LCD_CFG_MODE_GENERIC_24BIT		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define JZ_LCD_CFG_MODE_TV_OUT_P		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define JZ_LCD_CFG_MODE_TV_OUT_I		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define JZ_LCD_CFG_MODE_8BIT_SERIAL		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define JZ_LCD_CFG_MODE_LCM			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define JZ_LCD_VSYNC_VPS_OFFSET			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define JZ_LCD_VSYNC_VPE_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define JZ_LCD_HSYNC_HPS_OFFSET			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define JZ_LCD_HSYNC_HPE_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define JZ_LCD_VAT_HT_OFFSET			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define JZ_LCD_VAT_VT_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define JZ_LCD_DAH_HDS_OFFSET			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define JZ_LCD_DAH_HDE_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define JZ_LCD_DAV_VDS_OFFSET			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define JZ_LCD_DAV_VDE_OFFSET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define JZ_LCD_CTRL_BURST_4			(0x0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define JZ_LCD_CTRL_BURST_8			(0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define JZ_LCD_CTRL_BURST_16			(0x2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define JZ_LCD_CTRL_RGB555			BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define JZ_LCD_CTRL_OFUP			BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define JZ_LCD_CTRL_FRC_GRAYSCALE_16		(0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define JZ_LCD_CTRL_FRC_GRAYSCALE_4		(0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define JZ_LCD_CTRL_FRC_GRAYSCALE_2		(0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define JZ_LCD_CTRL_PDD_MASK			(0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define JZ_LCD_CTRL_EOF_IRQ			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define JZ_LCD_CTRL_SOF_IRQ			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define JZ_LCD_CTRL_OFU_IRQ			BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define JZ_LCD_CTRL_IFU0_IRQ			BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define JZ_LCD_CTRL_IFU1_IRQ			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define JZ_LCD_CTRL_DD_IRQ			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define JZ_LCD_CTRL_QDD_IRQ			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define JZ_LCD_CTRL_REVERSE_ENDIAN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define JZ_LCD_CTRL_LSB_FISRT			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define JZ_LCD_CTRL_DISABLE			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define JZ_LCD_CTRL_ENABLE			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define JZ_LCD_CTRL_BPP_1			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define JZ_LCD_CTRL_BPP_2			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define JZ_LCD_CTRL_BPP_4			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define JZ_LCD_CTRL_BPP_8			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define JZ_LCD_CTRL_BPP_15_16			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define JZ_LCD_CTRL_BPP_18_24			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define JZ_LCD_CTRL_BPP_MASK			(JZ_LCD_CTRL_RGB555 | 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define JZ_LCD_CMD_SOF_IRQ			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define JZ_LCD_CMD_EOF_IRQ			BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define JZ_LCD_CMD_ENABLE_PAL			BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define JZ_LCD_SYNC_MASK			0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define JZ_LCD_STATE_EOF_IRQ			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define JZ_LCD_STATE_SOF_IRQ			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define JZ_LCD_STATE_DISABLED			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define JZ_LCD_OSDC_OSDEN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define JZ_LCD_OSDC_F0EN			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define JZ_LCD_OSDC_F1EN			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define JZ_LCD_OSDCTRL_IPU			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define JZ_LCD_OSDCTRL_RGB555			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define JZ_LCD_OSDCTRL_CHANGE			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define JZ_LCD_OSDCTRL_BPP_15_16		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define JZ_LCD_OSDCTRL_BPP_18_24		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define JZ_LCD_OSDCTRL_BPP_30			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define JZ_LCD_OSDCTRL_BPP_MASK			(JZ_LCD_OSDCTRL_RGB555 | 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define JZ_LCD_OSDS_READY			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define JZ_LCD_IPUR_IPUREN			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define JZ_LCD_IPUR_IPUR_LSB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define JZ_LCD_XYP01_XPOS_LSB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define JZ_LCD_XYP01_YPOS_LSB			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define JZ_LCD_SIZE01_WIDTH_LSB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define JZ_LCD_SIZE01_HEIGHT_LSB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct drm_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct drm_plane_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct platform_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void ingenic_drm_plane_config(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			      struct drm_plane *plane, u32 fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern struct platform_driver *ingenic_ipu_driver_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */