Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __IPUV3_PLANE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __IPUV3_PLANE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <drm/drm_crtc.h> /* drm_plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) struct drm_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) struct drm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) struct ipu_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct drm_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct drm_framebuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct ipuv3_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct dmfc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct ipu_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct ipu_plane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct drm_plane	base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct ipu_soc		*ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct ipuv3_channel	*ipu_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct ipuv3_channel	*alpha_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct dmfc_channel	*dmfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct ipu_dp		*dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	int			dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	int			dp_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	bool			disabling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 				 int dma, int dp, unsigned int possible_crtcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 				 enum drm_plane_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Init IDMAC, DMFC, DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		       struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		       unsigned int crtc_w, unsigned int crtc_h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		       uint32_t src_x, uint32_t src_y, uint32_t src_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		       uint32_t src_h, bool interlaced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ipu_plane_get_resources(struct ipu_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void ipu_plane_put_resources(struct ipu_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ipu_plane_irq(struct ipu_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void ipu_plane_disable_deferred(struct drm_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool ipu_plane_atomic_update_pending(struct drm_plane *plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif