^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX IPUv3 DP Overlay Planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Philipp Zabel, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <drm/drm_fb_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <drm/drm_fourcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_gem_framebuffer_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_plane_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "imx-drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ipuv3-plane.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct ipu_plane_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct drm_plane_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool use_pre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline struct ipu_plane_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) to_ipu_plane_state(struct drm_plane_state *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return container_of(p, struct ipu_plane_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return container_of(p, struct ipu_plane, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const uint32_t ipu_plane_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DRM_FORMAT_ARGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DRM_FORMAT_XRGB1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DRM_FORMAT_ABGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DRM_FORMAT_XBGR1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DRM_FORMAT_RGBA5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DRM_FORMAT_BGRA5551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DRM_FORMAT_ARGB4444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DRM_FORMAT_ARGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DRM_FORMAT_XRGB8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DRM_FORMAT_ABGR8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DRM_FORMAT_XBGR8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DRM_FORMAT_RGBA8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DRM_FORMAT_RGBX8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DRM_FORMAT_BGRA8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DRM_FORMAT_BGRX8888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DRM_FORMAT_UYVY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DRM_FORMAT_VYUY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DRM_FORMAT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DRM_FORMAT_YVYU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DRM_FORMAT_YUV420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DRM_FORMAT_YVU420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DRM_FORMAT_YUV422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DRM_FORMAT_YVU422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DRM_FORMAT_YUV444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DRM_FORMAT_YVU444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DRM_FORMAT_NV12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DRM_FORMAT_NV16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DRM_FORMAT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DRM_FORMAT_RGB565_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DRM_FORMAT_BGR565_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DRM_FORMAT_RGB888_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DRM_FORMAT_BGR888_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DRM_FORMAT_RGBX8888_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DRM_FORMAT_BGRX8888_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const uint64_t ipu_format_modifiers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DRM_FORMAT_MOD_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DRM_FORMAT_MOD_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const uint64_t pre_format_modifiers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DRM_FORMAT_MOD_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DRM_FORMAT_MOD_VIVANTE_TILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DRM_FORMAT_MOD_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ipu_plane_irq(struct ipu_plane *ipu_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) IPU_IRQ_EOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct drm_framebuffer *fb = state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct drm_gem_cma_object *cma_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int x = state->src.x1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int y = state->src.y1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cma_obj = drm_fb_cma_get_gem_obj(fb, plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) BUG_ON(!cma_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) fb->format->cpp[plane] * x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) drm_plane_state_to_ubo(struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct drm_framebuffer *fb = state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct drm_gem_cma_object *cma_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long eba = drm_plane_state_to_eba(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int x = state->src.x1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int y = state->src.y1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cma_obj = drm_fb_cma_get_gem_obj(fb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BUG_ON(!cma_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) x /= fb->format->hsub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) y /= fb->format->vsub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) fb->format->cpp[1] * x - eba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) drm_plane_state_to_vbo(struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct drm_framebuffer *fb = state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct drm_gem_cma_object *cma_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long eba = drm_plane_state_to_eba(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int x = state->src.x1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int y = state->src.y1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cma_obj = drm_fb_cma_get_gem_obj(fb, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) BUG_ON(!cma_obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) x /= fb->format->hsub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) y /= fb->format->vsub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fb->format->cpp[2] * x - eba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!IS_ERR_OR_NULL(ipu_plane->dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ipu_dp_put(ipu_plane->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ipu_dmfc_put(ipu_plane->dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ipu_idmac_put(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ipu_idmac_put(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int alpha_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(ipu_plane->ipu_ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = PTR_ERR(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DRM_ERROR("failed to get idmac channel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (alpha_ch >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ERR(ipu_plane->alpha_ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = PTR_ERR(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) alpha_ch, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (IS_ERR(ipu_plane->dmfc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = PTR_ERR(ipu_plane->dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DRM_ERROR("failed to get dmfc: ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ipu_plane->dp_flow >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(ipu_plane->dp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = PTR_ERR(ipu_plane->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_ERROR("failed to get dp flow: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ipu_plane_put_resources(ipu_plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) switch (ipu_plane->base.state->fb->format->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case DRM_FORMAT_RGB565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case DRM_FORMAT_BGR565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case DRM_FORMAT_RGB888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case DRM_FORMAT_BGR888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case DRM_FORMAT_RGBX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case DRM_FORMAT_BGRX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void ipu_plane_enable(struct ipu_plane *ipu_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ipu_plane->dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ipu_dp_enable(ipu_plane->ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ipu_dmfc_enable_channel(ipu_plane->dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ipu_idmac_enable_channel(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ipu_plane_separate_alpha(ipu_plane))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ipu_idmac_enable_channel(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ipu_plane->dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ipu_dp_enable_channel(ipu_plane->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ipu_plane->base.base.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ipu_plane->dp && disable_dp_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ipu_dp_disable_channel(ipu_plane->dp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ipu_idmac_disable_channel(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ipu_plane->alpha_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ipu_idmac_disable_channel(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ipu_dmfc_disable_channel(ipu_plane->dmfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ipu_plane->dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ipu_dp_disable(ipu_plane->ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ipu_prg_present(ipu_plane->ipu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ipu_prg_channel_disable(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void ipu_plane_disable_deferred(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct ipu_plane *ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ipu_plane->disabling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ipu_plane->disabling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ipu_plane_disable(ipu_plane, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EXPORT_SYMBOL_GPL(ipu_plane_disable_deferred);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void ipu_plane_destroy(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct ipu_plane *ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) drm_plane_cleanup(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) kfree(ipu_plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void ipu_plane_state_reset(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int zpos = (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ipu_plane_state *ipu_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (plane->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ipu_state = to_ipu_plane_state(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __drm_atomic_helper_plane_destroy_state(plane->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) kfree(ipu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) plane->state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ipu_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ipu_state->base.zpos = zpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ipu_state->base.normalized_zpos = zpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct drm_plane_state *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ipu_plane_duplicate_state(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ipu_plane_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (WARN_ON(!plane->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) state = kmalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return &state->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void ipu_plane_destroy_state(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __drm_atomic_helper_plane_destroy_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) kfree(ipu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint32_t format, uint64_t modifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* linear is supported for all planes and formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (modifier == DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* without a PRG there are no supported modifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!ipu_prg_present(ipu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ipu_prg_format_supported(ipu, format, modifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct drm_plane_funcs ipu_plane_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .update_plane = drm_atomic_helper_update_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .disable_plane = drm_atomic_helper_disable_plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .destroy = ipu_plane_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .reset = ipu_plane_state_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .atomic_duplicate_state = ipu_plane_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .atomic_destroy_state = ipu_plane_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .format_mod_supported = ipu_plane_format_mod_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int ipu_plane_atomic_check(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct drm_plane_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct drm_plane_state *old_state = plane->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct drm_crtc_state *crtc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct device *dev = plane->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct drm_framebuffer *fb = state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct drm_framebuffer *old_fb = old_state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Ok to disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!fb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (WARN_ON(!state->crtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) crtc_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) drm_atomic_get_existing_crtc_state(state->state, state->crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (WARN_ON(!crtc_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = drm_atomic_helper_check_plane_state(state, crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DRM_PLANE_HELPER_NO_SCALING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DRM_PLANE_HELPER_NO_SCALING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) can_position, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* nothing to check when disabling or disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!crtc_state->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (plane->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case DRM_PLANE_TYPE_PRIMARY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* full plane minimum width is 13 pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (drm_rect_width(&state->dst) < 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case DRM_PLANE_TYPE_OVERLAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_warn(dev, "Unsupported plane type %d\n", plane->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (drm_rect_height(&state->dst) < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * We support resizing active plane or changing its format by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * forcing CRTC mode change in plane's ->atomic_check callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * and disabling all affected active planes in CRTC's ->atomic_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * callback. The planes will be reenabled in plane's ->atomic_update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (old_fb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) (drm_rect_width(&state->dst) != drm_rect_width(&old_state->dst) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) drm_rect_height(&state->dst) != drm_rect_height(&old_state->dst) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) fb->format != old_fb->format))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) eba = drm_plane_state_to_eba(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (eba & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (old_fb && fb->pitches[0] != old_fb->pitches[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (fb->format->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case DRM_FORMAT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case DRM_FORMAT_YVU420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case DRM_FORMAT_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case DRM_FORMAT_YVU422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case DRM_FORMAT_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case DRM_FORMAT_YVU444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Multiplanar formats have to meet the following restrictions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * - EBA, UBO and VBO are a multiple of 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * - UBO and VBO are unsigned and not larger than 0xfffff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * - Only EBA may be changed while scanout is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * - The strides of U and V planes must be identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) vbo = drm_plane_state_to_vbo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (vbo & 0x7 || vbo > 0xfffff8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (old_fb && (fb->format == old_fb->format)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) old_vbo = drm_plane_state_to_vbo(old_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (vbo != old_vbo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (fb->pitches[1] != fb->pitches[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case DRM_FORMAT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case DRM_FORMAT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ubo = drm_plane_state_to_ubo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ubo & 0x7 || ubo > 0xfffff8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (old_fb && (fb->format == old_fb->format)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) old_ubo = drm_plane_state_to_ubo(old_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ubo != old_ubo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (old_fb && old_fb->pitches[1] != fb->pitches[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * The x/y offsets must be even in case of horizontal/vertical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * chroma subsampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (((state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ((state->src.y1 >> 16) & (fb->format->vsub - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case DRM_FORMAT_RGB565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case DRM_FORMAT_BGR565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case DRM_FORMAT_RGB888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case DRM_FORMAT_BGR888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case DRM_FORMAT_RGBX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case DRM_FORMAT_BGRX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) alpha_eba = drm_plane_state_to_eba(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (alpha_eba & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (old_fb && old_fb->pitches[1] != fb->pitches[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void ipu_plane_atomic_disable(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct ipu_plane *ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ipu_plane->dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ipu_dp_disable_channel(ipu_plane->dp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ipu_plane->disabling = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int ipu_chan_assign_axi_id(int ipu_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) switch (ipu_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case IPUV3_CHANNEL_MEM_BG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case IPUV3_CHANNEL_MEM_FG_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case IPUV3_CHANNEL_MEM_DC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 *burstsize, u8 *num_bursts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const unsigned int width_bytes = width * cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int npb, bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Maximum number of pixels per burst without overshooting stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for (npb = 64 / cpp; npb > 0; --npb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (round_up(width_bytes, npb * cpp) <= stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *burstsize = npb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Maximum number of consecutive bursts without overshooting stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (bursts = 8; bursts > 1; bursts /= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (round_up(width_bytes, npb * cpp * bursts) <= stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *num_bursts = bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void ipu_plane_atomic_update(struct drm_plane *plane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct drm_plane_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ipu_plane *ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct drm_plane_state *state = plane->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct drm_crtc_state *crtc_state = state->crtc->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct drm_framebuffer *fb = state->fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct drm_rect *dst = &state->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long eba, ubo, vbo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned long alpha_eba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) enum ipu_color_space ics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int axi_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) const struct drm_format_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 burstsize, num_bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) switch (ipu_plane->dp_flow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case IPU_DP_FLOW_SYNC_BG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (state->normalized_zpos == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ipu_dp_set_global_alpha(ipu_plane->dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) !fb->format->has_alpha, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case IPU_DP_FLOW_SYNC_FG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (state->normalized_zpos == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ipu_dp_set_global_alpha(ipu_plane->dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) !fb->format->has_alpha, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) eba = drm_plane_state_to_eba(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Configure PRG channel and attached PRE, this changes the EBA to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * internal SRAM location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ipu_state->use_pre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) drm_rect_width(&state->src) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) drm_rect_height(&state->src) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) fb->pitches[0], fb->format->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) fb->modifier, &eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* nothing to do if PRE is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ipu_state->use_pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ipu_plane_separate_alpha(ipu_plane)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) alpha_eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (ipu_plane->dp_flow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case IPU_DP_FLOW_SYNC_BG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ipu_dp_setup_channel(ipu_plane->dp, ics, IPUV3_COLORSPACE_RGB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case IPU_DP_FLOW_SYNC_FG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ipu_dp_setup_channel(ipu_plane->dp, ics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) IPUV3_COLORSPACE_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) width = drm_rect_width(&state->src) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) height = drm_rect_height(&state->src) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) info = drm_format_info(fb->format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &burstsize, &num_bursts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ipu_cpmem_zero(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) switch (fb->format->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case DRM_FORMAT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case DRM_FORMAT_YVU420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case DRM_FORMAT_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case DRM_FORMAT_YVU422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case DRM_FORMAT_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case DRM_FORMAT_YVU444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ubo = drm_plane_state_to_ubo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) vbo = drm_plane_state_to_vbo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (fb->format->format == DRM_FORMAT_YVU420 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fb->format->format == DRM_FORMAT_YVU422 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fb->format->format == DRM_FORMAT_YVU444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) swap(ubo, vbo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fb->pitches[1], ubo, vbo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_dbg(ipu_plane->base.dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) state->src.x1 >> 16, state->src.y1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case DRM_FORMAT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case DRM_FORMAT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ubo = drm_plane_state_to_ubo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) fb->pitches[1], ubo, ubo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_dbg(ipu_plane->base.dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "phy = %lu %lu, x = %d, y = %d", eba, ubo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->src.x1 >> 16, state->src.y1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case DRM_FORMAT_RGB565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case DRM_FORMAT_BGR565_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case DRM_FORMAT_RGB888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case DRM_FORMAT_BGR888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case DRM_FORMAT_RGBX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case DRM_FORMAT_BGRX8888_A8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) alpha_eba = drm_plane_state_to_eba(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) num_bursts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) eba, alpha_eba, state->src.x1 >> 16, state->src.y1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ipu_cpmem_zero(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) drm_rect_width(&state->src) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) drm_rect_height(&state->src) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) eba, state->src.x1 >> 16, state->src.y1 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ipu_plane_enable(ipu_plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .prepare_fb = drm_gem_fb_prepare_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .atomic_check = ipu_plane_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .atomic_disable = ipu_plane_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .atomic_update = ipu_plane_atomic_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct ipu_plane *ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct drm_plane_state *state = plane->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* disabled crtcs must not block the update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!state->crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ipu_state->use_pre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Pretend no update is pending in the non-PRE/PRG case. For this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * happen, an atomic update would have to be deferred until after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * start of the next frame and simultaneously interrupt latency would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * have to be high enough to let the atomic update finish and issue an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * event before the previous end of frame interrupt handler can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int ipu_planes_assign_pre(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct drm_atomic_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct drm_crtc_state *old_crtc_state, *crtc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct drm_plane_state *plane_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct ipu_plane_state *ipu_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ipu_plane *ipu_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct drm_crtc *crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int available_pres = ipu_prg_max_active_channels();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = drm_atomic_add_affected_planes(state, crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * We are going over the planes in 2 passes: first we assign PREs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * planes with a tiling modifier, which need the PREs to resolve into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * linear. Any failure to assign a PRE there is fatal. In the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * pass we try to assign PREs to linear FBs, to improve memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * patterns for them. Failure at this point is non-fatal, as we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * scan out linear FBs without a PRE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) for_each_new_plane_in_state(state, plane, plane_state, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ipu_state = to_ipu_plane_state(plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!plane_state->fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ipu_state->use_pre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!ipu_prg_format_supported(ipu_plane->ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) plane_state->fb->format->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) plane_state->fb->modifier))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ipu_state->use_pre = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) available_pres--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for_each_new_plane_in_state(state, plane, plane_state, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ipu_state = to_ipu_plane_state(plane_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ipu_plane = to_ipu_plane(plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!plane_state->fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ipu_state->use_pre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* make sure that modifier is initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ipu_prg_format_supported(ipu_plane->ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) plane_state->fb->format->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) plane_state->fb->modifier)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ipu_state->use_pre = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) available_pres--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ipu_state->use_pre = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) EXPORT_SYMBOL_GPL(ipu_planes_assign_pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int dma, int dp, unsigned int possible_crtcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) enum drm_plane_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct ipu_plane *ipu_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const uint64_t *modifiers = ipu_format_modifiers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dma, dp, possible_crtcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!ipu_plane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DRM_ERROR("failed to allocate plane\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ipu_plane->ipu = ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ipu_plane->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ipu_plane->dp_flow = dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ipu_prg_present(ipu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) modifiers = pre_format_modifiers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &ipu_plane_funcs, ipu_plane_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ARRAY_SIZE(ipu_plane_formats),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) modifiers, type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DRM_ERROR("failed to initialize plane\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) kfree(ipu_plane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) drm_plane_create_zpos_immutable_property(&ipu_plane->base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ipu_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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