Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * i.MX IPUv3 Graphics driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Sascha Hauer, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_fb_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_gem_cma_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_vblank.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "imx-drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "ipuv3-plane.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRIVER_DESC		"i.MX IPUv3 Graphics"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct ipu_crtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct drm_crtc		base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* plane[0] is the full plane, plane[1] is the partial plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct ipu_plane	*plane[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct ipu_dc		*dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct ipu_di		*di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct drm_pending_vblank_event *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return container_of(crtc, struct ipu_crtc, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				   struct drm_crtc_state *old_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ipu_prg_enable(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	ipu_dc_enable(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ipu_dc_enable_channel(ipu_crtc->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ipu_di_enable(ipu_crtc->di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				    struct drm_crtc_state *old_crtc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bool disable_partial = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	bool disable_full = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct drm_plane *plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		if (plane == &ipu_crtc->plane[0]->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			disable_full = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			disable_partial = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (disable_partial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		ipu_plane_disable(ipu_crtc->plane[1], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (disable_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		ipu_plane_disable(ipu_crtc->plane[0], true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				    struct drm_crtc_state *old_crtc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ipu_dc_disable_channel(ipu_crtc->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ipu_di_disable(ipu_crtc->di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * Planes must be disabled before DC clock is removed, as otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * attached IDMACs will be left in undefined state, possibly hanging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * the IPU or even system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ipu_dc_disable(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ipu_prg_disable(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	drm_crtc_vblank_off(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	spin_lock_irq(&crtc->dev->event_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (crtc->state->event && !crtc->state->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		crtc->state->event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	spin_unlock_irq(&crtc->dev->event_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void imx_drm_crtc_reset(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct imx_crtc_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (crtc->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	kfree(to_imx_crtc_state(crtc->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	crtc->state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		__drm_atomic_helper_crtc_reset(crtc, &state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct imx_crtc_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	WARN_ON(state->base.crtc != crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	state->base.crtc = crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return &state->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				       struct drm_crtc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	__drm_atomic_helper_crtc_destroy_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	kfree(to_imx_crtc_state(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int ipu_enable_vblank(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	enable_irq(ipu_crtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void ipu_disable_vblank(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	disable_irq_nosync(ipu_crtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct drm_crtc_funcs ipu_crtc_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.set_config = drm_atomic_helper_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.destroy = drm_crtc_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.page_flip = drm_atomic_helper_page_flip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.reset = imx_drm_crtc_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.atomic_destroy_state = imx_drm_crtc_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.enable_vblank = ipu_enable_vblank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.disable_vblank = ipu_disable_vblank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct ipu_crtc *ipu_crtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct drm_crtc *crtc = &ipu_crtc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	drm_crtc_handle_vblank(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ipu_crtc->event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			struct ipu_plane *plane = ipu_crtc->plane[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			if (!plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			if (ipu_plane_atomic_update_pending(&plane->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (i == ARRAY_SIZE(ipu_crtc->plane)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			spin_lock_irqsave(&crtc->dev->event_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			ipu_crtc->event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			drm_crtc_vblank_put(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				  const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				  struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct videomode vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	drm_display_mode_to_videomode(adjusted_mode, &vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	drm_display_mode_from_videomode(&vm, adjusted_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				 struct drm_crtc_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 primary_plane_mask = drm_plane_mask(crtc->primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (state->active && (primary_plane_mask & state->plane_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				  struct drm_crtc_state *old_crtc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	drm_crtc_vblank_on(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				  struct drm_crtc_state *old_crtc_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	spin_lock_irq(&crtc->dev->event_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (crtc->state->event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		WARN_ON(drm_crtc_vblank_get(crtc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		ipu_crtc->event = crtc->state->event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		crtc->state->event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	spin_unlock_irq(&crtc->dev->event_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct drm_device *dev = crtc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct drm_encoder *encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct ipu_di_signal_cfg sig_cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	unsigned long encoder_types = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (encoder->crtc == crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			encoder_types |= BIT(encoder->encoder_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		__func__, encoder_types);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * If we have DAC or LDB, then we need the IPU DI clock to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 * clock from 27 MHz TVE_DI clock, but allow to divide it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			     BIT(DRM_MODE_ENCODER_LVDS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		sig_cfg.clkflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* Default to driving pixel data on negative clock edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			     DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	sig_cfg.bus_format = imx_crtc_state->bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	sig_cfg.v_to_h_sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	drm_display_mode_to_videomode(mode, &sig_cfg.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			 mode->flags & DRM_MODE_FLAG_INTERLACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			 imx_crtc_state->bus_format, mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.mode_fixup = ipu_crtc_mode_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.mode_set_nofb = ipu_crtc_mode_set_nofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.atomic_check = ipu_crtc_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.atomic_begin = ipu_crtc_atomic_begin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.atomic_flush = ipu_crtc_atomic_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.atomic_disable = ipu_crtc_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.atomic_enable = ipu_crtc_atomic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		ipu_dc_put(ipu_crtc->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (!IS_ERR_OR_NULL(ipu_crtc->di))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		ipu_di_put(ipu_crtc->di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		struct ipu_client_platformdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (IS_ERR(ipu_crtc->dc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		ret = PTR_ERR(ipu_crtc->dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (IS_ERR(ipu_crtc->di)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		ret = PTR_ERR(ipu_crtc->di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ipu_put_resources(ipu_crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct ipu_client_platformdata *pdata, struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	struct drm_crtc *crtc = &ipu_crtc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int dp = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ret = ipu_get_resources(ipu_crtc, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (pdata->dp >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		dp = IPU_DP_FLOW_SYNC_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 					    DRM_PLANE_TYPE_PRIMARY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (IS_ERR(ipu_crtc->plane[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		ret = PTR_ERR(ipu_crtc->plane[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		goto err_put_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	crtc->port = pdata->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	drm_crtc_helper_add(crtc, &ipu_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 				  &ipu_crtc_funcs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		goto err_put_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	/* If this crtc is using the DP, add an overlay plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 						IPU_DP_FLOW_SYNC_FG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 						drm_crtc_mask(&ipu_crtc->base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 						DRM_PLANE_TYPE_OVERLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		if (IS_ERR(ipu_crtc->plane[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			ipu_crtc->plane[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				dev_err(ipu_crtc->dev, "getting plane 1 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 					"resources failed with %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 				goto err_put_plane0_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			"imx_drm", ipu_crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		goto err_put_plane1_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	/* Only enable IRQ when we actually need it to trigger work. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	disable_irq(ipu_crtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) err_put_plane1_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (ipu_crtc->plane[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		ipu_plane_put_resources(ipu_crtc->plane[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err_put_plane0_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	ipu_plane_put_resources(ipu_crtc->plane[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err_put_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	ipu_put_resources(ipu_crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct ipu_client_platformdata *pdata = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	struct drm_device *drm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	struct ipu_crtc *ipu_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	ipu_crtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	memset(ipu_crtc, 0, sizeof(*ipu_crtc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	ipu_crtc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	return ipu_crtc_init(ipu_crtc, pdata, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void ipu_drm_unbind(struct device *dev, struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	ipu_put_resources(ipu_crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (ipu_crtc->plane[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		ipu_plane_put_resources(ipu_crtc->plane[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	ipu_plane_put_resources(ipu_crtc->plane[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct component_ops ipu_crtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.bind = ipu_drm_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	.unbind = ipu_drm_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int ipu_drm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	struct ipu_crtc *ipu_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	if (!dev->platform_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	if (!ipu_crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	dev_set_drvdata(dev, ipu_crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return component_add(dev, &ipu_crtc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int ipu_drm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	component_del(&pdev->dev, &ipu_crtc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct platform_driver ipu_drm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		.name = "imx-ipuv3-crtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	.probe = ipu_drm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	.remove = ipu_drm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };