^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX drm driver - Television Encoder (TVEv2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Philipp Zabel, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <video/imx-ipu-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "imx-drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TVE_COM_CONF_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TVE_TVDAC0_CONT_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TVE_TVDAC1_CONT_REG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TVE_TVDAC2_CONT_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TVE_CD_CONT_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TVE_INT_CONT_REG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TVE_STAT_REG 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TVE_TST_MODE_REG 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TVE_MV_CONT_REG 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* TVE_COM_CONF_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TVE_SYNC_CH_2_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TVE_SYNC_CH_1_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TVE_SYNC_CH_0_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TVE_TV_OUT_DISABLE (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TVE_TV_OUT_YPBPR (0x6 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TVE_TV_OUT_RGB (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TVE_TV_STAND_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TVE_P2I_CONV_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TVE_INP_VIDEO_FORM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TVE_INP_YCBCR_422 (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TVE_INP_YCBCR_444 (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TVE_DATA_SOURCE_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TVE_DATA_SOURCE_EXT (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TVE_IPU_CLK_EN_OFS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TVE_IPU_CLK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TVE_DAC_SAMP_RATE_OFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TVE_DAC_SAMP_RATE_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TVE_DAC_FULL_RATE (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TVE_DAC_DIV2_RATE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TVE_DAC_DIV4_RATE (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TVE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* TVE_TVDACx_CONT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* TVE_CD_CONT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TVE_CD_CH_2_SM_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TVE_CD_CH_1_SM_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TVE_CD_CH_0_SM_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TVE_CD_CH_2_LM_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TVE_CD_CH_1_LM_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TVE_CD_CH_0_LM_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TVE_CD_CH_2_REF_LVL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TVE_CD_CH_1_REF_LVL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TVE_CD_CH_0_REF_LVL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TVE_CD_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* TVE_INT_CONT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TVE_FRAME_END_IEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TVE_CD_MON_END_IEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TVE_CD_SM_IEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TVE_CD_LM_IEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* TVE_TST_MODE_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX_TVE_DAC_VOLTAGE 2750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TVE_MODE_TVOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) TVE_MODE_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct imx_tve {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct drm_encoder encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int di_hsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int di_vsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regulator *dac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct i2c_adapter *ddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk *di_sel_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_hw clk_hw_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *di_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline struct imx_tve *con_to_tve(struct drm_connector *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return container_of(c, struct imx_tve, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return container_of(e, struct imx_tve, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void tve_enable(struct imx_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_prepare_enable(tve->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* clear interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (tve->mode == TVE_MODE_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) regmap_write(tve->regmap, TVE_INT_CONT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) TVE_CD_SM_IEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) TVE_CD_LM_IEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) TVE_CD_MON_END_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void tve_disable(struct imx_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_disable_unprepare(tve->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int tve_setup_tvout(struct imx_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int tve_setup_vga(struct imx_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) TVE_TVDAC_GAIN_MASK, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TVE_TVDAC_GAIN_MASK, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TVE_TVDAC_GAIN_MASK, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* set configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val |= TVE_TV_STAND_HD_1080P30 | 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* set test mode (as documented) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TVE_TVDAC_TEST_MODE_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int imx_tve_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct imx_tve *tve = con_to_tve(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!tve->ddc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) edid = drm_get_edid(connector, tve->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) drm_connector_update_edid_property(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = drm_add_edid_modes(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int imx_tve_connector_mode_valid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct imx_tve *tve = con_to_tve(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* pixel clock with 2x oversampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (rate == mode->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* pixel clock without oversampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (rate == mode->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_warn(tve->dev, "ignoring mode %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mode->hdisplay, mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct drm_display_mode *orig_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct imx_tve *tve = enc_to_tve(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long rounded_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * we should try 4k * mode->clock first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * and enable 4x oversampling for lower resolutions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rate = 2000UL * mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_set_rate(tve->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rounded_rate = clk_get_rate(tve->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (rounded_rate >= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_set_rate(tve->di_clk, rounded_rate / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (tve->mode == TVE_MODE_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = tve_setup_vga(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = tve_setup_tvout(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(tve->dev, "failed to set configuration: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void imx_tve_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct imx_tve *tve = enc_to_tve(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tve_enable(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void imx_tve_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct imx_tve *tve = enc_to_tve(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tve_disable(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int imx_tve_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct imx_tve *tve = enc_to_tve(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct drm_connector_funcs imx_tve_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .destroy = imx_drm_connector_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .get_modes = imx_tve_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .mode_valid = imx_tve_connector_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .mode_set = imx_tve_encoder_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .enable = imx_tve_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .disable = imx_tve_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .atomic_check = imx_tve_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static irqreturn_t imx_tve_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct imx_tve *tve = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regmap_read(tve->regmap, TVE_STAT_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* clear interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (val & TVE_DAC_SAMP_RATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case TVE_DAC_DIV4_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return parent_rate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case TVE_DAC_DIV2_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case TVE_DAC_FULL_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) div = *prate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (div >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return *prate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else if (div >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return *prate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (div >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) val = TVE_DAC_DIV4_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) else if (div >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) val = TVE_DAC_DIV2_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val = TVE_DAC_FULL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) TVE_DAC_SAMP_RATE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(tve->dev, "failed to set divider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct clk_ops clk_tve_di_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .round_rate = clk_tve_di_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .set_rate = clk_tve_di_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .recalc_rate = clk_tve_di_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const char *tve_di_parent[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "tve_di",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .ops = &clk_tve_di_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tve_di_parent[0] = __clk_get_name(tve->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) init.parent_names = (const char **)&tve_di_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tve->clk_hw_di.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (IS_ERR(tve->di_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PTR_ERR(tve->di_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return PTR_ERR(tve->di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int encoder_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) encoder_type = tve->mode == TVE_MODE_VGA ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) drm_simple_encoder_init(drm, &tve->encoder, encoder_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) drm_connector_helper_add(&tve->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &imx_tve_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) drm_connector_init_with_ddc(drm, &tve->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &imx_tve_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DRM_MODE_CONNECTOR_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tve->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) drm_connector_attach_encoder(&tve->connector, &tve->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void imx_tve_disable_regulator(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct imx_tve *tve = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regulator_disable(tve->dac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return (reg % 4 == 0) && (reg <= 0xdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct regmap_config tve_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .readable_reg = imx_tve_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .max_register = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char * const imx_tve_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [TVE_MODE_TVOUT] = "tvout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [TVE_MODE_VGA] = "vga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int of_get_tve_mode(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const char *bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = of_property_read_string(np, "fsl,tve-mode", &bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!strcasecmp(bm, imx_tve_modes[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int imx_tve_bind(struct device *dev, struct device *master, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct drm_device *drm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct device_node *ddc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct imx_tve *tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tve = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) memset(tve, 0, sizeof(*tve));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tve->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ddc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) of_node_put(ddc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tve->mode = of_get_tve_mode(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (tve->mode != TVE_MODE_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(dev, "only VGA mode supported, currently\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (tve->mode == TVE_MODE_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = of_property_read_u32(np, "fsl,hsync-pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &tve->di_hsync_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dev, "failed to get hsync pin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = of_property_read_u32(np, "fsl,vsync-pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &tve->di_vsync_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(dev, "failed to get vsync pin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) tve_regmap_config.lock_arg = tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &tve_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (IS_ERR(tve->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PTR_ERR(tve->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return PTR_ERR(tve->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = devm_request_threaded_irq(dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) imx_tve_irq_handler, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "imx-tve", tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tve->dac_reg = devm_regulator_get(dev, "dac");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!IS_ERR(tve->dac_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = regulator_enable(tve->dac_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tve->clk = devm_clk_get(dev, "tve");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (IS_ERR(tve->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(dev, "failed to get high speed tve clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PTR_ERR(tve->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return PTR_ERR(tve->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* this is the IPU DI clock input selector, can be parented to tve_di */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tve->di_sel_clk = devm_clk_get(dev, "di_sel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (IS_ERR(tve->di_sel_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(dev, "failed to get ipu di mux clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PTR_ERR(tve->di_sel_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return PTR_ERR(tve->di_sel_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = tve_clk_init(tve, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "failed to read configuration register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (val != 0x00100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* disable cable detection for VGA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = imx_tve_register(drm, tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct component_ops imx_tve_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .bind = imx_tve_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int imx_tve_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct imx_tve *tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) platform_set_drvdata(pdev, tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return component_add(&pdev->dev, &imx_tve_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int imx_tve_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) component_del(&pdev->dev, &imx_tve_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct of_device_id imx_tve_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { .compatible = "fsl,imx53-tve", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct platform_driver imx_tve_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .probe = imx_tve_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .remove = imx_tve_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .of_match_table = imx_tve_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .name = "imx-tve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) module_platform_driver(imx_tve_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MODULE_DESCRIPTION("i.MX Television Encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MODULE_AUTHOR("Philipp Zabel, Pengutronix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_ALIAS("platform:imx-tve");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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