^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX drm driver - LVDS display bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Sascha Hauer, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <video/of_display_timing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <video/of_videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "imx-drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_NAME "imx-ldb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LDB_CH0_MODE_EN_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LDB_CH1_MODE_EN_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LDB_SPLIT_MODE_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LDB_BGREF_RMODE_INT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct imx_ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct imx_ldb_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct imx_ldb *ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct drm_encoder encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Defines what is connected to the ldb, only one at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct drm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct i2c_adapter *ddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int chno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int mode_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return container_of(c, struct imx_ldb_channel, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return container_of(e, struct imx_ldb_channel, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct bus_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct imx_ldb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct imx_ldb_channel channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *clk[2]; /* our own clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *clk_sel[4]; /* parent of display clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk_parent[4]; /* original parent of clk_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *clk_pll[2]; /* upstream clock we can adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 ldb_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct bus_mux *lvds_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 bus_format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct imx_ldb *ldb = imx_ldb_ch->ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (bus_format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (imx_ldb_ch->chno == 0 || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (imx_ldb_ch->chno == 1 || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (imx_ldb_ch->chno == 0 || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LDB_BIT_MAP_CH0_JEIDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (imx_ldb_ch->chno == 1 || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LDB_BIT_MAP_CH1_JEIDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int imx_ldb_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) num_modes = drm_panel_get_modes(imx_ldb_ch->panel, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (num_modes > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (imx_ldb_ch->edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) drm_connector_update_edid_property(connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) imx_ldb_ch->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (imx_ldb_ch->mode_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mode = drm_mode_create(connector->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) drm_mode_copy(mode, &imx_ldb_ch->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) drm_mode_probed_add(connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) num_modes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long serial_clk, unsigned long di_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_get_rate(ldb->clk_pll[chno]), serial_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_set_rate(ldb->clk_pll[chno], serial_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk_get_rate(ldb->clk_pll[chno]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk_get_rate(ldb->clk[chno]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (long int)di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk_set_rate(ldb->clk[chno], di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_get_rate(ldb->clk[chno]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* set display clock mux to LDB input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(ldb->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "unable to set di%d parent clock to ldb_di%d\n", mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct imx_ldb *ldb = imx_ldb_ch->ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) drm_panel_prepare(imx_ldb_ch->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_prepare_enable(ldb->clk[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_prepare_enable(ldb->clk[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (imx_ldb_ch == &ldb->channel[0] || dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (mux == 0 || ldb->lvds_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else if (mux == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (imx_ldb_ch == &ldb->channel[1] || dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (mux == 1 || ldb->lvds_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else if (mux == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ldb->lvds_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct bus_mux *lvds_mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (imx_ldb_ch == &ldb->channel[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) lvds_mux = &ldb->lvds_mux[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else if (imx_ldb_ch == &ldb->channel[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) lvds_mux = &ldb->lvds_mux[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mux << lvds_mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) drm_panel_enable(imx_ldb_ch->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct drm_connector_state *connector_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct drm_display_mode *mode = &crtc_state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct imx_ldb *ldb = imx_ldb_ch->ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long serial_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long di_clk = mode->clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 bus_format = imx_ldb_ch->bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_warn(ldb->dev, "%s: invalid mux %d\n", __func__, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (mode->clock > 170000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_warn(ldb->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "%s: mode exceeds 170 MHz pixel clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (mode->clock > 85000 && !dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_warn(ldb->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "%s: mode exceeds 85 MHz pixel clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) serial_clk = 3500UL * mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) serial_clk = 7000UL * mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) di_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (imx_ldb_ch == &ldb->channel[0] || dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (mode->flags & DRM_MODE_FLAG_NVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (imx_ldb_ch == &ldb->channel[1] || dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (mode->flags & DRM_MODE_FLAG_NVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!bus_format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct drm_connector *connector = connector_state->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct drm_display_info *di = &connector->display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (di->num_bus_formats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bus_format = di->bus_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct imx_ldb *ldb = imx_ldb_ch->ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int mux, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) drm_panel_disable(imx_ldb_ch->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (imx_ldb_ch == &ldb->channel[0] || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (imx_ldb_ch == &ldb->channel[1] || dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk_disable_unprepare(ldb->clk[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk_disable_unprepare(ldb->clk[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ldb->lvds_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct bus_mux *lvds_mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (imx_ldb_ch == &ldb->channel[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lvds_mux = &ldb->lvds_mux[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else if (imx_ldb_ch == &ldb->channel[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) lvds_mux = &ldb->lvds_mux[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_read(ldb->regmap, lvds_mux->reg, &mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mux &= lvds_mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mux >>= lvds_mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* set display clock mux back to original input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(ldb->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "unable to set di%d parent clock to original parent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) drm_panel_unprepare(imx_ldb_ch->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct drm_display_info *di = &conn_state->connector->display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 bus_format = imx_ldb_ch->bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Bus format description in DT overrides connector display info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!bus_format && di->num_bus_formats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bus_format = di->bus_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) imx_crtc_state->bus_flags = di->bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bus_format = imx_ldb_ch->bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) switch (bus_format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) imx_crtc_state->di_hsync_pin = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) imx_crtc_state->di_vsync_pin = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct drm_connector_funcs imx_ldb_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .destroy = imx_drm_connector_destroy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .get_modes = imx_ldb_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .enable = imx_ldb_encoder_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .disable = imx_ldb_encoder_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .atomic_check = imx_ldb_encoder_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) char clkname[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) snprintf(clkname, sizeof(clkname), "di%d", chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (IS_ERR(ldb->clk[chno]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PTR_ERR(ldb->clk[chno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int imx_ldb_register(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct imx_ldb_channel *imx_ldb_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct imx_ldb *ldb = imx_ldb_ch->ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct drm_encoder *encoder = &imx_ldb_ch->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = imx_ldb_get_clk(ldb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_LVDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (imx_ldb_ch->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = drm_bridge_attach(&imx_ldb_ch->encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) imx_ldb_ch->bridge, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DRM_ERROR("Failed to initialize bridge with drm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * We want to add the connector whenever there is no bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * that brings its own, not only when there is a panel. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * historical reasons, the ldb driver can also work without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * a panel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) drm_connector_helper_add(&imx_ldb_ch->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &imx_ldb_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &imx_ldb_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DRM_MODE_CONNECTOR_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) imx_ldb_ch->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct imx_ldb_bit_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 datawidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const char * const mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static u32 of_get_bus_format(struct device *dev, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const char *bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 datawidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = of_property_read_string(np, "fsl,data-mapping", &bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) of_property_read_u32(np, "fsl,data-width", &datawidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) datawidth == imx_ldb_bit_mappings[i].datawidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return imx_ldb_bit_mappings[i].bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct bus_mux imx6q_lvds_mux[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .reg = IOMUXC_GPR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .reg = IOMUXC_GPR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * of_match_device will walk through this list and take the first entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * matching any of its compatible values. Therefore, the more generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * entries (in this case fsl,imx53-ldb) need to be ordered last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct of_device_id imx_ldb_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { .compatible = "fsl,imx53-ldb", .data = NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int imx_ldb_panel_ddc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct imx_ldb_channel *channel, struct device_node *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct device_node *ddc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const u8 *edidp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ddc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) of_node_put(ddc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!channel->ddc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_warn(dev, "failed to get ddc i2c adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!channel->ddc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int edid_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* if no DDC available, fallback to hardcoded EDID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(dev, "no ddc available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) edidp = of_get_property(child, "edid", &edid_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (edidp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else if (!channel->panel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* fallback to display-timings node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = of_get_drm_display_mode(child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &channel->mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &channel->bus_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) OF_USE_NATIVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) channel->mode_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct drm_device *drm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) of_match_device(imx_ldb_dt_ids, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct imx_ldb *imx_ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int dual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) imx_ldb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memset(imx_ldb, 0, sizeof(*imx_ldb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(imx_ldb->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(dev, "failed to get parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return PTR_ERR(imx_ldb->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* disable LDB by resetting the control register to POR default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) imx_ldb->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) imx_ldb->lvds_mux = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dual = of_property_read_bool(np, "fsl,dual-channel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * There are three different possible clock mux configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * i.MX53: ipu1_di0_sel, ipu1_di1_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Map them all to di0_sel...di3_sel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) char clkname[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) sprintf(clkname, "di%d_sel", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (IS_ERR(imx_ldb->clk_sel[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = PTR_ERR(imx_ldb->clk_sel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) imx_ldb->clk_sel[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct imx_ldb_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = of_property_read_u32(child, "reg", &i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret || i < 0 || i > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto free_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!of_device_is_available(child))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (dual && i > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_warn(dev, "dual-channel mode, ignoring second output\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) channel = &imx_ldb->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) channel->ldb = imx_ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) channel->chno = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * The output port is port@4 with an external 4-port mux or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * port@2 with the internal 2-port mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret = drm_of_find_panel_or_bridge(child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) imx_ldb->lvds_mux ? 4 : 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &channel->panel, &channel->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret && ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) goto free_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* panel ddc only if there is no bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!channel->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = imx_ldb_panel_ddc(dev, channel, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto free_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bus_format = of_get_bus_format(dev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (bus_format == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * If no bus format was specified in the device tree,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * we can still get it from the connected panel later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (channel->panel && channel->panel->funcs &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) channel->panel->funcs->get_modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) bus_format = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (bus_format < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "could not determine data mapping: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) bus_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto free_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) channel->bus_format = bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) channel->child = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = imx_ldb_register(drm, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) channel->child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto free_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) free_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void imx_ldb_unbind(struct device *dev, struct device *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct imx_ldb_channel *channel = &imx_ldb->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) kfree(channel->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) i2c_put_adapter(channel->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct component_ops imx_ldb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .bind = imx_ldb_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .unbind = imx_ldb_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int imx_ldb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct imx_ldb *imx_ldb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) imx_ldb = devm_kzalloc(&pdev->dev, sizeof(*imx_ldb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!imx_ldb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) platform_set_drvdata(pdev, imx_ldb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return component_add(&pdev->dev, &imx_ldb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int imx_ldb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) component_del(&pdev->dev, &imx_ldb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct platform_driver imx_ldb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .probe = imx_ldb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .remove = imx_ldb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .of_match_table = imx_ldb_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) module_platform_driver(imx_ldb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MODULE_DESCRIPTION("i.MX LVDS driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MODULE_AUTHOR("Sascha Hauer, Pengutronix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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