^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _IMX_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _IMX_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) struct drm_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) struct drm_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) struct drm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct drm_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct drm_encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct drm_framebuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct drm_plane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct imx_crtc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct drm_crtc_state base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 bus_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 bus_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int di_hsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int di_vsync_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static inline struct imx_crtc_state *to_imx_crtc_state(struct drm_crtc_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return container_of(s, struct imx_crtc_state, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int imx_drm_init_drm(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int preferred_bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int imx_drm_exit_drm(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern struct platform_driver ipu_drm_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void imx_drm_mode_config_init(struct drm_device *drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int imx_drm_encoder_parse_of(struct drm_device *drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct drm_encoder *encoder, struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void imx_drm_connector_destroy(struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int ipu_planes_assign_pre(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct drm_atomic_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* _IMX_DRM_H_ */