^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2007-2011, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) struct psb_intel_mode_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* MID device specific descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct oaktrail_timing_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) u16 pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u8 hactive_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u8 hblank_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 hblank_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 hactive_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 vactive_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 vblank_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 vblank_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 vactive_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 hsync_offset_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 hsync_pulse_width_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 vsync_pulse_width_lo:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 vsync_offset_lo:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 vsync_pulse_width_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 vsync_offset_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 hsync_pulse_width_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 hsync_offset_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 width_mm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 height_mm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 height_mm_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 width_mm_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 hborder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 vborder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 unknown0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 hsync_positive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 vsync_positive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 separate_sync:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 stereo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 unknown6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 interlaced:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct gct_r10_timing_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 hactive_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 hactive_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 hblank_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 hblank_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 hsync_offset_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 hsync_offset_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 hsync_pulse_width_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 hsync_pulse_width_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 hsync_positive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 rsvd_1:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 vactive_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 vactive_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 vblank_lo:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 vblank_hi:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 vsync_offset_lo:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u16 vsync_offset_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 vsync_pulse_width_lo:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 vsync_pulse_width_hi:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 vsync_positive:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 rsvd_2:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct oaktrail_panel_descriptor_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 0x61190 if MIPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Register 0x61210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 Panel_MIPI_Display_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*16 bits, Defined as follows: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* if MIPI, 0x0000 if LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Bit 0, Type, 2 bits, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* 0: Type-1, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 1: Type-2, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* 2: Type-3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 3: Type-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Bit 2, Pixel Format, 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Bit0: 16bpp (not supported in LNC), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Bit1: 18bpp loosely packed, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Bit2: 18bpp packed, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Bit3: 24bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Bit 6, Reserved, 2 bits, 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Bit 14, Reserved, 2 bits, 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct oaktrail_panel_descriptor_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 0x61190 if MIPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Register 0x61210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 Panel_MIPI_Display_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*16 bits, Defined as follows: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* if MIPI, 0x0000 if LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Bit 0, Type, 2 bits, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 0: Type-1, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 1: Type-2, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 2: Type-3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 3: Type-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Bit 2, Pixel Format, 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Bit0: 16bpp (not supported in LNC), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Bit1: 18bpp loosely packed, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Bit2: 18bpp packed, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Bit3: 24bpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Bit 6, Reserved, 2 bits, 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Bit 14, Reserved, 2 bits, 00b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) union oaktrail_panel_rx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 1: Burst and non-burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* 2/3: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 Rsvd:5;/*5 bits,00000b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } panelrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 panel_receiver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct gct_r0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) union { /*8 bits,Defined as follows: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 PanelType:4; /*4 bits, Bit field for panels*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* 0 - 3: 0 = LVDS, 1 = MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*2 bits,Specifies which of the*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 BootPanelIndex:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 4 panels to use by default*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* the 4 MIPI DSI receivers to use*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 PanelDescriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct gct_r1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) union { /*8 bits,Defined as follows: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 PanelType:4; /*4 bits, Bit field for panels*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 0 - 3: 0 = LVDS, 1 = MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*2 bits,Specifies which of the*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 BootPanelIndex:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* 4 panels to use by default*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* the 4 MIPI DSI receivers to use*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } PD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 PanelDescriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct gct_r10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct gct_r10_timing_info DTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 Panel_MIPI_Display_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 Panel_MIPI_Receiver_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u16 Panel_Backlight_Inverter_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 Panel_Initial_Brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 MIPI_Ctlr_Init_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 MIPI_Panel_Init_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct oaktrail_gct_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 bpi; /* boot panel index, number of panel used during boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct oaktrail_timing_info DTD; /* timing info for the selected panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 Panel_Port_Control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 PP_Cycle_Delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u16 Panel_Backlight_Inverter_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u16 Panel_MIPI_Display_Descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MODE_SETTING_IN_CRTC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MODE_SETTING_IN_ENCODER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MODE_SETTING_ON_GOING 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MODE_SETTING_IN_DSR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MODE_SETTING_ENCODER_DONE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Moorestown HDMI interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct oaktrail_hdmi_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int mmio, mmio_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int dpms_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct hdmi_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* register state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 saveDPLL_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 saveDPLL_DIV_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 saveDPLL_ADJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 saveDPLL_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 saveDPLL_CLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 savePCH_HTOTAL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 savePCH_HBLANK_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 savePCH_HSYNC_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 savePCH_VTOTAL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 savePCH_VBLANK_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 savePCH_VSYNC_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 savePCH_PIPEBCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 savePCH_PIPEBSRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) extern void oaktrail_hdmi_setup(struct drm_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) extern void oaktrail_hdmi_teardown(struct drm_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) extern void oaktrail_hdmi_save(struct drm_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) extern void oaktrail_hdmi_restore(struct drm_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct drm_display_mode *adjusted_mode, int x, int y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct drm_framebuffer *old_fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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