Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2007, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	    Alan Cox <alan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/shmem_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "blitter.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "psb_drv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	GTT resource allocator - manage page mappings in GTT space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *	psb_gtt_mask_pte	-	generate GTT pte entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	@pfn: page number to encode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *	@type: type of memory in the GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	Set the GTT entry for the appropriate memory type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	uint32_t mask = PSB_PTE_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	/* Ensure we explode rather than put an invalid low mapping of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	   a high mapping page into the gtt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	BUG_ON(pfn & ~(0xFFFFFFFF >> PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (type & PSB_MMU_CACHED_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		mask |= PSB_PTE_CACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (type & PSB_MMU_RO_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		mask |= PSB_PTE_RO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (type & PSB_MMU_WO_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		mask |= PSB_PTE_WO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	return (pfn << PAGE_SHIFT) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *	psb_gtt_entry		-	find the GTT entries for a gtt_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *	@dev: our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *	@r: our GTT range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *	Given a gtt_range object return the GTT offset of the page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *	entries for this gtt_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static u32 __iomem *psb_gtt_entry(struct drm_device *dev, struct gtt_range *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	offset = r->resource.start - dev_priv->gtt_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return dev_priv->gtt_map + (offset >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	psb_gtt_insert	-	put an object into the GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	@dev: our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	@r: our GTT range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *	@resume: on resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	Take our preallocated GTT range and insert the GEM object into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *	the GTT. This is protected via the gtt mutex which the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *	must hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			  int resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 __iomem *gtt_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (r->pages == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	WARN_ON(r->stolen);	/* refcount these maybe ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	gtt_slot = psb_gtt_entry(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	pages = r->pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (!resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* Make sure changes are visible to the GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		set_pages_array_wc(pages, r->npage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Write our page entries into the GTT itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	for (i = r->roll; i < r->npage; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				       PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		iowrite32(pte, gtt_slot++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	for (i = 0; i < r->roll; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				       PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		iowrite32(pte, gtt_slot++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Make sure all the entries are set before we return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ioread32(gtt_slot - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	psb_gtt_remove	-	remove an object from the GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *	@dev: our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *	@r: our GTT range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *	Remove a preallocated GTT range from the GTT. Overwrite all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *	page table entries with the dummy page. This is protected via the gtt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	mutex which the caller must hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void psb_gtt_remove(struct drm_device *dev, struct gtt_range *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 __iomem *gtt_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	WARN_ON(r->stolen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	gtt_slot = psb_gtt_entry(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			       PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for (i = 0; i < r->npage; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		iowrite32(pte, gtt_slot++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ioread32(gtt_slot - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	set_pages_array_wb(r->pages, r->npage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *	psb_gtt_roll	-	set scrolling position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *	@dev: our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *	@r: the gtt mapping we are using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *	@roll: roll offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *	Roll an existing pinned mapping by moving the pages through the GTT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *	This allows us to implement hardware scrolling on the consoles without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *	a 2D engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void psb_gtt_roll(struct drm_device *dev, struct gtt_range *r, int roll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 __iomem *gtt_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (roll >= r->npage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	r->roll = roll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Not currently in the GTT - no worry we will write the mapping at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	   the right position when it gets pinned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (!r->stolen && !r->in_gart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	gtt_slot = psb_gtt_entry(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for (i = r->roll; i < r->npage; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				       PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		iowrite32(pte, gtt_slot++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (i = 0; i < r->roll; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				       PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		iowrite32(pte, gtt_slot++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ioread32(gtt_slot - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	psb_gtt_attach_pages	-	attach and pin GEM pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *	@gt: the gtt range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *	Pin and build an in kernel list of the pages that back our GEM object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *	While we hold this the pages cannot be swapped out. This is protected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  *	via the gtt mutex which the caller must hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int psb_gtt_attach_pages(struct gtt_range *gt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	WARN_ON(gt->pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	pages = drm_gem_get_pages(&gt->gem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (IS_ERR(pages))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return PTR_ERR(pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	gt->npage = gt->gem.size / PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	gt->pages = pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *	psb_gtt_detach_pages	-	attach and pin GEM pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *	@gt: the gtt range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *	Undo the effect of psb_gtt_attach_pages. At this point the pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *	must have been removed from the GTT as they could now be paged out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *	and move bus address. This is protected via the gtt mutex which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *	caller must hold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void psb_gtt_detach_pages(struct gtt_range *gt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	drm_gem_put_pages(&gt->gem, gt->pages, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	gt->pages = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *	psb_gtt_pin		-	pin pages into the GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  *	@gt: range to pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  *	Pin a set of pages into the GTT. The pins are refcounted so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  *	multiple pins need multiple unpins to undo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  *	Non GEM backed objects treat this as a no-op as they are always GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *	backed objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int psb_gtt_pin(struct gtt_range *gt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct drm_device *dev = gt->gem.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u32 gpu_base = dev_priv->gtt.gatt_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_lock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (gt->in_gart == 0 && gt->stolen == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		ret = psb_gtt_attach_pages(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = psb_gtt_insert(dev, gt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			psb_gtt_detach_pages(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				     gt->pages, (gpu_base + gt->offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				     gt->npage, 0, 0, PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	gt->in_gart++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mutex_unlock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  *	psb_gtt_unpin		-	Drop a GTT pin requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *	@gt: range to pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  *	Undoes the effect of psb_gtt_pin. On the last drop the GEM object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *	will be removed from the GTT which will also drop the page references
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  *	and allow the VM to clean up or page stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *	Non GEM backed objects treat this as a no-op as they are always GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *	backed objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void psb_gtt_unpin(struct gtt_range *gt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct drm_device *dev = gt->gem.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	u32 gpu_base = dev_priv->gtt.gatt_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* While holding the gtt_mutex no new blits can be initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mutex_lock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Wait for any possible usage of the memory to be finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = gma_blt_wait_idle(dev_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		DRM_ERROR("Failed to idle the blitter, unpin failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	WARN_ON(!gt->in_gart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	gt->in_gart--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (gt->in_gart == 0 && gt->stolen == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				     (gpu_base + gt->offset), gt->npage, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		psb_gtt_remove(dev, gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		psb_gtt_detach_pages(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mutex_unlock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  *	GTT resource allocator - allocate and manage GTT address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  *	psb_gtt_alloc_range	-	allocate GTT address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  *	@dev: Our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  *	@len: length (bytes) of address space required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  *	@name: resource name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  *	@backed: resource should be backed by stolen pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  *	@align: requested alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  *	Ask the kernel core to find us a suitable range of addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  *	to use for a GTT mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  *	Returns a gtt_range structure describing the object, or NULL on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  *	error. On successful return the resource is both allocated and marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  *	as in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				      const char *name, int backed, u32 align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct gtt_range *gt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct resource *r = dev_priv->gtt_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	unsigned long start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (backed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		/* The start of the GTT is the stolen pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		start = r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		end = r->start + dev_priv->gtt.stolen_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		/* The rest we will use for GEM backed objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		start = r->start + dev_priv->gtt.stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		end = r->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (gt == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	gt->resource.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	gt->stolen = backed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	gt->in_gart = backed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	gt->roll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	/* Ensure this is set for non GEM objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	gt->gem.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = allocate_resource(dev_priv->gtt_mem, &gt->resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				len, start, end, align, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		gt->offset = gt->resource.start - r->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return gt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	kfree(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  *	psb_gtt_free_range	-	release GTT address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  *	@dev: our DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  *	@gt: a mapping created with psb_gtt_alloc_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  *	Release a resource that was allocated with psb_gtt_alloc_range. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  *	object has been pinned by mmap users we clean this up here currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* Undo the mmap pin if we are destroying the object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (gt->mmapping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		psb_gtt_unpin(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		gt->mmapping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	WARN_ON(gt->in_gart && !gt->stolen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	release_resource(&gt->resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	kfree(gt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void psb_gtt_alloc(struct drm_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	init_rwsem(&dev_priv->gtt.sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void psb_gtt_takedown(struct drm_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (dev_priv->gtt_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		iounmap(dev_priv->gtt_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		dev_priv->gtt_map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (dev_priv->gtt_initialized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 				      dev_priv->gmch_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		(void) PSB_RVDC32(PSB_PGETBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (dev_priv->vram_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		iounmap(dev_priv->gtt_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int psb_gtt_init(struct drm_device *dev, int resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	unsigned gtt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	unsigned long stolen_size, vram_stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	unsigned i, num_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	unsigned pfn_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct psb_gtt *pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	uint32_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (!resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		mutex_init(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		mutex_init(&dev_priv->mmap_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		psb_gtt_alloc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	pg = &dev_priv->gtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* Enable the GTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			      dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	(void) PSB_RVDC32(PSB_PGETBL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	/* The root resource we allocate address space from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	dev_priv->gtt_initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	 *	The video mmu has a hw bug when accessing 0x0D0000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	 *	Make gatt start at 0x0e000,0000. This doesn't actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	 *	matter for us but may do if the video acceleration ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	 *	gets opened up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	pg->mmu_gatt_start = 0xE0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 								>> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	/* CDV doesn't report this. In which case the system has 64 gtt pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (pg->gtt_start == 0 || gtt_pages == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		dev_dbg(dev->dev, "GTT PCI BAR not initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		gtt_pages = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		pg->gtt_start = dev_priv->pge_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 								>> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (pg->gatt_pages == 0 || pg->gatt_start == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		static struct resource fudge;	/* Preferably peppermint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		/* This can occur on CDV systems. Fudge it in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		   We really don't care what imaginary space is being allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		   at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		dev_dbg(dev->dev, "GATT PCI BAR not initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		pg->gatt_start = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		pg->gatt_pages = (128 * 1024 * 1024) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		/* This is a little confusing but in fact the GTT is providing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		   a view from the GPU into memory and not vice versa. As such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		   this is really allocating space that is not the same as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		   CPU address space on CDV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		fudge.start = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		fudge.end = 0x40000000 + 128 * 1024 * 1024 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		fudge.name = "fudge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		fudge.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		dev_priv->gtt_mem = &fudge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 								- PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	stolen_size = vram_stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	dev_dbg(dev->dev, "Stolen memory base 0x%x, size %luK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 			dev_priv->stolen_base, vram_stolen_size / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (resume && (gtt_pages != pg->gtt_pages) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	    (stolen_size != pg->stolen_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		dev_err(dev->dev, "GTT resume error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	pg->gtt_pages = gtt_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	pg->stolen_size = stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	dev_priv->vram_stolen_size = vram_stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	 *	Map the GTT and the stolen memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	if (!resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		dev_priv->gtt_map = ioremap(pg->gtt_phys_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 						gtt_pages << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (!dev_priv->gtt_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		dev_err(dev->dev, "Failure to map gtt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	if (!resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 						 stolen_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	if (!dev_priv->vram_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		dev_err(dev->dev, "Failure to map stolen base.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	 * Insert vram stolen pages into the GTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	pfn_base = dev_priv->stolen_base >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	num_pages = vram_stolen_size >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	dev_dbg(dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		num_pages, pfn_base << PAGE_SHIFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	for (i = 0; i < num_pages; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		pte = psb_gtt_mask_pte(pfn_base + i, PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		iowrite32(pte, dev_priv->gtt_map + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	 * Init rest of GTT to the scratch page to avoid accidents or scribbles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	pfn_base = page_to_pfn(dev_priv->scratch_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	pte = psb_gtt_mask_pte(pfn_base, PSB_MMU_CACHED_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	for (; i < gtt_pages; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		iowrite32(pte, dev_priv->gtt_map + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	(void) ioread32(dev_priv->gtt_map + i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	psb_gtt_takedown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int psb_gtt_restore(struct drm_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	struct drm_psb_private *dev_priv = dev->dev_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	struct resource *r = dev_priv->gtt_mem->child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	struct gtt_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	unsigned int restored = 0, total = 0, size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	/* On resume, the gtt_mutex is already initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	mutex_lock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	psb_gtt_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	while (r != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		range = container_of(r, struct gtt_range, resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		if (range->pages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 			psb_gtt_insert(dev, range, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 			size += range->resource.end - range->resource.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 			restored++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		r = r->sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		total++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	mutex_unlock(&dev_priv->gtt_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	DRM_DEBUG_DRIVER("Restored %u of %u gtt ranges (%u KB)", restored,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 			 total, (size / 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }