^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Cloned from drivers/media/video/s5p-tv/regs-vp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Video processor register header file for Samsung Mixer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef SAMSUNG_REGS_VP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SAMSUNG_REGS_VP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Register part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VP_ENABLE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VP_SRESET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VP_SHADOW_UPDATE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VP_FIELD_ID 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VP_MODE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VP_IMG_SIZE_Y 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VP_IMG_SIZE_C 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VP_PER_RATE_CTRL 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VP_TOP_Y_PTR 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VP_BOT_Y_PTR 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VP_TOP_C_PTR 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VP_BOT_C_PTR 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VP_ENDIAN_MODE 0x03CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VP_SRC_H_POSITION 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VP_SRC_V_POSITION 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VP_SRC_WIDTH 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VP_SRC_HEIGHT 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VP_DST_H_POSITION 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VP_DST_V_POSITION 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VP_DST_WIDTH 0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VP_DST_HEIGHT 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VP_H_RATIO 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VP_V_RATIO 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VP_POLY8_Y0_LL 0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VP_POLY4_Y0_LL 0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VP_POLY4_C0_LL 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Bit definition part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* generates mask for range of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VP_MASK(high_bit, low_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VP_MASK_VAL(val, high_bit, low_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* VP_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VP_ENABLE_ON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* VP_SRESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VP_SRESET_PROCESSING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* VP_SHADOW_UPDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VP_SHADOW_UPDATE_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* VP_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VP_MODE_NV12 (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VP_MODE_NV21 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VP_MODE_LINE_SKIP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VP_MODE_MEM_LINEAR (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VP_MODE_MEM_TILED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VP_MODE_FMT_MASK (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VP_MODE_2D_IPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* VP_IMG_SIZE_Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* VP_IMG_SIZE_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* VP_SRC_H_POSITION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* VP_ENDIAN_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VP_ENDIAN_MODE_LITTLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* SAMSUNG_REGS_VP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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