Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Cloned from drivers/media/video/s5p-tv/regs-mixer.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Mixer register header file for Samsung Mixer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef SAMSUNG_REGS_MIXER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define SAMSUNG_REGS_MIXER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Register part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MXR_STATUS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MXR_CFG				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MXR_INT_EN			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MXR_INT_STATUS			0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MXR_LAYER_CFG			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MXR_VIDEO_CFG			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MXR_GRAPHIC0_CFG		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MXR_GRAPHIC0_BASE		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MXR_GRAPHIC0_SPAN		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MXR_GRAPHIC0_SXY		0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MXR_GRAPHIC0_WH			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MXR_GRAPHIC0_DXY		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MXR_GRAPHIC0_BLANK		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MXR_GRAPHIC1_CFG		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MXR_GRAPHIC1_BASE		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MXR_GRAPHIC1_SPAN		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MXR_GRAPHIC1_SXY		0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MXR_GRAPHIC1_WH			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MXR_GRAPHIC1_DXY		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MXR_GRAPHIC1_BLANK		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MXR_BG_CFG			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MXR_BG_COLOR0			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MXR_BG_COLOR1			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MXR_BG_COLOR2			0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MXR_CM_COEFF_Y			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MXR_CM_COEFF_CB			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MXR_CM_COEFF_CR			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MXR_MO				0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MXR_RESOLUTION			0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MXR_CFG_S			0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MXR_GRAPHIC0_BASE_S		0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MXR_GRAPHIC1_BASE_S		0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* for parametrized access to layer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MXR_GRAPHIC_CFG(i)		(0x0020 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MXR_GRAPHIC_BASE(i)		(0x0024 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MXR_GRAPHIC_SPAN(i)		(0x0028 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MXR_GRAPHIC_SXY(i)		(0x002C + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MXR_GRAPHIC_WH(i)		(0x0030 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MXR_GRAPHIC_DXY(i)		(0x0034 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MXR_GRAPHIC_BLANK(i)		(0x0038 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MXR_GRAPHIC_BASE_S(i)		(0x2024 + (i) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Bit definition part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* generates mask for range of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MXR_MASK(high_bit, low_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MXR_MASK_VAL(val, high_bit, low_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	(((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* bits for MXR_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MXR_STATUS_SOFT_RESET		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MXR_STATUS_16_BURST		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MXR_STATUS_BURST_MASK		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MXR_STATUS_BIG_ENDIAN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MXR_STATUS_ENDIAN_MASK		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MXR_STATUS_SYNC_ENABLE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MXR_STATUS_REG_IDLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MXR_STATUS_REG_RUN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* bits for MXR_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MXR_CFG_LAYER_UPDATE		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MXR_CFG_QUANT_RANGE_FULL	(0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MXR_CFG_QUANT_RANGE_LIMITED	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MXR_CFG_RGB601			(0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MXR_CFG_RGB709			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MXR_CFG_RGB_FMT_MASK		0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MXR_CFG_OUT_YUV444		(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MXR_CFG_OUT_RGB888		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MXR_CFG_OUT_MASK		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MXR_CFG_DST_SDO			(0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MXR_CFG_DST_HDMI		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MXR_CFG_DST_MASK		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MXR_CFG_SCAN_HD_720		(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MXR_CFG_SCAN_HD_1080		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MXR_CFG_GRP1_ENABLE		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MXR_CFG_GRP0_ENABLE		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MXR_CFG_VP_ENABLE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MXR_CFG_SCAN_INTERLACE		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MXR_CFG_SCAN_PROGRESSIVE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MXR_CFG_SCAN_NTSC		(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MXR_CFG_SCAN_PAL		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MXR_CFG_SCAN_SD			(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MXR_CFG_SCAN_HD			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MXR_CFG_SCAN_MASK		0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* bits for MXR_VIDEO_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MXR_VID_CFG_BLEND_EN		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* bits for MXR_GRAPHICn_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MXR_GRP_CFG_COLOR_KEY_DISABLE	(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MXR_GRP_CFG_BLEND_PRE_MUL	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MXR_GRP_CFG_WIN_BLEND_EN	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MXR_GRP_CFG_PIXEL_BLEND_EN	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MXR_GRP_CFG_MISC_MASK		((3 << 16) | (3 << 20) | 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MXR_GRP_CFG_FORMAT_VAL(x)	MXR_MASK_VAL(x, 11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MXR_GRP_CFG_FORMAT_MASK		MXR_GRP_CFG_FORMAT_VAL(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MXR_GRP_CFG_ALPHA_VAL(x)	MXR_MASK_VAL(x, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* bits for MXR_GRAPHICn_WH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MXR_GRP_WH_H_SCALE(x)		MXR_MASK_VAL(x, 28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MXR_GRP_WH_V_SCALE(x)		MXR_MASK_VAL(x, 12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MXR_GRP_WH_WIDTH(x)		MXR_MASK_VAL(x, 26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MXR_GRP_WH_HEIGHT(x)		MXR_MASK_VAL(x, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* bits for MXR_RESOLUTION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MXR_MXR_RES_HEIGHT(x)		MXR_MASK_VAL(x, 26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MXR_MXR_RES_WIDTH(x)		MXR_MASK_VAL(x, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* bits for MXR_GRAPHICn_SXY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MXR_GRP_SXY_SX(x)		MXR_MASK_VAL(x, 26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MXR_GRP_SXY_SY(x)		MXR_MASK_VAL(x, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* bits for MXR_GRAPHICn_DXY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MXR_GRP_DXY_DX(x)		MXR_MASK_VAL(x, 26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MXR_GRP_DXY_DY(x)		MXR_MASK_VAL(x, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* bits for MXR_INT_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MXR_INT_EN_VSYNC		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MXR_INT_EN_ALL			(0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* bits for MXR_INT_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MXR_INT_CLEAR_VSYNC		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MXR_INT_STATUS_VSYNC		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* bits for MXR_LAYER_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MXR_LAYER_CFG_GRP1_VAL(x)	MXR_MASK_VAL(x, 11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MXR_LAYER_CFG_GRP1_MASK		MXR_LAYER_CFG_GRP1_VAL(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MXR_LAYER_CFG_GRP0_VAL(x)	MXR_MASK_VAL(x, 7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MXR_LAYER_CFG_GRP0_MASK		MXR_LAYER_CFG_GRP0_VAL(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MXR_LAYER_CFG_VP_VAL(x)		MXR_MASK_VAL(x, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MXR_LAYER_CFG_VP_MASK		MXR_LAYER_CFG_VP_VAL(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* bits for MXR_CM_COEFF_Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MXR_CM_COEFF_RGB_FULL		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif /* SAMSUNG_REGS_MIXER_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)