Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Cloned from drivers/media/video/s5p-tv/regs-hdmi.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * HDMI register header file for Samsung TVOUT driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef SAMSUNG_REGS_HDMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SAMSUNG_REGS_HDMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Register part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* HDMI Version 1.3 & Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HDMI_CTRL_BASE(x)		((x) + 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HDMI_CORE_BASE(x)		((x) + 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HDMI_I2S_BASE(x)		((x) + 0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HDMI_TG_BASE(x)			((x) + 0x00050000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HDMI_INTC_CON			HDMI_CTRL_BASE(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HDMI_INTC_FLAG			HDMI_CTRL_BASE(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HDMI_HPD_STATUS			HDMI_CTRL_BASE(0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HDMI_V13_PHY_RSTOUT		HDMI_CTRL_BASE(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HDMI_V13_PHY_VPLL		HDMI_CTRL_BASE(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HDMI_V13_PHY_CMU		HDMI_CTRL_BASE(0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HDMI_V13_CORE_RSTOUT		HDMI_CTRL_BASE(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* Core registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HDMI_CON_0			HDMI_CORE_BASE(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HDMI_CON_1			HDMI_CORE_BASE(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HDMI_CON_2			HDMI_CORE_BASE(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HDMI_SYS_STATUS			HDMI_CORE_BASE(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HDMI_V13_PHY_STATUS		HDMI_CORE_BASE(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HDMI_STATUS_EN			HDMI_CORE_BASE(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HDMI_HPD			HDMI_CORE_BASE(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HDMI_MODE_SEL			HDMI_CORE_BASE(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HDMI_ENC_EN			HDMI_CORE_BASE(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HDMI_V13_BLUE_SCREEN_0		HDMI_CORE_BASE(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HDMI_V13_BLUE_SCREEN_1		HDMI_CORE_BASE(0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HDMI_V13_BLUE_SCREEN_2		HDMI_CORE_BASE(0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HDMI_H_BLANK_0			HDMI_CORE_BASE(0x00A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HDMI_H_BLANK_1			HDMI_CORE_BASE(0x00A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HDMI_V13_V_BLANK_0		HDMI_CORE_BASE(0x00B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HDMI_V13_V_BLANK_1		HDMI_CORE_BASE(0x00B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HDMI_V13_V_BLANK_2		HDMI_CORE_BASE(0x00B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HDMI_V13_H_V_LINE_0		HDMI_CORE_BASE(0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HDMI_V13_H_V_LINE_1		HDMI_CORE_BASE(0x00C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HDMI_V13_H_V_LINE_2		HDMI_CORE_BASE(0x00C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HDMI_VSYNC_POL			HDMI_CORE_BASE(0x00E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HDMI_INT_PRO_MODE		HDMI_CORE_BASE(0x00E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HDMI_V13_V_BLANK_F_0		HDMI_CORE_BASE(0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define HDMI_V13_V_BLANK_F_1		HDMI_CORE_BASE(0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define HDMI_V13_V_BLANK_F_2		HDMI_CORE_BASE(0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HDMI_V13_H_SYNC_GEN_0		HDMI_CORE_BASE(0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HDMI_V13_H_SYNC_GEN_1		HDMI_CORE_BASE(0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HDMI_V13_H_SYNC_GEN_2		HDMI_CORE_BASE(0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HDMI_V13_V_SYNC_GEN_1_0		HDMI_CORE_BASE(0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HDMI_V13_V_SYNC_GEN_1_1		HDMI_CORE_BASE(0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HDMI_V13_V_SYNC_GEN_1_2		HDMI_CORE_BASE(0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HDMI_V13_V_SYNC_GEN_2_0		HDMI_CORE_BASE(0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HDMI_V13_V_SYNC_GEN_2_1		HDMI_CORE_BASE(0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HDMI_V13_V_SYNC_GEN_2_2		HDMI_CORE_BASE(0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HDMI_V13_V_SYNC_GEN_3_0		HDMI_CORE_BASE(0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HDMI_V13_V_SYNC_GEN_3_1		HDMI_CORE_BASE(0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HDMI_V13_V_SYNC_GEN_3_2		HDMI_CORE_BASE(0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HDMI_V13_AVI_CON		HDMI_CORE_BASE(0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HDMI_V13_AVI_BYTE(n)		HDMI_CORE_BASE(0x0320 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HDMI_V13_DC_CONTROL		HDMI_CORE_BASE(0x05C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HDMI_V13_VIDEO_PATTERN_GEN	HDMI_CORE_BASE(0x05C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HDMI_V13_HPD_GEN		HDMI_CORE_BASE(0x05C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HDMI_V13_AUI_CON		HDMI_CORE_BASE(0x0360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HDMI_V13_SPD_CON		HDMI_CORE_BASE(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* Timing generator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HDMI_TG_CMD			HDMI_TG_BASE(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HDMI_TG_H_FSZ_L			HDMI_TG_BASE(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HDMI_TG_H_FSZ_H			HDMI_TG_BASE(0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HDMI_TG_HACT_ST_L		HDMI_TG_BASE(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HDMI_TG_HACT_ST_H		HDMI_TG_BASE(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HDMI_TG_HACT_SZ_L		HDMI_TG_BASE(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HDMI_TG_HACT_SZ_H		HDMI_TG_BASE(0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HDMI_TG_V_FSZ_L			HDMI_TG_BASE(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HDMI_TG_V_FSZ_H			HDMI_TG_BASE(0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HDMI_TG_VSYNC_L			HDMI_TG_BASE(0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HDMI_TG_VSYNC_H			HDMI_TG_BASE(0x003C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HDMI_TG_VSYNC2_L		HDMI_TG_BASE(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HDMI_TG_VSYNC2_H		HDMI_TG_BASE(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define HDMI_TG_VACT_ST_L		HDMI_TG_BASE(0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HDMI_TG_VACT_ST_H		HDMI_TG_BASE(0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HDMI_TG_VACT_SZ_L		HDMI_TG_BASE(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HDMI_TG_VACT_SZ_H		HDMI_TG_BASE(0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HDMI_TG_FIELD_CHG_L		HDMI_TG_BASE(0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HDMI_TG_FIELD_CHG_H		HDMI_TG_BASE(0x005C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HDMI_TG_VACT_ST2_L		HDMI_TG_BASE(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HDMI_TG_VACT_ST2_H		HDMI_TG_BASE(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HDMI_TG_VSYNC_TOP_HDMI_L	HDMI_TG_BASE(0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HDMI_TG_VSYNC_TOP_HDMI_H	HDMI_TG_BASE(0x007C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HDMI_TG_VSYNC_BOT_HDMI_L	HDMI_TG_BASE(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HDMI_TG_VSYNC_BOT_HDMI_H	HDMI_TG_BASE(0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HDMI_TG_FIELD_TOP_HDMI_L	HDMI_TG_BASE(0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HDMI_TG_FIELD_TOP_HDMI_H	HDMI_TG_BASE(0x008C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HDMI_TG_FIELD_BOT_HDMI_L	HDMI_TG_BASE(0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HDMI_TG_FIELD_BOT_HDMI_H	HDMI_TG_BASE(0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * Bit definition part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* HDMI_INTC_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HDMI_INTC_EN_GLOBAL		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HDMI_INTC_EN_HPD_PLUG		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HDMI_INTC_EN_HPD_UNPLUG		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* HDMI_INTC_FLAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HDMI_INTC_FLAG_HPD_PLUG		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HDMI_INTC_FLAG_HPD_UNPLUG	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* HDMI_PHY_RSTOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HDMI_PHY_SW_RSTOUT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* HDMI_CORE_RSTOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HDMI_CORE_SW_RSTOUT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* HDMI_CON_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HDMI_BLUE_SCR_EN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HDMI_ASP_EN			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HDMI_ASP_DIS			(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HDMI_ASP_MASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HDMI_EN				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* HDMI_CON_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HDMI_VID_PREAMBLE_DIS		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HDMI_GUARD_BAND_DIS		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* HDMI_PHY_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HDMI_PHY_STATUS_READY		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* HDMI_MODE_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HDMI_MODE_HDMI_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HDMI_MODE_DVI_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HDMI_MODE_MASK			(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* HDMI_TG_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HDMI_TG_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HDMI_FIELD_EN			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* HDMI Version 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* #define HDMI_INTC_CON		HDMI_CTRL_BASE(0x0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* #define HDMI_INTC_FLAG		HDMI_CTRL_BASE(0x0004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HDMI_HDCP_KEY_LOAD		HDMI_CTRL_BASE(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* #define HDMI_HPD_STATUS		HDMI_CTRL_BASE(0x000C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HDMI_INTC_CON_1			HDMI_CTRL_BASE(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HDMI_INTC_FLAG_1		HDMI_CTRL_BASE(0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HDMI_PHY_STATUS_0		HDMI_CTRL_BASE(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HDMI_PHY_STATUS_CMU		HDMI_CTRL_BASE(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HDMI_PHY_STATUS_PLL		HDMI_CTRL_BASE(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HDMI_PHY_CON_0			HDMI_CTRL_BASE(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HDMI_HPD_CTRL			HDMI_CTRL_BASE(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HDMI_HPD_ST			HDMI_CTRL_BASE(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HDMI_HPD_TH_X			HDMI_CTRL_BASE(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HDMI_AUDIO_CLKSEL		HDMI_CTRL_BASE(0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HDMI_V14_PHY_RSTOUT		HDMI_CTRL_BASE(0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HDMI_PHY_VPLL			HDMI_CTRL_BASE(0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HDMI_PHY_CMU			HDMI_CTRL_BASE(0x007C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HDMI_CORE_RSTOUT		HDMI_CTRL_BASE(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* PHY Control bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* HDMI_PHY_CON_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HDMI_PHY_POWER_OFF_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Video related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HDMI_YMAX			HDMI_CORE_BASE(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HDMI_YMIN			HDMI_CORE_BASE(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HDMI_CMAX			HDMI_CORE_BASE(0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HDMI_CMIN			HDMI_CORE_BASE(0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HDMI_V2_BLANK_0			HDMI_CORE_BASE(0x00B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HDMI_V2_BLANK_1			HDMI_CORE_BASE(0x00B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HDMI_V1_BLANK_0			HDMI_CORE_BASE(0x00B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HDMI_V1_BLANK_1			HDMI_CORE_BASE(0x00BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HDMI_V_LINE_0			HDMI_CORE_BASE(0x00C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HDMI_V_LINE_1			HDMI_CORE_BASE(0x00C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HDMI_H_LINE_0			HDMI_CORE_BASE(0x00C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HDMI_H_LINE_1			HDMI_CORE_BASE(0x00CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HDMI_HSYNC_POL			HDMI_CORE_BASE(0x00E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HDMI_V_BLANK_F0_0		HDMI_CORE_BASE(0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HDMI_V_BLANK_F0_1		HDMI_CORE_BASE(0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HDMI_V_BLANK_F1_0		HDMI_CORE_BASE(0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HDMI_V_BLANK_F1_1		HDMI_CORE_BASE(0x011C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HDMI_H_SYNC_START_0		HDMI_CORE_BASE(0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HDMI_H_SYNC_START_1		HDMI_CORE_BASE(0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HDMI_H_SYNC_END_0		HDMI_CORE_BASE(0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HDMI_H_SYNC_END_1		HDMI_CORE_BASE(0x012C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HDMI_V_SYNC_LINE_BEF_2_0	HDMI_CORE_BASE(0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HDMI_V_SYNC_LINE_BEF_2_1	HDMI_CORE_BASE(0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HDMI_V_SYNC_LINE_BEF_1_0	HDMI_CORE_BASE(0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HDMI_V_SYNC_LINE_BEF_1_1	HDMI_CORE_BASE(0x013C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HDMI_V_SYNC_LINE_AFT_2_0	HDMI_CORE_BASE(0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HDMI_V_SYNC_LINE_AFT_2_1	HDMI_CORE_BASE(0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HDMI_V_SYNC_LINE_AFT_1_0	HDMI_CORE_BASE(0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HDMI_V_SYNC_LINE_AFT_1_1	HDMI_CORE_BASE(0x014C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HDMI_V_SYNC_LINE_AFT_PXL_2_0	HDMI_CORE_BASE(0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HDMI_V_SYNC_LINE_AFT_PXL_2_1	HDMI_CORE_BASE(0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HDMI_V_SYNC_LINE_AFT_PXL_1_0	HDMI_CORE_BASE(0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HDMI_V_SYNC_LINE_AFT_PXL_1_1	HDMI_CORE_BASE(0x015C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HDMI_V_BLANK_F2_0		HDMI_CORE_BASE(0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HDMI_V_BLANK_F2_1		HDMI_CORE_BASE(0x0164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HDMI_V_BLANK_F3_0		HDMI_CORE_BASE(0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HDMI_V_BLANK_F3_1		HDMI_CORE_BASE(0x016C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HDMI_V_BLANK_F4_0		HDMI_CORE_BASE(0x0170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HDMI_V_BLANK_F4_1		HDMI_CORE_BASE(0x0174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HDMI_V_BLANK_F5_0		HDMI_CORE_BASE(0x0178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HDMI_V_BLANK_F5_1		HDMI_CORE_BASE(0x017C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HDMI_V_SYNC_LINE_AFT_3_0	HDMI_CORE_BASE(0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDMI_V_SYNC_LINE_AFT_3_1	HDMI_CORE_BASE(0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HDMI_V_SYNC_LINE_AFT_4_0	HDMI_CORE_BASE(0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HDMI_V_SYNC_LINE_AFT_4_1	HDMI_CORE_BASE(0x018C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HDMI_V_SYNC_LINE_AFT_5_0	HDMI_CORE_BASE(0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HDMI_V_SYNC_LINE_AFT_5_1	HDMI_CORE_BASE(0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HDMI_V_SYNC_LINE_AFT_6_0	HDMI_CORE_BASE(0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HDMI_V_SYNC_LINE_AFT_6_1	HDMI_CORE_BASE(0x019C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HDMI_V_SYNC_LINE_AFT_PXL_3_0	HDMI_CORE_BASE(0x01A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HDMI_V_SYNC_LINE_AFT_PXL_3_1	HDMI_CORE_BASE(0x01A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HDMI_V_SYNC_LINE_AFT_PXL_4_0	HDMI_CORE_BASE(0x01A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HDMI_V_SYNC_LINE_AFT_PXL_4_1	HDMI_CORE_BASE(0x01AC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HDMI_V_SYNC_LINE_AFT_PXL_5_0	HDMI_CORE_BASE(0x01B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HDMI_V_SYNC_LINE_AFT_PXL_5_1	HDMI_CORE_BASE(0x01B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HDMI_V_SYNC_LINE_AFT_PXL_6_0	HDMI_CORE_BASE(0x01B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HDMI_V_SYNC_LINE_AFT_PXL_6_1	HDMI_CORE_BASE(0x01BC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HDMI_VACT_SPACE_1_0		HDMI_CORE_BASE(0x01C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HDMI_VACT_SPACE_1_1		HDMI_CORE_BASE(0x01C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HDMI_VACT_SPACE_2_0		HDMI_CORE_BASE(0x01C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HDMI_VACT_SPACE_2_1		HDMI_CORE_BASE(0x01CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HDMI_VACT_SPACE_3_0		HDMI_CORE_BASE(0x01D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define HDMI_VACT_SPACE_3_1		HDMI_CORE_BASE(0x01D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HDMI_VACT_SPACE_4_0		HDMI_CORE_BASE(0x01D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HDMI_VACT_SPACE_4_1		HDMI_CORE_BASE(0x01DC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HDMI_VACT_SPACE_5_0		HDMI_CORE_BASE(0x01E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HDMI_VACT_SPACE_5_1		HDMI_CORE_BASE(0x01E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define HDMI_VACT_SPACE_6_0		HDMI_CORE_BASE(0x01E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HDMI_VACT_SPACE_6_1		HDMI_CORE_BASE(0x01EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HDMI_GCP_CON			HDMI_CORE_BASE(0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HDMI_GCP_BYTE1			HDMI_CORE_BASE(0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HDMI_GCP_BYTE2			HDMI_CORE_BASE(0x0214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HDMI_GCP_BYTE3			HDMI_CORE_BASE(0x0218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Audio related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HDMI_ASP_CON			HDMI_CORE_BASE(0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HDMI_ASP_SP_FLAT		HDMI_CORE_BASE(0x0304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HDMI_ASP_CHCFG0			HDMI_CORE_BASE(0x0310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HDMI_ASP_CHCFG1			HDMI_CORE_BASE(0x0314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HDMI_ASP_CHCFG2			HDMI_CORE_BASE(0x0318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HDMI_ASP_CHCFG3			HDMI_CORE_BASE(0x031C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define HDMI_V13_ACR_CON		HDMI_CORE_BASE(0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HDMI_V13_ACR_MCTS0		HDMI_CORE_BASE(0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HDMI_V13_ACR_MCTS1		HDMI_CORE_BASE(0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HDMI_V13_ACR_MCTS2		HDMI_CORE_BASE(0x018C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HDMI_V13_ACR_CTS0		HDMI_CORE_BASE(0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HDMI_V13_ACR_CTS1		HDMI_CORE_BASE(0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HDMI_V13_ACR_CTS2		HDMI_CORE_BASE(0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HDMI_V13_ACR_N0			HDMI_CORE_BASE(0x01A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HDMI_V13_ACR_N1			HDMI_CORE_BASE(0x01A4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HDMI_V13_ACR_N2			HDMI_CORE_BASE(0x01A8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HDMI_V14_ACR_CON		HDMI_CORE_BASE(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define HDMI_V14_ACR_MCTS0		HDMI_CORE_BASE(0x0410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HDMI_V14_ACR_MCTS1		HDMI_CORE_BASE(0x0414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define HDMI_V14_ACR_MCTS2		HDMI_CORE_BASE(0x0418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HDMI_V14_ACR_CTS0		HDMI_CORE_BASE(0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HDMI_V14_ACR_CTS1		HDMI_CORE_BASE(0x0424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HDMI_V14_ACR_CTS2		HDMI_CORE_BASE(0x0428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HDMI_V14_ACR_N0			HDMI_CORE_BASE(0x0430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HDMI_V14_ACR_N1			HDMI_CORE_BASE(0x0434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HDMI_V14_ACR_N2			HDMI_CORE_BASE(0x0438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Packet related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HDMI_ACP_CON			HDMI_CORE_BASE(0x0500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HDMI_ACP_TYPE			HDMI_CORE_BASE(0x0514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HDMI_ACP_DATA(n)		HDMI_CORE_BASE(0x0520 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HDMI_ISRC_CON			HDMI_CORE_BASE(0x0600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HDMI_ISRC1_HEADER1		HDMI_CORE_BASE(0x0614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HDMI_ISRC1_DATA(n)		HDMI_CORE_BASE(0x0620 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HDMI_ISRC2_DATA(n)		HDMI_CORE_BASE(0x06A0 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HDMI_AVI_CON			HDMI_CORE_BASE(0x0700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HDMI_AVI_HEADER0		HDMI_CORE_BASE(0x0710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HDMI_AVI_HEADER1		HDMI_CORE_BASE(0x0714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HDMI_AVI_HEADER2		HDMI_CORE_BASE(0x0718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HDMI_AVI_CHECK_SUM		HDMI_CORE_BASE(0x071C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HDMI_AVI_BYTE(n)		HDMI_CORE_BASE(0x0720 + 4 * (n-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HDMI_AUI_CON			HDMI_CORE_BASE(0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HDMI_AUI_HEADER0		HDMI_CORE_BASE(0x0810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HDMI_AUI_HEADER1		HDMI_CORE_BASE(0x0814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HDMI_AUI_HEADER2		HDMI_CORE_BASE(0x0818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HDMI_AUI_CHECK_SUM		HDMI_CORE_BASE(0x081C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HDMI_AUI_BYTE(n)		HDMI_CORE_BASE(0x0820 + 4 * (n-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HDMI_MPG_CON			HDMI_CORE_BASE(0x0900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HDMI_MPG_CHECK_SUM		HDMI_CORE_BASE(0x091C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HDMI_MPG_DATA(n)		HDMI_CORE_BASE(0x0920 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HDMI_SPD_CON			HDMI_CORE_BASE(0x0A00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HDMI_SPD_HEADER0		HDMI_CORE_BASE(0x0A10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HDMI_SPD_HEADER1		HDMI_CORE_BASE(0x0A14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HDMI_SPD_HEADER2		HDMI_CORE_BASE(0x0A18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HDMI_SPD_DATA(n)		HDMI_CORE_BASE(0x0A20 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HDMI_GAMUT_CON			HDMI_CORE_BASE(0x0B00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HDMI_GAMUT_HEADER0		HDMI_CORE_BASE(0x0B10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HDMI_GAMUT_HEADER1		HDMI_CORE_BASE(0x0B14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HDMI_GAMUT_HEADER2		HDMI_CORE_BASE(0x0B18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define HDMI_GAMUT_METADATA(n)		HDMI_CORE_BASE(0x0B20 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define HDMI_VSI_CON			HDMI_CORE_BASE(0x0C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HDMI_VSI_HEADER0		HDMI_CORE_BASE(0x0C10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HDMI_VSI_HEADER1		HDMI_CORE_BASE(0x0C14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define HDMI_VSI_HEADER2		HDMI_CORE_BASE(0x0C18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define HDMI_VSI_DATA(n)		HDMI_CORE_BASE(0x0C20 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define HDMI_DC_CONTROL			HDMI_CORE_BASE(0x0D00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HDMI_VIDEO_PATTERN_GEN		HDMI_CORE_BASE(0x0D04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HDMI_AN_SEED_SEL		HDMI_CORE_BASE(0x0E48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define HDMI_AN_SEED_0			HDMI_CORE_BASE(0x0E58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define HDMI_AN_SEED_1			HDMI_CORE_BASE(0x0E5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define HDMI_AN_SEED_2			HDMI_CORE_BASE(0x0E60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define HDMI_AN_SEED_3			HDMI_CORE_BASE(0x0E64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* AVI bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define HDMI_AVI_CON_DO_NOT_TRANSMIT	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define HDMI_AVI_CON_EVERY_VSYNC	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AVI_ACTIVE_FORMAT_VALID	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AVI_UNDERSCANNED_DISPLAY_VALID	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* AUI bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define HDMI_AUI_CON_NO_TRAN		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define HDMI_AUI_CON_EVERY_VSYNC	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* VSI bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define HDMI_VSI_CON_DO_NOT_TRANSMIT	(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define HDMI_VSI_CON_EVERY_VSYNC	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* HDCP related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define HDMI_HDCP_SHA1(n)		HDMI_CORE_BASE(0x7000 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define HDMI_HDCP_KSV_LIST(n)		HDMI_CORE_BASE(0x7050 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define HDMI_HDCP_KSV_LIST_CON		HDMI_CORE_BASE(0x7064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define HDMI_HDCP_SHA_RESULT		HDMI_CORE_BASE(0x7070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define HDMI_HDCP_CTRL1			HDMI_CORE_BASE(0x7080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define HDMI_HDCP_CTRL2			HDMI_CORE_BASE(0x7084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define HDMI_HDCP_CHECK_RESULT		HDMI_CORE_BASE(0x7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define HDMI_HDCP_BKSV(n)		HDMI_CORE_BASE(0x70A0 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define HDMI_HDCP_AKSV(n)		HDMI_CORE_BASE(0x70C0 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define HDMI_HDCP_AN(n)			HDMI_CORE_BASE(0x70E0 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define HDMI_HDCP_BCAPS			HDMI_CORE_BASE(0x7100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HDMI_HDCP_BSTATUS_0		HDMI_CORE_BASE(0x7110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HDMI_HDCP_BSTATUS_1		HDMI_CORE_BASE(0x7114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HDMI_HDCP_RI_0			HDMI_CORE_BASE(0x7140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HDMI_HDCP_RI_1			HDMI_CORE_BASE(0x7144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define HDMI_HDCP_I2C_INT		HDMI_CORE_BASE(0x7180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define HDMI_HDCP_AN_INT		HDMI_CORE_BASE(0x7190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define HDMI_HDCP_WDT_INT		HDMI_CORE_BASE(0x71A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HDMI_HDCP_RI_INT		HDMI_CORE_BASE(0x71B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HDMI_HDCP_RI_COMPARE_0		HDMI_CORE_BASE(0x71D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define HDMI_HDCP_RI_COMPARE_1		HDMI_CORE_BASE(0x71D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define HDMI_HDCP_FRAME_COUNT		HDMI_CORE_BASE(0x71E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HDMI_RGB_ROUND_EN		HDMI_CORE_BASE(0xD500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HDMI_VACT_SPACE_R_0		HDMI_CORE_BASE(0xD504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define HDMI_VACT_SPACE_R_1		HDMI_CORE_BASE(0xD508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define HDMI_VACT_SPACE_G_0		HDMI_CORE_BASE(0xD50C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define HDMI_VACT_SPACE_G_1		HDMI_CORE_BASE(0xD510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HDMI_VACT_SPACE_B_0		HDMI_CORE_BASE(0xD514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define HDMI_VACT_SPACE_B_1		HDMI_CORE_BASE(0xD518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define HDMI_BLUE_SCREEN_B_0		HDMI_CORE_BASE(0xD520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define HDMI_BLUE_SCREEN_B_1		HDMI_CORE_BASE(0xD524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define HDMI_BLUE_SCREEN_G_0		HDMI_CORE_BASE(0xD528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define HDMI_BLUE_SCREEN_G_1		HDMI_CORE_BASE(0xD52C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define HDMI_BLUE_SCREEN_R_0		HDMI_CORE_BASE(0xD530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define HDMI_BLUE_SCREEN_R_1		HDMI_CORE_BASE(0xD534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* HDMI I2S register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define HDMI_I2S_CLK_CON		HDMI_I2S_BASE(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define HDMI_I2S_CON_1			HDMI_I2S_BASE(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define HDMI_I2S_CON_2			HDMI_I2S_BASE(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define HDMI_I2S_PIN_SEL_0		HDMI_I2S_BASE(0x00c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define HDMI_I2S_PIN_SEL_1		HDMI_I2S_BASE(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define HDMI_I2S_PIN_SEL_2		HDMI_I2S_BASE(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define HDMI_I2S_PIN_SEL_3		HDMI_I2S_BASE(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define HDMI_I2S_DSD_CON		HDMI_I2S_BASE(0x01c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define HDMI_I2S_MUX_CON		HDMI_I2S_BASE(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define HDMI_I2S_CH_ST_CON		HDMI_I2S_BASE(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* n must be within range 0...(HDMI_I2S_CH_ST_MAXNUM - 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define HDMI_I2S_CH_ST_MAXNUM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define HDMI_I2S_CH_ST(n)		HDMI_I2S_BASE(0x028 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define HDMI_I2S_CH_ST_SH_0		HDMI_I2S_BASE(0x03c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HDMI_I2S_CH_ST_SH_1		HDMI_I2S_BASE(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HDMI_I2S_CH_ST_SH_2		HDMI_I2S_BASE(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HDMI_I2S_CH_ST_SH_3		HDMI_I2S_BASE(0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HDMI_I2S_CH_ST_SH_4		HDMI_I2S_BASE(0x04c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define HDMI_I2S_MUX_CH			HDMI_I2S_BASE(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HDMI_I2S_MUX_CUV		HDMI_I2S_BASE(0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* I2S bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* I2S_CLK_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HDMI_I2S_CLK_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define HDMI_I2S_CLK_EN			(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* I2S_CON_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HDMI_I2S_SCLK_FALLING_EDGE	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define HDMI_I2S_SCLK_RISING_EDGE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define HDMI_I2S_L_CH_LOW_POL		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define HDMI_I2S_L_CH_HIGH_POL		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* I2S_CON_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define HDMI_I2S_MSB_FIRST_MODE		(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HDMI_I2S_LSB_FIRST_MODE		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define HDMI_I2S_BIT_CH_32FS		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HDMI_I2S_BIT_CH_48FS		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define HDMI_I2S_BIT_CH_RESERVED	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define HDMI_I2S_SDATA_16BIT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define HDMI_I2S_SDATA_20BIT		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define HDMI_I2S_SDATA_24BIT		(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define HDMI_I2S_BASIC_FORMAT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HDMI_I2S_L_JUST_FORMAT		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define HDMI_I2S_R_JUST_FORMAT		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define HDMI_I2S_CON_2_CLR		(~(0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HDMI_I2S_SET_BIT_CH(x)		(((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HDMI_I2S_SET_SDATA_BIT(x)	(((x) & 0x7) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* I2S_PIN_SEL_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HDMI_I2S_SEL_SCLK(x)		(((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HDMI_I2S_SEL_LRCK(x)		((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* I2S_PIN_SEL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define HDMI_I2S_SEL_SDATA1(x)		(((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define HDMI_I2S_SEL_SDATA0(x)		((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* I2S_PIN_SEL_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define HDMI_I2S_SEL_SDATA3(x)		(((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define HDMI_I2S_SEL_SDATA2(x)		((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* I2S_PIN_SEL_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define HDMI_I2S_SEL_DSD(x)		((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* I2S_DSD_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define HDMI_I2S_DSD_CLK_RI_EDGE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HDMI_I2S_DSD_CLK_FA_EDGE	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define HDMI_I2S_DSD_ENABLE		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define HDMI_I2S_DSD_DISABLE		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* I2S_MUX_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define HDMI_I2S_NOISE_FILTER_ZERO	(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HDMI_I2S_NOISE_FILTER_2_STAGE	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define HDMI_I2S_NOISE_FILTER_3_STAGE	(2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HDMI_I2S_NOISE_FILTER_4_STAGE	(3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define HDMI_I2S_NOISE_FILTER_5_STAGE	(4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define HDMI_I2S_IN_DISABLE		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HDMI_I2S_IN_ENABLE		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HDMI_I2S_AUD_SPDIF		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HDMI_I2S_AUD_I2S		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HDMI_I2S_AUD_DSD		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HDMI_I2S_CUV_SPDIF_ENABLE	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define HDMI_I2S_CUV_I2S_ENABLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HDMI_I2S_MUX_DISABLE		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define HDMI_I2S_MUX_ENABLE		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define HDMI_I2S_MUX_CON_CLR		(~(0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* I2S_CH_ST_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define HDMI_I2S_CH_STATUS_RELOAD	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define HDMI_I2S_CH_ST_CON_CLR		(~(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define HDMI_I2S_CH_STATUS_MODE_0	(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH	(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define HDMI_I2S_2AUD_CH_WITH_PREEMPH	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define HDMI_I2S_DEFAULT_EMPHASIS	(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define HDMI_I2S_COPYRIGHT		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define HDMI_I2S_NO_COPYRIGHT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define HDMI_I2S_LINEAR_PCM		(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define HDMI_I2S_NO_LINEAR_PCM		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HDMI_I2S_CONSUMER_FORMAT	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define HDMI_I2S_PROF_FORMAT		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define HDMI_I2S_CH_ST_0_CLR		(~(0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define HDMI_I2S_CD_PLAYER		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define HDMI_I2S_DAT_PLAYER		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define HDMI_I2S_DCC_PLAYER		(0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define HDMI_I2S_MINI_DISC_PLAYER	(0x49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define HDMI_I2S_CHANNEL_NUM_MASK	(0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define HDMI_I2S_SOURCE_NUM_MASK	(0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define HDMI_I2S_SET_CHANNEL_NUM(x)	(((x) & (0xF)) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define HDMI_I2S_SET_SOURCE_NUM(x)	((x) & (0xF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define HDMI_I2S_CLK_ACCUR_LEVEL_1	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HDMI_I2S_CLK_ACCUR_LEVEL_2	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define HDMI_I2S_CLK_ACCUR_LEVEL_3	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define HDMI_I2S_SMP_FREQ_44_1		(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define HDMI_I2S_SMP_FREQ_48		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define HDMI_I2S_SMP_FREQ_32		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define HDMI_I2S_SMP_FREQ_96		(0xA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define HDMI_I2S_SET_SMP_FREQ(x)	((x) & (0xF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define HDMI_I2S_ORG_SMP_FREQ_44_1	(0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define HDMI_I2S_ORG_SMP_FREQ_88_2	(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HDMI_I2S_ORG_SMP_FREQ_22_05	(0xB << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define HDMI_I2S_ORG_SMP_FREQ_176_4	(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define HDMI_I2S_WORD_LEN_NOT_DEFINE	(0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define HDMI_I2S_WORD_LEN_MAX24_20BITS	(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define HDMI_I2S_WORD_LEN_MAX24_22BITS	(0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define HDMI_I2S_WORD_LEN_MAX24_23BITS	(0x4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define HDMI_I2S_WORD_LEN_MAX24_24BITS	(0x5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define HDMI_I2S_WORD_LEN_MAX24_21BITS	(0x6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define HDMI_I2S_WORD_LEN_MAX20_16BITS	(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define HDMI_I2S_WORD_LEN_MAX20_18BITS	(0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define HDMI_I2S_WORD_LEN_MAX20_19BITS	(0x4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define HDMI_I2S_WORD_LEN_MAX20_20BITS	(0x5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define HDMI_I2S_WORD_LEN_MAX20_17BITS	(0x6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define HDMI_I2S_WORD_LEN_MAX_24BITS	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define HDMI_I2S_WORD_LEN_MAX_20BITS	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* I2S_MUX_CH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HDMI_I2S_CH3_R_EN		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HDMI_I2S_CH3_L_EN		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HDMI_I2S_CH3_EN			(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define HDMI_I2S_CH2_R_EN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define HDMI_I2S_CH2_L_EN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define HDMI_I2S_CH2_EN			(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define HDMI_I2S_CH1_R_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define HDMI_I2S_CH1_L_EN		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define HDMI_I2S_CH1_EN			(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define HDMI_I2S_CH0_R_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HDMI_I2S_CH0_L_EN		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HDMI_I2S_CH0_EN			(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define HDMI_I2S_CH_ALL_EN		(0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define HDMI_I2S_MUX_CH_CLR		(~HDMI_I2S_CH_ALL_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* I2S_MUX_CUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define HDMI_I2S_CUV_R_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define HDMI_I2S_CUV_L_EN		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define HDMI_I2S_CUV_RL_EN		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* I2S_CUV_L_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define HDMI_I2S_CUV_R_DATA_MASK	(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define HDMI_I2S_CUV_L_DATA_MASK	(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Timing generator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* TG configure/status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define HDMI_TG_VACT_ST3_L		HDMI_TG_BASE(0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define HDMI_TG_VACT_ST3_H		HDMI_TG_BASE(0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define HDMI_TG_VACT_ST4_L		HDMI_TG_BASE(0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define HDMI_TG_VACT_ST4_H		HDMI_TG_BASE(0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define HDMI_TG_3D			HDMI_TG_BASE(0x00F0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define HDMI_TG_DECON_EN		HDMI_TG_BASE(0x01e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* HDMI PHY Registers Offsets*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define HDMIPHY_POWER			0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define HDMIPHY_MODE_SET_DONE		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define HDMIPHY5433_MODE_SET_DONE	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* HDMI PHY Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define HDMI_PHY_POWER_ON              0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define HDMI_PHY_POWER_OFF             0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* HDMI PHY Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define HDMI_PHY_DISABLE_MODE_SET	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define HDMI_PHY_ENABLE_MODE_SET	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* PMU Registers for PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define PMU_HDMI_PHY_CONTROL		0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define PMU_HDMI_PHY_ENABLE_BIT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EXYNOS5433_SYSREG_DISP_HDMI_PHY	0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SYSREG_HDMI_REFCLK_INT_CLK	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif /* SAMSUNG_REGS_HDMI_H */