Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* linux/drivers/gpu/drm/exynos/regs-gsc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Register definition file for Samsung G-Scaler driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef EXYNOS_REGS_GSC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define EXYNOS_REGS_GSC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* G-Scaler enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define GSC_ENABLE			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define GSC_ENABLE_PP_UPDATE_TIME_MASK	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define GSC_ENABLE_PP_UPDATE_TIME_CURR	(0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GSC_ENABLE_PP_UPDATE_TIME_EOPAS	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GSC_ENABLE_CLK_GATE_MODE_MASK	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GSC_ENABLE_CLK_GATE_MODE_FREE	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define GSC_ENABLE_IPC_MODE_MASK	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GSC_ENABLE_NORM_MODE		(0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GSC_ENABLE_IPC_MODE		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GSC_ENABLE_PP_UPDATE_MODE_MASK	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GSC_ENABLE_PP_UPDATE_FIRE_MODE	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GSC_ENABLE_IN_PP_UPDATE		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GSC_ENABLE_ON_CLEAR_MASK	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GSC_ENABLE_ON_CLEAR_ONESHOT	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GSC_ENABLE_QOS_ENABLE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GSC_ENABLE_OP_STATUS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GSC_ENABLE_SFR_UPDATE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GSC_ENABLE_ON			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* G-Scaler S/W reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GSC_SW_RESET			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GSC_SW_RESET_SRESET		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* G-Scaler IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GSC_IRQ				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GSC_IRQ_STATUS_OR_IRQ		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GSC_IRQ_STATUS_OR_FRM_DONE	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GSC_IRQ_OR_MASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define GSC_IRQ_FRMDONE_MASK		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define GSC_IRQ_ENABLE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* G-Scaler input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GSC_IN_CON			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GSC_IN_CHROM_STRIDE_SEL_MASK	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GSC_IN_CHROM_STRIDE_SEPAR	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GSC_IN_RB_SWAP_MASK		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GSC_IN_RB_SWAP			(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GSC_IN_ROT_MASK			(7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GSC_IN_ROT_270			(7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GSC_IN_ROT_90_YFLIP		(6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define GSC_IN_ROT_90_XFLIP		(5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GSC_IN_ROT_90			(4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GSC_IN_ROT_180			(3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GSC_IN_ROT_YFLIP		(2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define GSC_IN_ROT_XFLIP		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define GSC_IN_RGB_TYPE_MASK		(3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define GSC_IN_RGB_HD_WIDE		(3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define GSC_IN_RGB_HD_NARROW		(2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define GSC_IN_RGB_SD_WIDE		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define GSC_IN_RGB_SD_NARROW		(0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GSC_IN_YUV422_1P_ORDER_MASK	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GSC_IN_YUV422_1P_ORDER_LSB_Y	(0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define GSC_IN_YUV422_1P_OEDER_LSB_C	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define GSC_IN_CHROMA_ORDER_MASK	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define GSC_IN_CHROMA_ORDER_CBCR	(0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define GSC_IN_CHROMA_ORDER_CRCB	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define GSC_IN_FORMAT_MASK		(7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define GSC_IN_XRGB8888			(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define GSC_IN_RGB565			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define GSC_IN_YUV420_2P		(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define GSC_IN_YUV420_3P		(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GSC_IN_YUV422_1P		(4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GSC_IN_YUV422_2P		(5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GSC_IN_YUV422_3P		(6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GSC_IN_TILE_TYPE_MASK		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define GSC_IN_TILE_C_16x8		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define GSC_IN_TILE_C_16x16		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GSC_IN_TILE_MODE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define GSC_IN_LOCAL_SEL_MASK		(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GSC_IN_LOCAL_CAM3		(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define GSC_IN_LOCAL_FIMD_WB		(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define GSC_IN_LOCAL_CAM1		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GSC_IN_LOCAL_CAM0		(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define GSC_IN_PATH_MASK		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GSC_IN_PATH_LOCAL		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GSC_IN_PATH_MEMORY		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* G-Scaler source image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GSC_SRCIMG_SIZE			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GSC_SRCIMG_HEIGHT_MASK		(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GSC_SRCIMG_HEIGHT(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GSC_SRCIMG_WIDTH_MASK		(0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GSC_SRCIMG_WIDTH(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* G-Scaler source image offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GSC_SRCIMG_OFFSET		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GSC_SRCIMG_OFFSET_Y_MASK	(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GSC_SRCIMG_OFFSET_Y(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GSC_SRCIMG_OFFSET_X_MASK	(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GSC_SRCIMG_OFFSET_X(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* G-Scaler cropped source image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GSC_CROPPED_SIZE		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GSC_CROPPED_HEIGHT_MASK		(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GSC_CROPPED_HEIGHT(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GSC_CROPPED_WIDTH_MASK		(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GSC_CROPPED_WIDTH(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* G-Scaler output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GSC_OUT_CON			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GSC_OUT_GLOBAL_ALPHA_MASK	(0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GSC_OUT_GLOBAL_ALPHA(x)		((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GSC_OUT_CHROM_STRIDE_SEL_MASK	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GSC_OUT_CHROM_STRIDE_SEPAR	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GSC_OUT_RB_SWAP_MASK		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GSC_OUT_RB_SWAP			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GSC_OUT_RGB_TYPE_MASK		(3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GSC_OUT_RGB_HD_NARROW		(3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GSC_OUT_RGB_HD_WIDE		(2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GSC_OUT_RGB_SD_NARROW		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GSC_OUT_RGB_SD_WIDE		(0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GSC_OUT_YUV422_1P_ORDER_MASK	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GSC_OUT_YUV422_1P_ORDER_LSB_Y	(0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GSC_OUT_YUV422_1P_OEDER_LSB_C	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GSC_OUT_CHROMA_ORDER_MASK	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GSC_OUT_CHROMA_ORDER_CBCR	(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GSC_OUT_CHROMA_ORDER_CRCB	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GSC_OUT_FORMAT_MASK		(7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GSC_OUT_XRGB8888		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GSC_OUT_RGB565			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GSC_OUT_YUV420_2P		(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GSC_OUT_YUV420_3P		(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GSC_OUT_YUV422_1P		(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GSC_OUT_YUV422_2P		(5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GSC_OUT_YUV422_3P		(6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GSC_OUT_YUV444			(7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GSC_OUT_TILE_TYPE_MASK		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GSC_OUT_TILE_C_16x8		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GSC_OUT_TILE_C_16x16		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GSC_OUT_TILE_MODE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GSC_OUT_PATH_MASK		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GSC_OUT_PATH_LOCAL		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GSC_OUT_PATH_MEMORY		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* G-Scaler scaled destination image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GSC_SCALED_SIZE			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GSC_SCALED_HEIGHT_MASK		(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GSC_SCALED_HEIGHT(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GSC_SCALED_WIDTH_MASK		(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GSC_SCALED_WIDTH(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* G-Scaler pre scale ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GSC_PRE_SCALE_RATIO		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GSC_PRESC_SHFACTOR_MASK		(7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GSC_PRESC_SHFACTOR(x)		((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GSC_PRESC_V_RATIO_MASK		(7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GSC_PRESC_V_RATIO(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GSC_PRESC_H_RATIO_MASK		(7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GSC_PRESC_H_RATIO(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* G-Scaler main scale horizontal ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GSC_MAIN_H_RATIO		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GSC_MAIN_H_RATIO_MASK		(0xfffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GSC_MAIN_H_RATIO_VALUE(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* G-Scaler main scale vertical ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GSC_MAIN_V_RATIO		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GSC_MAIN_V_RATIO_MASK		(0xfffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GSC_MAIN_V_RATIO_VALUE(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* G-Scaler input chrominance stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GSC_IN_CHROM_STRIDE		0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GSC_IN_CHROM_STRIDE_MASK	(0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GSC_IN_CHROM_STRIDE_VALUE(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* G-Scaler destination image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GSC_DSTIMG_SIZE			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GSC_DSTIMG_HEIGHT_MASK		(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GSC_DSTIMG_HEIGHT(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GSC_DSTIMG_WIDTH_MASK		(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GSC_DSTIMG_WIDTH(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* G-Scaler destination image offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GSC_DSTIMG_OFFSET		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GSC_DSTIMG_OFFSET_Y_MASK	(0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GSC_DSTIMG_OFFSET_Y(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GSC_DSTIMG_OFFSET_X_MASK	(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GSC_DSTIMG_OFFSET_X(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* G-Scaler output chrominance stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GSC_OUT_CHROM_STRIDE		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GSC_OUT_CHROM_STRIDE_MASK	(0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GSC_OUT_CHROM_STRIDE_VALUE(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* G-Scaler input y address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GSC_IN_BASE_ADDR_Y_MASK		0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* G-Scaler input y base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GSC_IN_BASE_ADDR_Y(n)		(0x50 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* G-Scaler input y base current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GSC_IN_BASE_ADDR_Y_CUR(n)	(0x60 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* G-Scaler input cb address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GSC_IN_BASE_ADDR_CB_MASK	0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* G-Scaler input cb base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GSC_IN_BASE_ADDR_CB(n)		(0x80 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* G-Scaler input cb base current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GSC_IN_BASE_ADDR_CB_CUR(n)	(0x90 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* G-Scaler input cr address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GSC_IN_BASE_ADDR_CR_MASK	0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* G-Scaler input cr base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GSC_IN_BASE_ADDR_CR(n)		(0xB0 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* G-Scaler input cr base current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GSC_IN_BASE_ADDR_CR_CUR(n)	(0xC0 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* G-Scaler input address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GSC_IN_CURR_ADDR_INDEX	(0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GSC_IN_CURR_GET_INDEX(x)	((x) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GSC_IN_BASE_ADDR_PINGPONG(x)	((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GSC_IN_BASE_ADDR_MASK		(0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* G-Scaler output y address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GSC_OUT_BASE_ADDR_Y_MASK	0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* G-Scaler output y base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GSC_OUT_BASE_ADDR_Y(n)		(0x110 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* G-Scaler output cb address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GSC_OUT_BASE_ADDR_CB_MASK	0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* G-Scaler output cb base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GSC_OUT_BASE_ADDR_CB(n)		(0x160 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* G-Scaler output cr address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GSC_OUT_BASE_ADDR_CR_MASK	0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* G-Scaler output cr base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GSC_OUT_BASE_ADDR_CR(n)		(0x1B0 + (n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* G-Scaler output address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GSC_OUT_CURR_ADDR_INDEX		(0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GSC_OUT_CURR_GET_INDEX(x)	((x) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GSC_OUT_BASE_ADDR_PINGPONG(x)	((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GSC_OUT_BASE_ADDR_MASK		(0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* G-Scaler horizontal scaling filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GSC_HCOEF(n, s, x)	(0x300 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* G-Scaler vertical scaling filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GSC_VCOEF(n, s, x)	(0x200 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* G-Scaler BUS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GSC_BUSCON			0xA78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GSC_BUSCON_INT_TIME_MASK	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GSC_BUSCON_INT_DATA_TRANS	(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GSC_BUSCON_INT_AXI_RESPONSE	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GSC_BUSCON_AWCACHE(x)		((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GSC_BUSCON_ARCACHE(x)		((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* G-Scaler V position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GSC_VPOSITION			0xA7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GSC_VPOS_F(x)			((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* G-Scaler clock initial count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GSC_CLK_INIT_COUNT		0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GSC_CLK_GATE_MODE_INIT_CNT(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* G-Scaler clock snoop count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GSC_CLK_SNOOP_COUNT		0xC04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GSC_CLK_GATE_MODE_SNOOP_CNT(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* SYSCON. GSCBLK_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SYSREG_GSCBLK_CFG1		0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GSC_BLK_DISP1WB_DEST(x)		(x << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GSC_BLK_SW_RESET_WB_DEST(x)	(1 << (18 + x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GSC_BLK_PXLASYNC_LO_MASK_WB(x)	(0 << (14 + x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GSC_BLK_GSCL_WB_IN_SRC_SEL(x)	(1 << (2 * x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SYSREG_GSCBLK_CFG2		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PXLASYNC_LO_MASK_CAMIF_GSCL(x)	(1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif /* EXYNOS_REGS_GSC_H_ */