^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/gpu/drm/exynos/regs-fimc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Register definition file for Samsung Camera Interface (FIMC) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef EXYNOS_REGS_FIMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define EXYNOS_REGS_FIMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Register part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Input source format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EXYNOS_CISRCFMT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Window offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EXYNOS_CIWDOFST (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Global control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_CIGCTRL (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Window offset 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_CIWDOFST2 (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Y 1st frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS_CIOYSA1 (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Y 2nd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EXYNOS_CIOYSA2 (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Y 3rd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EXYNOS_CIOYSA3 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Y 4th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EXYNOS_CIOYSA4 (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Cb 1st frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXYNOS_CIOCBSA1 (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Cb 2nd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS_CIOCBSA2 (0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Cb 3rd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EXYNOS_CIOCBSA3 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Cb 4th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXYNOS_CIOCBSA4 (0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Cr 1st frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXYNOS_CIOCRSA1 (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Cr 2nd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS_CIOCRSA2 (0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Cr 3rd frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXYNOS_CIOCRSA3 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Cr 4th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXYNOS_CIOCRSA4 (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Target image format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXYNOS_CITRGFMT (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Output DMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXYNOS_CIOCTRL (0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Pre-scaler control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXYNOS_CISCPRERATIO (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Pre-scaler control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXYNOS_CISCPREDST (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Main scaler control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXYNOS_CISCCTRL (0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Target area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXYNOS_CITAREA (0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXYNOS_CISTATUS (0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Status2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXYNOS_CISTATUS2 (0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Image capture enable command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EXYNOS_CIIMGCPT (0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Capture sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXYNOS_CICPTSEQ (0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Image effects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EXYNOS_CIIMGEFF (0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Y frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EXYNOS_CIIYSA0 (0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Cb frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXYNOS_CIICBSA0 (0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Cr frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EXYNOS_CIICRSA0 (0xdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Input DMA Y Line Skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EXYNOS_CIILINESKIP_Y (0xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Input DMA Cb Line Skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EXYNOS_CIILINESKIP_CB (0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Input DMA Cr Line Skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EXYNOS_CIILINESKIP_CR (0xf4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Real input DMA image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EXYNOS_CIREAL_ISIZE (0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Input DMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EXYNOS_MSCTRL (0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Y frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EXYNOS_CIIYSA1 (0x144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Cb frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EXYNOS_CIICBSA1 (0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Cr frame start address for input DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXYNOS_CIICRSA1 (0x14c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Output DMA Y offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EXYNOS_CIOYOFF (0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Output DMA CB offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EXYNOS_CIOCBOFF (0x16c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Output DMA CR offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EXYNOS_CIOCROFF (0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Input DMA Y offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EXYNOS_CIIYOFF (0x174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Input DMA CB offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EXYNOS_CIICBOFF (0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Input DMA CR offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EXYNOS_CIICROFF (0x17c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Input DMA original image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EXYNOS_ORGISIZE (0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Output DMA original image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EXYNOS_ORGOSIZE (0x184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Real output DMA image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EXYNOS_CIEXTEN (0x188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* DMA parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EXYNOS_CIDMAPARAM (0x18c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* MIPI CSI image format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EXYNOS_CSIIMGFMT (0x194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* FIMC Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EXYNOS_MISC_FIMC (0x198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Add for FIMC v5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Output Frame Buffer Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EXYNOS_CIFCNTSEQ (0x1fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Y 5th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EXYNOS_CIOYSA5 (0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Y 6th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EXYNOS_CIOYSA6 (0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Y 7th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EXYNOS_CIOYSA7 (0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Y 8th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EXYNOS_CIOYSA8 (0x20c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Y 9th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EXYNOS_CIOYSA9 (0x210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Y 10th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EXYNOS_CIOYSA10 (0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Y 11th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EXYNOS_CIOYSA11 (0x218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Y 12th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EXYNOS_CIOYSA12 (0x21c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Y 13th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EXYNOS_CIOYSA13 (0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Y 14th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EXYNOS_CIOYSA14 (0x224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Y 15th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EXYNOS_CIOYSA15 (0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Y 16th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EXYNOS_CIOYSA16 (0x22c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Y 17th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EXYNOS_CIOYSA17 (0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Y 18th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EXYNOS_CIOYSA18 (0x234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Y 19th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EXYNOS_CIOYSA19 (0x238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Y 20th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EXYNOS_CIOYSA20 (0x23c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Y 21th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EXYNOS_CIOYSA21 (0x240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Y 22th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EXYNOS_CIOYSA22 (0x244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Y 23th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EXYNOS_CIOYSA23 (0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Y 24th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EXYNOS_CIOYSA24 (0x24c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Y 25th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EXYNOS_CIOYSA25 (0x250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Y 26th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EXYNOS_CIOYSA26 (0x254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Y 27th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EXYNOS_CIOYSA27 (0x258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Y 28th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EXYNOS_CIOYSA28 (0x25c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Y 29th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EXYNOS_CIOYSA29 (0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Y 30th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EXYNOS_CIOYSA30 (0x264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Y 31th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EXYNOS_CIOYSA31 (0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Y 32th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EXYNOS_CIOYSA32 (0x26c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* CB 5th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EXYNOS_CIOCBSA5 (0x270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* CB 6th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EXYNOS_CIOCBSA6 (0x274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* CB 7th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EXYNOS_CIOCBSA7 (0x278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* CB 8th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EXYNOS_CIOCBSA8 (0x27c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* CB 9th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EXYNOS_CIOCBSA9 (0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* CB 10th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EXYNOS_CIOCBSA10 (0x284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* CB 11th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EXYNOS_CIOCBSA11 (0x288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* CB 12th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EXYNOS_CIOCBSA12 (0x28c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* CB 13th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EXYNOS_CIOCBSA13 (0x290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* CB 14th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EXYNOS_CIOCBSA14 (0x294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* CB 15th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EXYNOS_CIOCBSA15 (0x298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* CB 16th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EXYNOS_CIOCBSA16 (0x29c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* CB 17th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EXYNOS_CIOCBSA17 (0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* CB 18th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EXYNOS_CIOCBSA18 (0x2a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* CB 19th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EXYNOS_CIOCBSA19 (0x2a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* CB 20th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EXYNOS_CIOCBSA20 (0x2ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* CB 21th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EXYNOS_CIOCBSA21 (0x2b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* CB 22th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EXYNOS_CIOCBSA22 (0x2b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* CB 23th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EXYNOS_CIOCBSA23 (0x2b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* CB 24th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EXYNOS_CIOCBSA24 (0x2bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* CB 25th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EXYNOS_CIOCBSA25 (0x2c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* CB 26th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EXYNOS_CIOCBSA26 (0x2c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* CB 27th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EXYNOS_CIOCBSA27 (0x2c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* CB 28th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define EXYNOS_CIOCBSA28 (0x2cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* CB 29th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EXYNOS_CIOCBSA29 (0x2d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* CB 30th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define EXYNOS_CIOCBSA30 (0x2d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* CB 31th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define EXYNOS_CIOCBSA31 (0x2d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* CB 32th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EXYNOS_CIOCBSA32 (0x2dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* CR 5th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EXYNOS_CIOCRSA5 (0x2e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* CR 6th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define EXYNOS_CIOCRSA6 (0x2e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* CR 7th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EXYNOS_CIOCRSA7 (0x2e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* CR 8th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EXYNOS_CIOCRSA8 (0x2ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* CR 9th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EXYNOS_CIOCRSA9 (0x2f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* CR 10th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EXYNOS_CIOCRSA10 (0x2f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* CR 11th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EXYNOS_CIOCRSA11 (0x2f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* CR 12th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EXYNOS_CIOCRSA12 (0x2fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* CR 13th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EXYNOS_CIOCRSA13 (0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* CR 14th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EXYNOS_CIOCRSA14 (0x304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* CR 15th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EXYNOS_CIOCRSA15 (0x308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* CR 16th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EXYNOS_CIOCRSA16 (0x30c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* CR 17th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EXYNOS_CIOCRSA17 (0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* CR 18th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EXYNOS_CIOCRSA18 (0x314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* CR 19th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EXYNOS_CIOCRSA19 (0x318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* CR 20th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define EXYNOS_CIOCRSA20 (0x31c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* CR 21th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EXYNOS_CIOCRSA21 (0x320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* CR 22th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EXYNOS_CIOCRSA22 (0x324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* CR 23th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define EXYNOS_CIOCRSA23 (0x328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* CR 24th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define EXYNOS_CIOCRSA24 (0x32c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* CR 25th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EXYNOS_CIOCRSA25 (0x330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* CR 26th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define EXYNOS_CIOCRSA26 (0x334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* CR 27th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EXYNOS_CIOCRSA27 (0x338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* CR 28th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EXYNOS_CIOCRSA28 (0x33c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* CR 29th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EXYNOS_CIOCRSA29 (0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* CR 30th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EXYNOS_CIOCRSA30 (0x344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* CR 31th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define EXYNOS_CIOCRSA31 (0x348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* CR 32th frame start address for output DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define EXYNOS_CIOCRSA32 (0x34c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Macro part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* frame start address 1 ~ 4, 5 ~ 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Number of Default PingPong Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DEF_PP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define EXYNOS_CIOYSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (((__x) < DEF_PP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (EXYNOS_CIOYSA1 + (__x) * 4) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define EXYNOS_CIOCBSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (((__x) < DEF_PP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (EXYNOS_CIOCBSA1 + (__x) * 4) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define EXYNOS_CIOCRSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (((__x) < DEF_PP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (EXYNOS_CIOCRSA1 + (__x) * 4) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Number of Default PingPong Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DEF_IPP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define EXYNOS_CIIYSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (((__x) < DEF_IPP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (EXYNOS_CIIYSA0) : (EXYNOS_CIIYSA1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EXYNOS_CIICBSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (((__x) < DEF_IPP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (EXYNOS_CIICBSA0) : (EXYNOS_CIICBSA1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define EXYNOS_CIICRSA(__x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (((__x) < DEF_IPP) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (EXYNOS_CIICRSA0) : (EXYNOS_CIICRSA1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define EXYNOS_CIWDOFST_WINHOROFST(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define EXYNOS_CIWDOFST_WINVEROFST(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define EXYNOS_CIWDOFST2_WINHOROFST2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define EXYNOS_CIWDOFST2_WINVEROFST2(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define EXYNOS_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define EXYNOS_CITRGFMT_TARGETVSIZE(x) (((x) & 0x1fff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define EXYNOS_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define EXYNOS_CISCPRERATIO_PREHORRATIO(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define EXYNOS_CISCPRERATIO_PREVERRATIO(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define EXYNOS_CISCPREDST_PREDSTWIDTH(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define EXYNOS_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EXYNOS_CISCCTRL_MAINHORRATIO(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EXYNOS_CISCCTRL_MAINVERRATIO(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define EXYNOS_CITAREA_TARGET_AREA(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EXYNOS_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define EXYNOS_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EXYNOS_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EXYNOS_CISTATUS_GET_LCD_STATUS(x) (((x) >> 9) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EXYNOS_CISTATUS_GET_ENVID_STATUS(x) (((x) >> 8) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(x) (((x) >> 7) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(x) ((x) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define EXYNOS_CIIMGEFF_FIN(x) ((x & 0x7) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EXYNOS_CIIMGEFF_PAT_CB(x) ((x) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EXYNOS_CIIMGEFF_PAT_CR(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define EXYNOS_CIILINESKIP(x) (((x) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EXYNOS_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EXYNOS_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define EXYNOS_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define EXYNOS_MSCTRL_GET_INDMA_STATUS(x) ((x) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define EXYNOS_CIOYOFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EXYNOS_CIOYOFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define EXYNOS_CIOCBOFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define EXYNOS_CIOCBOFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EXYNOS_CIOCROFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define EXYNOS_CIOCROFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define EXYNOS_CIIYOFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EXYNOS_CIIYOFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EXYNOS_CIICBOFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define EXYNOS_CIICBOFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define EXYNOS_CIICROFF_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define EXYNOS_CIICROFF_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define EXYNOS_ORGISIZE_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define EXYNOS_ORGISIZE_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define EXYNOS_ORGOSIZE_VERTICAL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define EXYNOS_ORGOSIZE_HORIZONTAL(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define EXYNOS_CIEXTEN_TARGETH_EXT(x) ((((x) & 0x2000) >> 13) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define EXYNOS_CIEXTEN_TARGETV_EXT(x) ((((x) & 0x2000) >> 13) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT(x) (((x) & 0x3F) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT(x) ((x) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Bit definition part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Source format register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define EXYNOS_CISRCFMT_ITU601_8BIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define EXYNOS_CISRCFMT_ITU656_8BIT (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define EXYNOS_CISRCFMT_ITU601_16BIT (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define EXYNOS_CISRCFMT_ORDER422_YCBYCR (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define EXYNOS_CISRCFMT_ORDER422_YCRYCB (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define EXYNOS_CISRCFMT_ORDER422_CBYCRY (2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define EXYNOS_CISRCFMT_ORDER422_CRYCBY (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* ITU601 16bit only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define EXYNOS_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* ITU601 16bit only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define EXYNOS_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Window offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define EXYNOS_CIWDOFST_WINOFSEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define EXYNOS_CIWDOFST_CLROVFIY (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define EXYNOS_CIWDOFST_CLROVRLB (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define EXYNOS_CIWDOFST_WINHOROFST_MASK (0x7ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define EXYNOS_CIWDOFST_CLROVFICB (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define EXYNOS_CIWDOFST_CLROVFICR (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define EXYNOS_CIWDOFST_WINVEROFST_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Global control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define EXYNOS_CIGCTRL_SWRST (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define EXYNOS_CIGCTRL_CAMRST_A (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define EXYNOS_CIGCTRL_SELCAM_ITU_B (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define EXYNOS_CIGCTRL_SELCAM_ITU_A (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define EXYNOS_CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define EXYNOS_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define EXYNOS_CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define EXYNOS_CIGCTRL_TESTPATTERN_MASK (3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define EXYNOS_CIGCTRL_TESTPATTERN_SHIFT (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define EXYNOS_CIGCTRL_INVPOLPCLK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define EXYNOS_CIGCTRL_INVPOLVSYNC (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define EXYNOS_CIGCTRL_INVPOLHREF (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define EXYNOS_CIGCTRL_IRQ_OVFEN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define EXYNOS_CIGCTRL_HREF_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define EXYNOS_CIGCTRL_IRQ_EDGE (0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define EXYNOS_CIGCTRL_IRQ_LEVEL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define EXYNOS_CIGCTRL_IRQ_CLR (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define EXYNOS_CIGCTRL_IRQ_END_DISABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define EXYNOS_CIGCTRL_IRQ_DISABLE (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define EXYNOS_CIGCTRL_IRQ_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define EXYNOS_CIGCTRL_SHADOW_DISABLE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define EXYNOS_CIGCTRL_CAM_JPEG (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define EXYNOS_CIGCTRL_SELCAM_MIPI_B (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define EXYNOS_CIGCTRL_SELCAM_MIPI_A (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define EXYNOS_CIGCTRL_SELCAM_MIPI_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define EXYNOS_CIGCTRL_SELWB_CAMIF_CAMERA (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define EXYNOS_CIGCTRL_SELWRITEBACK_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define EXYNOS_CIGCTRL_SELWRITEBACK_A (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define EXYNOS_CIGCTRL_SELWRITEBACK_B (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define EXYNOS_CIGCTRL_SELWB_CAMIF_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define EXYNOS_CIGCTRL_CSC_ITU601 (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define EXYNOS_CIGCTRL_CSC_ITU709 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define EXYNOS_CIGCTRL_CSC_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define EXYNOS_CIGCTRL_INVPOLHSYNC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define EXYNOS_CIGCTRL_SELCAM_FIMC_ITU (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define EXYNOS_CIGCTRL_SELCAM_FIMC_MIPI (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define EXYNOS_CIGCTRL_SELCAM_FIMC_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define EXYNOS_CIGCTRL_PROGRESSIVE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define EXYNOS_CIGCTRL_INTERLACE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Window offset2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define EXYNOS_CIWDOFST_WINHOROFST2_MASK (0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define EXYNOS_CIWDOFST_WINVEROFST2_MASK (0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Target format register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define EXYNOS_CITRGFMT_INROT90_CLOCKWISE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define EXYNOS_CITRGFMT_OUTFORMAT_RGB (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EXYNOS_CITRGFMT_OUTFORMAT_MASK (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define EXYNOS_CITRGFMT_FLIP_SHIFT (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define EXYNOS_CITRGFMT_FLIP_NORMAL (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define EXYNOS_CITRGFMT_FLIP_X_MIRROR (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define EXYNOS_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define EXYNOS_CITRGFMT_FLIP_180 (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define EXYNOS_CITRGFMT_FLIP_MASK (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define EXYNOS_CITRGFMT_TARGETV_MASK (0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define EXYNOS_CITRGFMT_TARGETH_MASK (0x1fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Output DMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define EXYNOS_CIOCTRL_WEAVE_OUT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EXYNOS_CIOCTRL_WEAVE_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define EXYNOS_CIOCTRL_LASTENDEN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define EXYNOS_CIOCTRL_ORDER2P_MSB_CRCB (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define EXYNOS_CIOCTRL_ORDER2P_MSB_CBCR (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define EXYNOS_CIOCTRL_ORDER2P_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EXYNOS_CIOCTRL_ORDER2P_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define EXYNOS_CIOCTRL_YCBCR_3PLANE (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define EXYNOS_CIOCTRL_YCBCR_2PLANE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define EXYNOS_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define EXYNOS_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define EXYNOS_CIOCTRL_ALPHA_OUT (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define EXYNOS_CIOCTRL_ORDER422_YCBYCR (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define EXYNOS_CIOCTRL_ORDER422_YCRYCB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define EXYNOS_CIOCTRL_ORDER422_CBYCRY (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define EXYNOS_CIOCTRL_ORDER422_CRYCBY (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define EXYNOS_CIOCTRL_ORDER422_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Main scaler control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define EXYNOS_CISCCTRL_SCALERBYPASS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define EXYNOS_CISCCTRL_SCALEUP_H (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define EXYNOS_CISCCTRL_SCALEUP_V (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define EXYNOS_CISCCTRL_CSCR2Y_NARROW (0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define EXYNOS_CISCCTRL_CSCR2Y_WIDE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define EXYNOS_CISCCTRL_CSCY2R_NARROW (0 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define EXYNOS_CISCCTRL_CSCY2R_WIDE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define EXYNOS_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define EXYNOS_CISCCTRL_PROGRESSIVE (0 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define EXYNOS_CISCCTRL_INTERLACE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define EXYNOS_CISCCTRL_SCAN_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define EXYNOS_CISCCTRL_SCALERSTART (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define EXYNOS_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define EXYNOS_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define EXYNOS_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define EXYNOS_CISCCTRL_EXTRGB_NORMAL (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define EXYNOS_CISCCTRL_EXTRGB_EXTENSION (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define EXYNOS_CISCCTRL_ONE2ONE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK (0x1ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define EXYNOS_CISTATUS_OVFIY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define EXYNOS_CISTATUS_OVFICB (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define EXYNOS_CISTATUS_OVFICR (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define EXYNOS_CISTATUS_VSYNC (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define EXYNOS_CISTATUS_SCALERSTART (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define EXYNOS_CISTATUS_WINOFSTEN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define EXYNOS_CISTATUS_IMGCPTEN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define EXYNOS_CISTATUS_IMGCPTENSC (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define EXYNOS_CISTATUS_VSYNC_A (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define EXYNOS_CISTATUS_VSYNC_B (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define EXYNOS_CISTATUS_OVRLB (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define EXYNOS_CISTATUS_FRAMEEND (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define EXYNOS_CISTATUS_LASTCAPTUREEND (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define EXYNOS_CISTATUS_VVALID_A (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define EXYNOS_CISTATUS_VVALID_B (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Image capture enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EXYNOS_CIIMGCPT_IMGCPTEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define EXYNOS_CIIMGCPT_IMGCPTEN_SC (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define EXYNOS_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define EXYNOS_CIIMGCPT_CPT_FRMOD_EN (0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define EXYNOS_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Image effects register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define EXYNOS_CIIMGEFF_IE_DISABLE (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define EXYNOS_CIIMGEFF_IE_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define EXYNOS_CIIMGEFF_IE_SC_BEFORE (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define EXYNOS_CIIMGEFF_IE_SC_AFTER (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define EXYNOS_CIIMGEFF_FIN_BYPASS (0 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define EXYNOS_CIIMGEFF_FIN_ARBITRARY (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define EXYNOS_CIIMGEFF_FIN_NEGATIVE (2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define EXYNOS_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define EXYNOS_CIIMGEFF_FIN_MASK (7 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define EXYNOS_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | (0xff << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Real input DMA size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define EXYNOS_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define EXYNOS_CIREAL_ISIZE_HEIGHT_MASK (0x3FFF << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define EXYNOS_CIREAL_ISIZE_WIDTH_MASK (0x3FFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Input DMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define EXYNOS_MSCTRL_FIELD_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define EXYNOS_MSCTRL_FIELD_WEAVE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define EXYNOS_MSCTRL_FIELD_NORMAL (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define EXYNOS_MSCTRL_BURST_CNT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define EXYNOS_MSCTRL_BURST_CNT_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define EXYNOS_MSCTRL_ORDER2P_LSB_CBCR (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define EXYNOS_MSCTRL_ORDER2P_LSB_CRCB (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define EXYNOS_MSCTRL_ORDER2P_MSB_CRCB (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define EXYNOS_MSCTRL_ORDER2P_MSB_CBCR (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define EXYNOS_MSCTRL_ORDER2P_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define EXYNOS_MSCTRL_C_INT_IN_3PLANE (0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define EXYNOS_MSCTRL_C_INT_IN_2PLANE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define EXYNOS_MSCTRL_FLIP_SHIFT (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define EXYNOS_MSCTRL_FLIP_NORMAL (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define EXYNOS_MSCTRL_FLIP_X_MIRROR (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define EXYNOS_MSCTRL_FLIP_Y_MIRROR (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define EXYNOS_MSCTRL_FLIP_180 (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define EXYNOS_MSCTRL_FLIP_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define EXYNOS_MSCTRL_ORDER422_CRYCBY (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define EXYNOS_MSCTRL_ORDER422_YCRYCB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define EXYNOS_MSCTRL_ORDER422_CBYCRY (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define EXYNOS_MSCTRL_ORDER422_YCBYCR (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define EXYNOS_MSCTRL_INPUT_EXTCAM (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define EXYNOS_MSCTRL_INPUT_MEMORY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define EXYNOS_MSCTRL_INPUT_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define EXYNOS_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EXYNOS_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define EXYNOS_MSCTRL_INFORMAT_RGB (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define EXYNOS_MSCTRL_ENVID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* DMA parameter register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EXYNOS_CIDMAPARAM_R_MODE_LINEAR (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define EXYNOS_CIDMAPARAM_R_MODE_CONFTILE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define EXYNOS_CIDMAPARAM_R_MODE_16X16 (2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EXYNOS_CIDMAPARAM_R_MODE_64X32 (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define EXYNOS_CIDMAPARAM_R_MODE_MASK (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define EXYNOS_CIDMAPARAM_W_MODE_LINEAR (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define EXYNOS_CIDMAPARAM_W_MODE_CONFTILE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define EXYNOS_CIDMAPARAM_W_MODE_16X16 (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define EXYNOS_CIDMAPARAM_W_MODE_64X32 (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define EXYNOS_CIDMAPARAM_W_MODE_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Gathering Extension register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define EXYNOS_CIEXTEN_TARGETH_EXT_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define EXYNOS_CIEXTEN_TARGETV_EXT_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK (0x3F << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK (0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define EXYNOS_CIEXTEN_YUV444_OUT (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* FIMC Clock Source Select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define EXYNOS_CLKSRC_HCLK (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define EXYNOS_CLKSRC_HCLK_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define EXYNOS_CLKSRC_SCLK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* SYSREG for FIMC writeback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SYSREG_CAMERA_BLK (0x0218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SYSREG_FIMD0WB_DEST_MASK (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SYSREG_FIMD0WB_DEST_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #endif /* EXYNOS_REGS_FIMC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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