Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef EXYNOS_REGS_DECON7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define EXYNOS_REGS_DECON7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* VIDCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define VIDCON0					0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define VIDCON0_SWRESET				(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define VIDCON0_DECON_STOP_STATUS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define VIDCON0_ENVID				(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define VIDCON0_ENVID_F				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* VIDOUTCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define VIDOUTCON0				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define VIDOUTCON0_DUAL_MASK			(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define VIDOUTCON0_DUAL_ON			(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define VIDOUTCON0_DISP_IF_1_ON			(0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define VIDOUTCON0_DISP_IF_0_ON			(0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VIDOUTCON0_DUAL_OFF			(0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define VIDOUTCON0_IF_SHIFT			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define VIDOUTCON0_IF_MASK			(0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VIDOUTCON0_RGBIF			(0x0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define VIDOUTCON0_I80IF			(0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* VIDCON3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VIDCON3					0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* VIDCON4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VIDCON4					0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VIDCON4_FIFOCNT_START_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* VCLKCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define VCLKCON0				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VCLKCON0_CLKVALUP			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define VCLKCON0_VCLKFREE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* VCLKCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VCLKCON1				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define VCLKCON1_CLKVAL_NUM_VCLK(val)		(((val) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define VCLKCON2				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* SHADOWCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SHADOWCON				0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* WINCONx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WINCON(_win)				(0x50 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WINCONx_BUFSTATUS			(0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WINCONx_BUFSEL_MASK			(0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WINCONx_BUFSEL_SHIFT			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WINCONx_BURSTLEN_16WORD			(0x0 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WINCONx_BURSTLEN_8WORD			(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WINCONx_BURSTLEN_MASK			(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define WINCONx_BURSTLEN_SHIFT			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define WINCONx_BLD_PLANE			(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WINCONx_BLD_PIX				(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WINCONx_ALPHA_MUL			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WINCONx_BPPMODE_MASK			(0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WINCONx_BPPMODE_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WINCONx_BPPMODE_16BPP_565		(0x8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WINCONx_BPPMODE_24BPP_BGRx		(0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WINCONx_BPPMODE_24BPP_RGBx		(0x6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WINCONx_BPPMODE_24BPP_xBGR		(0x5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WINCONx_BPPMODE_24BPP_xRGB		(0x4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WINCONx_BPPMODE_32BPP_BGRA		(0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WINCONx_BPPMODE_32BPP_RGBA		(0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WINCONx_BPPMODE_32BPP_ABGR		(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WINCONx_BPPMODE_32BPP_ARGB		(0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WINCONx_ALPHA_SEL			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WINCONx_ENWIN				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define WINCON1_ALPHA_MUL_F			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WINCON2_ALPHA_MUL_F			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WINCON3_ALPHA_MUL_F			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WINCON4_ALPHA_MUL_F			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /*  VIDOSDxH: The height for the OSD image(READ ONLY)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define VIDOSD_H(_x)				(0x80 + ((_x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* Frame buffer start addresses: VIDWxxADD0n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define VIDW_BUF_START(_win)			(0x80 + ((_win) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define VIDW_BUF_START1(_win)			(0x84 + ((_win) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VIDW_BUF_START2(_win)			(0x88 + ((_win) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define VIDW_OFFSET_X(_win)			(0x0170 + ((_win) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define VIDW_OFFSET_Y(_win)			(0x0174 + ((_win) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VIDW_BLKOFFSET(_win)			(0x01B0 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VIDW_BLKSIZE(win)			(0x0200 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Interrupt controls register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VIDINTCON2				0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VIDINTCON1_INTEXTRA1_EN			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VIDINTCON1_INTEXTRA0_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Interrupt controls and status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VIDINTCON3				0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VIDINTCON1_INTEXTRA1_PEND		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VIDINTCON1_INTEXTRA0_PEND		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* VIDOSDxA ~ VIDOSDxE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VIDOSD_BASE				0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OSD_STRIDE				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIDOSD_A(_win)				(VIDOSD_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 						((_win) * OSD_STRIDE) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIDOSD_B(_win)				(VIDOSD_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 						((_win) * OSD_STRIDE) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIDOSD_C(_win)				(VIDOSD_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 						((_win) * OSD_STRIDE) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIDOSD_D(_win)				(VIDOSD_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						((_win) * OSD_STRIDE) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIDOSD_E(_win)				(VIDOSD_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 						((_win) * OSD_STRIDE) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VIDOSDxA_TOPLEFT_X_MASK			(0x1fff << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VIDOSDxA_TOPLEFT_X_SHIFT		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIDOSDxA_TOPLEFT_X_LIMIT		0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x1fff) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIDOSDxA_TOPLEFT_Y_MASK			(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VIDOSDxA_TOPLEFT_Y_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VIDOSDxA_TOPLEFT_Y_LIMIT		0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x1fff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VIDOSDxB_BOTRIGHT_X_MASK		(0x1fff << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIDOSDxB_BOTRIGHT_X_SHIFT		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VIDOSDxB_BOTRIGHT_X_LIMIT		0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x1fff) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VIDOSDxB_BOTRIGHT_Y_MASK		(0x1fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x1fff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VIDOSDxC_ALPHA0_R_F(_x)			(((_x) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VIDOSDxC_ALPHA0_G_F(_x)			(((_x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIDOSDxC_ALPHA0_B_F(_x)			(((_x) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VIDOSDxD_ALPHA1_R_F(_x)			(((_x) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VIDOSDxD_ALPHA1_G_F(_x)			(((_x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIDOSDxD_ALPHA1_B_F(_x)			(((_x) & 0xFF) >> 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Window MAP (Color map) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WINxMAP(_win)				(0x340 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define WINxMAP_MAP				(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define WINxMAP_MAP_COLOUR_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Window colour-key control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WKEYCON					0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WKEYCON0				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WKEYCON1				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define WxKEYCON0_KEYBL_EN			(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define WxKEYCON0_KEYEN_F			(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define WxKEYCON0_DIRCON			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WxKEYCON0_COMPKEY_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WxKEYCON0_COMPKEY_LIMIT			0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WxKEYCON1_COLVAL_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define WxKEYCON1_COLVAL_LIMIT			0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WxKEYCON1_COLVAL(_x)			((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* color key control register for hardware window 1 ~ 4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WKEYCON0_BASE(x)		((WKEYCON + WKEYCON0) + ((x - 1) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* color key value register for hardware window 1 ~ 4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WKEYCON1_BASE(x)		((WKEYCON + WKEYCON1) + ((x - 1) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Window KEY Alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define WxKEYALPHA(_win)			(0x3A0 + (((_win) - 1) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define Wx_KEYALPHA_R_F_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define Wx_KEYALPHA_G_F_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define Wx_KEYALPHA_B_F_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Blending equation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BLENDE(_win)				(0x03C0 + ((_win) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BLENDE_COEF_ZERO			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BLENDE_COEF_ONE				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BLENDE_COEF_ALPHA_A			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BLENDE_COEF_ONE_MINUS_ALPHA_A		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BLENDE_COEF_ALPHA_B			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BLENDE_COEF_ONE_MINUS_ALPHA_B		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BLENDE_COEF_ALPHA0			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BLENDE_COEF_A				0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BLENDE_COEF_ONE_MINUS_A			0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BLENDE_COEF_B				0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BLENDE_COEF_ONE_MINUS_B			0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BLENDE_Q_FUNC(_v)			((_v) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BLENDE_P_FUNC(_v)			((_v) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BLENDE_B_FUNC(_v)			((_v) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define BLENDE_A_FUNC(_v)			((_v) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Blending equation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BLENDCON				0x3D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BLENDCON_NEW_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Interrupt control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VIDINTCON0				0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VIDINTCON0_WAKEUP_MASK			(0x3f << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VIDINTCON0_INTEXTRAEN			(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VIDINTCON0_FRAMESEL0_SHIFT		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VIDINTCON0_INT_FRAME			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VIDINTCON0_FIFOLEVEL_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VIDINTCON0_FIFOLEVEL_EMPTY		(0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VIDINTCON0_FIFOLEVEL_TO25PC		(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VIDINTCON0_FIFOLEVEL_TO50PC		(0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VIDINTCON0_FIFOSEL_MAIN_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VIDINTCON0_INT_FIFO			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define VIDINTCON0_INT_ENABLE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Interrupt controls and status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VIDINTCON1				0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VIDINTCON1_INT_EXTRA			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VIDINTCON1_INT_I80			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VIDINTCON1_INT_FRAME			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VIDINTCON1_INT_FIFO			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* VIDCON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VIDCON1(_x)				(0x0600 + ((_x) * 0x50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define VIDCON1_LINECNT_GET(_v)			(((_v) >> 17) & 0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define VIDCON1_VCLK_MASK			(0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VIDCON1_VCLK_HOLD			(0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define VIDCON1_VCLK_RUN			(0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VIDCON1_VCLK_RUN_VDEN_DISABLE		(0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VIDCON1_RGB_ORDER_O_MASK		(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define VIDCON1_RGB_ORDER_O_RGB			(0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define VIDCON1_RGB_ORDER_O_GBR			(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VIDCON1_RGB_ORDER_O_BRG			(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define VIDCON1_RGB_ORDER_O_BGR			(0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VIDCON1_RGB_ORDER_O_RBG			(0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VIDCON1_RGB_ORDER_O_GRB			(0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* VIDTCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define VIDTCON0				0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VIDTCON0_VBPD_MASK			(0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VIDTCON0_VBPD_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define VIDTCON0_VBPD_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define VIDTCON0_VBPD(_x)			((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define VIDTCON0_VFPD_MASK			(0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define VIDTCON0_VFPD_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VIDTCON0_VFPD_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define VIDTCON0_VFPD(_x)			((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* VIDTCON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define VIDTCON1				0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define VIDTCON1_VSPW_MASK			(0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define VIDTCON1_VSPW_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define VIDTCON1_VSPW_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define VIDTCON1_VSPW(_x)			((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* VIDTCON2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define VIDTCON2				0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define VIDTCON2_HBPD_MASK			(0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define VIDTCON2_HBPD_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VIDTCON2_HBPD_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VIDTCON2_HBPD(_x)			((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define VIDTCON2_HFPD_MASK			(0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VIDTCON2_HFPD_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define VIDTCON2_HFPD_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define VIDTCON2_HFPD(_x)			((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* VIDTCON3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define VIDTCON3				0x61C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VIDTCON3_HSPW_MASK			(0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define VIDTCON3_HSPW_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define VIDTCON3_HSPW_LIMIT			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VIDTCON3_HSPW(_x)			((_x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* VIDTCON4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define VIDTCON4				0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define VIDTCON4_LINEVAL_MASK			(0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VIDTCON4_LINEVAL_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VIDTCON4_LINEVAL_LIMIT			0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VIDTCON4_LINEVAL(_x)			(((_x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define VIDTCON4_HOZVAL_MASK			(0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define VIDTCON4_HOZVAL_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define VIDTCON4_HOZVAL_LIMIT			0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define VIDTCON4_HOZVAL(_x)			(((_x) & 0xfff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* LINECNT OP THRSHOLD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define LINECNT_OP_THRESHOLD			0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* CRCCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CRCCTRL					0x6C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CRCCTRL_CRCCLKEN			(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CRCCTRL_CRCSTART_F			(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CRCCTRL_CRCEN				(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* DECON_CMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DECON_CMU				0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DECON_CMU_ALL_CLKGATE_ENABLE		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DECON_CMU_SE_CLKGATE_ENABLE		(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DECON_CMU_SFR_CLKGATE_ENABLE		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DECON_CMU_MEM_CLKGATE_ENABLE		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* DECON_UPDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DECON_UPDATE				0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DECON_UPDATE_SLAVE_SYNC			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DECON_UPDATE_STANDALONE_F		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif /* EXYNOS_REGS_DECON7_H */