Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Samsung Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef EXYNOS_REGS_DECON5433_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define EXYNOS_REGS_DECON5433_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* Exynos543X DECON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define DECON_VIDCON0			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define DECON_VIDOUTCON0		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define DECON_WINCONx(n)		(0x0020 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DECON_VIDOSDxH(n)		(0x0080 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DECON_SHADOWCON			0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DECON_VIDOSDxA(n)		(0x00B0 + ((n) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DECON_VIDOSDxB(n)		(0x00B4 + ((n) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DECON_VIDOSDxC(n)		(0x00B8 + ((n) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DECON_VIDOSDxD(n)		(0x00BC + ((n) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DECON_VIDOSDxE(n)		(0x00C0 + ((n) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DECON_VIDW0xADD0B0(n)		(0x0150 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DECON_VIDW0xADD0B1(n)		(0x0154 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DECON_VIDW0xADD0B2(n)		(0x0158 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DECON_VIDW0xADD1B0(n)		(0x01A0 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DECON_VIDW0xADD1B1(n)		(0x01A4 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DECON_VIDW0xADD1B2(n)		(0x01A8 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DECON_VIDW0xADD2(n)		(0x0200 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DECON_LOCALxSIZE(n)		(0x0214 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DECON_VIDINTCON0		0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DECON_VIDINTCON1		0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DECON_WxKEYCON0(n)		(0x0230 + ((n - 1) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DECON_WxKEYCON1(n)		(0x0234 + ((n - 1) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DECON_WxKEYALPHA(n)		(0x0250 + ((n - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DECON_WINxMAP(n)		(0x0270 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DECON_QOSLUT07_00		0x02C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DECON_QOSLUT15_08		0x02C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DECON_QOSCTRL			0x02C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DECON_BLENDERQx(n)		(0x0300 + ((n - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DECON_BLENDCON			0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DECON_OPE_VIDW0xADD0(n)		(0x0400 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DECON_OPE_VIDW0xADD1(n)		(0x0414 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DECON_FRAMEFIFO_REG7		0x051C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DECON_FRAMEFIFO_REG8		0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DECON_FRAMEFIFO_STATUS		0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DECON_CMU			0x1404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DECON_UPDATE			0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DECON_CRFMID			0x1414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DECON_UPDATE_SCHEME		0x1438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DECON_VIDCON1			0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DECON_VIDCON2			0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DECON_VIDCON3			0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DECON_VIDCON4			0x200C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DECON_VIDTCON2			0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DECON_FRAME_SIZE		0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DECON_LINECNT_OP_THRESHOLD	0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DECON_TRIGCON			0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DECON_TRIGSKIP			0x2050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DECON_CRCRDATA			0x20B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DECON_CRCCTRL			0x20B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Exynos5430 DECON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DECON_VIDTCON0			0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DECON_VIDTCON1			0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Exynos5433 DECON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DECON_VIDTCON00			0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DECON_VIDTCON01			0x2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DECON_VIDTCON10			0x2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DECON_VIDTCON11			0x201C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Exynos543X DECON Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DECON_W013DSTREOCON		0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DECON_W233DSTREOCON		0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DECON_FRAMEFIFO_REG0		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DECON_ENHANCER_CTRL		0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Exynos543X DECON TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DECON_VCLKCON0			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DECON_VIDINTCON2		0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DECON_VIDINTCON3		0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* VIDCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define VIDCON0_SWRESET			(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define VIDCON0_CLKVALUP		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define VIDCON0_VLCKFREE		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define VIDCON0_STOP_STATUS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define VIDCON0_ENVID			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define VIDCON0_ENVID_F			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* VIDOUTCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define VIDOUT_INTERLACE_EN_F		(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define VIDOUT_LCD_ON			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define VIDOUT_IF_F_MASK		(0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VIDOUT_RGB_IF			(0x0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define VIDOUT_COMMAND_IF		(0x2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* WINCONx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define WINCONx_HAWSWP_F		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define WINCONx_WSWP_F			(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WINCONx_BURSTLEN_MASK		(0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WINCONx_BURSTLEN_16WORD		(0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WINCONx_BURSTLEN_8WORD		(0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WINCONx_BURSTLEN_4WORD		(0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WINCONx_ALPHA_MUL_F		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WINCONx_BLD_PIX_F		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WINCONx_BPPMODE_MASK		(0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WINCONx_BPPMODE_16BPP_565	(0x5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WINCONx_BPPMODE_16BPP_A1555	(0x6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WINCONx_BPPMODE_16BPP_I1555	(0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WINCONx_BPPMODE_24BPP_888	(0xb << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WINCONx_BPPMODE_24BPP_A1887	(0xc << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WINCONx_BPPMODE_25BPP_A1888	(0xd << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WINCONx_BPPMODE_32BPP_A8888	(0xd << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WINCONx_BPPMODE_16BPP_A4444	(0xe << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WINCONx_ALPHA_SEL_F		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WINCONx_ENWIN_F			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WINCONx_BLEND_MODE_MASK		(0xc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* SHADOWCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SHADOWCON_PROTECT_MASK		GENMASK(14, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SHADOWCON_Wx_PROTECT(n)		(1 << (10 + (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* VIDOSDxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIDOSDxC_ALPHA0_RGB_MASK	(0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* VIDOSDxD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VIDOSD_Wx_ALPHA_R_F(n)		(((n) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIDOSD_Wx_ALPHA_G_F(n)		(((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VIDOSD_Wx_ALPHA_B_F(n)		(((n) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* VIDINTCON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VIDINTCON0_FRAMEDONE		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIDINTCON0_FRAMESEL_BP		(0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VIDINTCON0_FRAMESEL_VS		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VIDINTCON0_FRAMESEL_AC		(2 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIDINTCON0_FRAMESEL_FP		(3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VIDINTCON0_INTFRMEN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VIDINTCON0_INTEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* VIDINTCON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VIDINTCON1_INTFRMDONEPEND	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIDINTCON1_INTFRMPEND		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VIDINTCON1_INTFIFOPEND		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* DECON_CMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMU_CLKGAGE_MODE_SFR_F		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMU_CLKGAGE_MODE_MEM_F		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* DECON_UPDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define STANDALONE_UPDATE_F		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* DECON_VIDCON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIDCON1_LINECNT_MASK		(0x0fff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VIDCON1_I80_ACTIVE		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VIDCON1_VSTATUS_MASK		(0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VIDCON1_VSTATUS_VS		(0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIDCON1_VSTATUS_BP		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VIDCON1_VSTATUS_AC		(2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIDCON1_VSTATUS_FP		(3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VIDCON1_VCLK_MASK		(0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIDCON1_VCLK_RUN_VDEN_DISABLE	(0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VIDCON1_VCLK_HOLD		(0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VIDCON1_VCLK_RUN		(0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* DECON_VIDTCON00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VIDTCON00_VBPD_F(x)		(((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VIDTCON00_VFPD_F(x)		((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* DECON_VIDTCON01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VIDTCON01_VSPW_F(x)		(((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* DECON_VIDTCON10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VIDTCON10_HBPD_F(x)		(((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VIDTCON10_HFPD_F(x)		((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* DECON_VIDTCON11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VIDTCON11_HSPW_F(x)		(((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* DECON_VIDTCON2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VIDTCON2_LINEVAL(x)		(((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VIDTCON2_HOZVAL(x)		((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* TRIGCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TRIGCON_TRIGEN_PER_F		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TRIGCON_TRIGEN_F		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TRIGCON_TE_AUTO_MASK		(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TRIGCON_WB_SWTRIGCMD		(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TRIGCON_SWTRIGCMD_W4BUF		(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TRIGCON_TRIGMODE_W4BUF		(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TRIGCON_SWTRIGCMD_W3BUF		(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TRIGCON_TRIGMODE_W3BUF		(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TRIGCON_SWTRIGCMD_W2BUF		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TRIGCON_TRIGMODE_W2BUF		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TRIGCON_SWTRIGCMD_W1BUF		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TRIGCON_TRIGMODE_W1BUF		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TRIGCON_SWTRIGCMD_W0BUF		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TRIGCON_TRIGMODE_W0BUF		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TRIGCON_HWTRIGMASK		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TRIGCON_HWTRIGEN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TRIGCON_HWTRIG_INV		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TRIGCON_SWTRIGCMD		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TRIGCON_SWTRIGEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* DECON_CRCCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CRCCTRL_CRCCLKEN		(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CRCCTRL_CRCSTART_F		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CRCCTRL_CRCEN			(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CRCCTRL_MASK			(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* BLENDCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BLEND_NEW			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* BLENDERQx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BLENDERQ_ZERO			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BLENDERQ_ONE			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BLENDERQ_ALPHA_A		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BLENDERQ_ONE_MINUS_ALPHA_A	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BLENDERQ_ALPHA0			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BLENDERQ_Q_FUNC_F(n)		(n << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BLENDERQ_P_FUNC_F(n)		(n << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BLENDERQ_B_FUNC_F(n)		(n << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BLENDERQ_A_FUNC_F(n)		(n << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* BLENDCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BLEND_NEW			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif /* EXYNOS_REGS_DECON5433_H */