^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) #ifndef STATE_XML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define STATE_XML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Autogenerated file, DO NOT EDIT manually!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This file was generated by the rules-ng-ng headergen tool in this git repository:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) http://0x04.net/cgit/index.cgi/rules-ng-ng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) git clone git://0x04.net/rules-ng-ng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The rules-ng-ng source files this header was generated from are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Copyright (C) 2012-2017 by the following authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - Wladimir J. van der Laan <laanwj@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - Christian Gmeiner <christian.gmeiner@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - Lucas Stach <l.stach@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - Russell King <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) the rights to use, copy, modify, merge, publish, distribute, sub license,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VARYING_COMPONENT_USE_UNUSED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VARYING_COMPONENT_USE_USED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FE_DATA_TYPE_BYTE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FE_DATA_TYPE_SHORT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FE_DATA_TYPE_INT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FE_DATA_TYPE_FLOAT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FE_DATA_TYPE_HALF_FLOAT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FE_DATA_TYPE_FIXED 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FE_DATA_TYPE_BYTE_I 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FE_DATA_TYPE_SHORT_I 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VIVS_FE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VIVS_FE_COMMAND_ADDRESS 0x00000654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VIVS_FE_COMMAND_CONTROL 0x00000658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VIVS_FE_DMA_STATUS 0x0000065c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIVS_FE_DMA_DEBUG_STATE 0x00000660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VIVS_FE_DMA_ADDRESS 0x00000664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VIVS_FE_DMA_LOW 0x00000668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VIVS_FE_DMA_HIGH 0x0000066c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VIVS_FE_AUTO_FLUSH 0x00000670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VIVS_FE_UNK00678 0x00000678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define VIVS_FE_UNK0067C 0x0000067c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define VIVS_FE_HALTI5_UNK007C4 0x000007c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define VIVS_FE_HALTI5_UNK007D8 0x000007d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VIVS_FE_DESC_START 0x000007dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VIVS_FE_DESC_END 0x000007e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VIVS_FE_DESC_AVAIL 0x000007e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VIVS_GL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VIVS_GL_PIPE_SELECT 0x00003800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VIVS_GL_EVENT 0x00003804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VIVS_GL_EVENT_EVENT_ID__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define VIVS_GL_EVENT_FROM_FE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define VIVS_GL_EVENT_FROM_PE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define VIVS_GL_EVENT_FROM_BLT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VIVS_GL_EVENT_SOURCE__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VIVS_GL_SEMAPHORE_TOKEN 0x00003808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define VIVS_GL_FLUSH_CACHE 0x0000380c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define VIVS_GL_FLUSH_MMU 0x00003810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define VIVS_GL_UNK0382C 0x0000382c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define VIVS_GL_UNK03834 0x00003834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define VIVS_GL_UNK03838 0x00003838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define VIVS_GL_API_MODE 0x0000384c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define VIVS_GL_API_MODE_OPENGL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define VIVS_GL_API_MODE_OPENVG 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VIVS_GL_API_MODE_OPENCL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define VIVS_GL_CONTEXT_POINTER 0x00003850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define VIVS_GL_UNK03854 0x00003854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define VIVS_GL_BUG_FIXES 0x00003860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define VIVS_GL_HALTI5_UNK03884 0x00003884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define VIVS_GL_GS_UNK0388C 0x0000388c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define VIVS_GL_SHADER_INDEX 0x0000389c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define VIVS_GL_GS_UNK038A0__LEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define VIVS_GL_SECURITY_UNK3900 0x00003900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define VIVS_GL_SECURITY_UNK3904 0x00003904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define VIVS_GL_UNK03A00 0x00003a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define VIVS_GL_UNK03A04 0x00003a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define VIVS_GL_UNK03A08 0x00003a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define VIVS_GL_UNK03A0C 0x00003a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define VIVS_GL_UNK03A10 0x00003a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define VIVS_GL_STALL_TOKEN 0x00003c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define VIVS_GL_STALL_TOKEN_TO__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define VIVS_NFE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define VIVS_DUMMY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define VIVS_DUMMY_DUMMY 0x0003fffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif /* STATE_XML */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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