^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright © 1997-2003 by The XFree86 Project, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2007 Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2007-2008 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jesse Barnes <jesse.barnes@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2005-2006 Luc Verhaegen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2001, Andy Ritger aritger@nvidia.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Except as contained in this notice, the name of the copyright holder(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * and author(s) shall not be used in advertising or otherwise to promote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the sale, use or other dealings in this Software without prior written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * authorization from the copyright holder(s) and author(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/list_sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <video/of_videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <drm/drm_modes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "drm_crtc_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * drm_mode_debug_printmodeline - print a mode to dmesg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @mode: mode to print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Describe @mode using DRM_DEBUG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void drm_mode_debug_printmodeline(const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DRM_DEBUG_KMS("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) EXPORT_SYMBOL(drm_mode_debug_printmodeline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * drm_mode_create - create a new display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @dev: DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Create a new, cleared drm_display_mode with kzalloc, allocate an ID for it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * and return it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Pointer to new mode on success, NULL on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct drm_display_mode *drm_mode_create(struct drm_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct drm_display_mode *nmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) nmode = kzalloc(sizeof(struct drm_display_mode), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!nmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return nmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) EXPORT_SYMBOL(drm_mode_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * drm_mode_destroy - remove a mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @dev: DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @mode: mode to remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Release @mode's unique ID, then free it @mode structure itself using kfree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) kfree(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EXPORT_SYMBOL(drm_mode_destroy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * drm_mode_probed_add - add a mode to a connector's probed_mode list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @connector: connector the new mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @mode: mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Add @mode to @connector's probed_mode list for later use. This list should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * then in a second step get filtered and all the modes actually supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * the hardware moved to the @connector's modes list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void drm_mode_probed_add(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) list_add_tail(&mode->head, &connector->probed_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXPORT_SYMBOL(drm_mode_probed_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * drm_cvt_mode -create a modeline based on the CVT algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @dev: drm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @hdisplay: hdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @vdisplay: vdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @vrefresh: vrefresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @reduced: whether to use reduced blanking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @interlaced: whether to compute an interlaced mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @margins: whether to add margins (borders)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * This function is called to generate the modeline based on CVT algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * according to the hdisplay, vdisplay, vrefresh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * It is based from the VESA(TM) Coordinated Video Timing Generator by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Graham Loveridge April 9, 2003 available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * What I have done is to translate it by using integer calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * The modeline based on the CVT algorithm stored in a drm_display_mode object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * The display mode object is allocated with drm_mode_create(). Returns NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * when no mode could be allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int vdisplay, int vrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool reduced, bool interlaced, bool margins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HV_FACTOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* 1) top/bottom margin size (% of height) - default: 1.8, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CVT_MARGIN_PERCENTAGE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* 2) character cell horizontal granularity (pixels) - default 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CVT_H_GRANULARITY 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 3) Minimum vertical porch (lines) - default 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CVT_MIN_V_PORCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* 4) Minimum number of vertical back porch lines - default 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CVT_MIN_V_BPORCH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Pixel Clock step (kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CVT_CLOCK_STEP 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct drm_display_mode *drm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int vfieldrate, hperiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!hdisplay || !vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* allocate the drm_display_mode structure. If failure, we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * return directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) drm_mode = drm_mode_create(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!drm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* the CVT default refresh rate is 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!vrefresh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) vrefresh = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* the required field fresh rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) vfieldrate = vrefresh * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) vfieldrate = vrefresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* horizontal pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* determine the left&right borders */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) hmargin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (margins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) hmargin -= hmargin % CVT_H_GRANULARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* find the total active pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* find the number of lines per field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) vdisplay_rnd = vdisplay / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) vdisplay_rnd = vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* find the top & bottom borders */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) vmargin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (margins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) drm_mode->vdisplay = vdisplay + 2 * vmargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) interlace = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) interlace = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Determine VSync Width from aspect ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vsync = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vsync = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) vsync = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) vsync = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) vsync = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) else /* custom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) vsync = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!reduced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* simplify the GTF calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* 4) Minimum time of vertical sync + back porch interval (µs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * default 550.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CVT_MIN_VSYNC_BP 550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* 3) Nominal HSync width (% of line period) - default 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CVT_HSYNC_PERCENTAGE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int hblank_percentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int vsyncandback_porch, __maybe_unused vback_porch, hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* estimated the horizontal period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp1 = HV_FACTOR * 1000000 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 9. Find number of lines in sync + backporch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (tmp1 < (vsync + CVT_MIN_V_PORCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) vsyncandback_porch = tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* 10. Find number of lines in back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) vback_porch = vsyncandback_porch - vsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) vsyncandback_porch + CVT_MIN_V_PORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 5) Definition of Horizontal blanking time limitation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Gradient (%/kHz) - default 600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CVT_M_FACTOR 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Offset (%) - default 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CVT_C_FACTOR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Blanking time scaling factor - default 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CVT_K_FACTOR 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Scaling factor weighting - default 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CVT_J_FACTOR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CVT_J_FACTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* 12. Find ideal blanking duty cycle from formula */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hperiod / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* 13. Blanking time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (hblank_percentage < 20 * HV_FACTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) hblank_percentage = 20 * HV_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hblank = drm_mode->hdisplay * hblank_percentage /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (100 * HV_FACTOR - hblank_percentage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hblank -= hblank % (2 * CVT_H_GRANULARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* 14. find the total pixels per line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) drm_mode->htotal = drm_mode->hdisplay + hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) drm_mode->hsync_start = drm_mode->hsync_end -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) drm_mode->hsync_start += CVT_H_GRANULARITY -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) drm_mode->hsync_start % CVT_H_GRANULARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* fill the Vsync values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) drm_mode->vsync_end = drm_mode->vsync_start + vsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Reduced blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Minimum vertical blanking interval time (µs)- default 460 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CVT_RB_MIN_VBLANK 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Fixed number of clocks for horizontal sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CVT_RB_H_SYNC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Fixed number of clocks for horizontal blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CVT_RB_H_BLANK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Fixed number of lines for vertical front porch - default 3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CVT_RB_VFPORCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int vbilines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* 8. Estimate Horizontal period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmp1 = HV_FACTOR * 1000000 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp2 = vdisplay_rnd + 2 * vmargin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hperiod = tmp1 / (tmp2 * vfieldrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* 9. Find number of lines in vertical blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 10. Check if vertical blanking is sufficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* 11. Find total number of lines in vertical field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* 12. Find total number of pixels in a line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Fill in HSync values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Fill in VSync values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) drm_mode->vsync_end = drm_mode->vsync_start + vsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* 15/13. Find pixel clock frequency (kHz for xf86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tmp *= HV_FACTOR * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) do_div(tmp, hperiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tmp -= drm_mode->clock % CVT_CLOCK_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) drm_mode->clock = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* 18/16. Find actual vertical frame frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* ignore - just set the mode flag for interlaced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (interlaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) drm_mode->vtotal *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Fill the mode line name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) drm_mode_set_name(drm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (reduced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DRM_MODE_FLAG_NVSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DRM_MODE_FLAG_NHSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return drm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXPORT_SYMBOL(drm_cvt_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * drm_gtf_mode_complex - create the modeline based on the full GTF algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @dev: drm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @hdisplay: hdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @vdisplay: vdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @vrefresh: vrefresh rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @interlaced: whether to compute an interlaced mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @margins: desired margin (borders) size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @GTF_M: extended GTF formula parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @GTF_2C: extended GTF formula parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @GTF_K: extended GTF formula parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @GTF_2J: extended GTF formula parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * GTF feature blocks specify C and J in multiples of 0.5, so we pass them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * in here multiplied by two. For a C of 40, pass in 80.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * The modeline based on the full GTF algorithm stored in a drm_display_mode object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * The display mode object is allocated with drm_mode_create(). Returns NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * when no mode could be allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct drm_display_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int vrefresh, bool interlaced, int margins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int GTF_M, int GTF_2C, int GTF_K, int GTF_2J)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { /* 1) top/bottom margin size (% of height) - default: 1.8, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define GTF_MARGIN_PERCENTAGE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* 2) character cell horizontal granularity (pixels) - default 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define GTF_CELL_GRAN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* 3) Minimum vertical porch (lines) - default 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define GTF_MIN_V_PORCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* width of vsync in lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define V_SYNC_RQD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* width of hsync as % of total line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define H_SYNC_PERCENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* min time of vsync + back porch (microsec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MIN_VSYNC_PLUS_BP 550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* C' and M' are part of the Blanking Duty Cycle computation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define GTF_M_PRIME (GTF_K * GTF_M / 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct drm_display_mode *drm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int top_margin, bottom_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int hfreq_est;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int vsync_plus_bp, __maybe_unused vback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int vtotal_lines, __maybe_unused vfieldrate_est;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int __maybe_unused hperiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int vfield_rate, __maybe_unused vframe_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int left_margin, right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int total_active_pixels, ideal_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int hblank, total_pixels, pixel_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int hsync, hfront_porch, vodd_front_porch_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!hdisplay || !vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) drm_mode = drm_mode_create(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!drm_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* 1. In order to give correct results, the number of horizontal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * pixels requested is first processed to ensure that it is divisible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * by the character size, by rounding it to the nearest character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * cell boundary:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* 2. If interlace is requested, the number of vertical lines assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * by the calculation must be halved, as the computation calculates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * the number of vertical lines per field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) vdisplay_rnd = vdisplay / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) vdisplay_rnd = vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* 3. Find the frame rate required: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vfieldrate_rqd = vrefresh * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) vfieldrate_rqd = vrefresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* 4. Find number of lines in Top margin: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) top_margin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (margins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* 5. Find number of lines in bottom margin: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bottom_margin = top_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* 6. If interlace is required, then set variable interlace: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) interlace = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) interlace = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* 7. Estimate the Horizontal frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 2 + interlace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* 8. Find the number of lines in V sync + back porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) vsync_plus_bp = (vsync_plus_bp + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* 9. Find the number of lines in V back porch alone: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vback_porch = vsync_plus_bp - V_SYNC_RQD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* 10. Find the total number of lines in Vertical field period: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) vtotal_lines = vdisplay_rnd + top_margin + bottom_margin +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) vsync_plus_bp + GTF_MIN_V_PORCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* 11. Estimate the Vertical field frequency: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) vfieldrate_est = hfreq_est / vtotal_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* 12. Find the actual horizontal period: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* 13. Find the actual Vertical field frequency: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) vfield_rate = hfreq_est / vtotal_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* 14. Find the Vertical frame frequency: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) vframe_rate = vfield_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) vframe_rate = vfield_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* 15. Find number of pixels in left margin: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (margins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) left_margin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* 16.Find number of pixels in right margin: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) right_margin = left_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* 17.Find total number of active pixels in image and left and right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) total_active_pixels = hdisplay_rnd + left_margin + right_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* 18.Find the ideal blanking duty cycle from blanking duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ideal_duty_cycle = GTF_C_PRIME * 1000 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (GTF_M_PRIME * 1000000 / hfreq_est);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* 19.Find the number of pixels in the blanking time to the nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * double character cell: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hblank = total_active_pixels * ideal_duty_cycle /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (100000 - ideal_duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hblank = hblank * 2 * GTF_CELL_GRAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* 20.Find total number of pixels: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) total_pixels = total_active_pixels + hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* 21.Find pixel clock frequency: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pixel_freq = total_pixels * hfreq_est / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Stage 1 computations are now complete; I should really pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * the results to another function and do the Stage 2 computations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * but I only need a few more values so I'll just append the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * computations here for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* 17. Find the number of pixels in the horizontal sync period: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hsync = H_SYNC_PERCENT * total_pixels / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hsync = hsync * GTF_CELL_GRAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* 18. Find the number of pixels in horizontal front porch period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hfront_porch = hblank / 2 - hsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* 36. Find the number of lines in the odd front porch period: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) vodd_front_porch_lines = GTF_MIN_V_PORCH ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* finally, pack the results in the mode struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) drm_mode->hdisplay = hdisplay_rnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) drm_mode->hsync_end = drm_mode->hsync_start + hsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) drm_mode->htotal = total_pixels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) drm_mode->vdisplay = vdisplay_rnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) drm_mode->vtotal = vtotal_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) drm_mode->clock = pixel_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (interlaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) drm_mode->vtotal *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) drm_mode_set_name(drm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return drm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) EXPORT_SYMBOL(drm_gtf_mode_complex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * drm_gtf_mode - create the modeline based on the GTF algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @dev: drm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @hdisplay: hdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @vdisplay: vdisplay size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @vrefresh: vrefresh rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @interlaced: whether to compute an interlaced mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @margins: desired margin (borders) size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * return the modeline based on GTF algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * This function is to create the modeline based on the GTF algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Generalized Timing Formula is derived from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * GTF Spreadsheet by Andy Morrish (1/5/97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * available at https://www.vesa.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * What I have done is to translate it by using integer calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * I also refer to the function of fb_get_mode in the file of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * drivers/video/fbmon.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Standard GTF parameters::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * M = 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * C = 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * K = 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * J = 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * The modeline based on the GTF algorithm stored in a drm_display_mode object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * The display mode object is allocated with drm_mode_create(). Returns NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * when no mode could be allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct drm_display_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) drm_gtf_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bool interlaced, int margins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return drm_gtf_mode_complex(dev, hdisplay, vdisplay, vrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) interlaced, margins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 600, 40 * 2, 128, 20 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) EXPORT_SYMBOL(drm_gtf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #ifdef CONFIG_VIDEOMODE_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * drm_display_mode_from_videomode - fill in @dmode using @vm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * @vm: videomode structure to use as source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * @dmode: drm_display_mode structure to use as destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Fills out @dmode using the display mode specified in @vm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void drm_display_mode_from_videomode(const struct videomode *vm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct drm_display_mode *dmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dmode->hdisplay = vm->hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dmode->htotal = dmode->hsync_end + vm->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dmode->vdisplay = vm->vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dmode->vtotal = dmode->vsync_end + vm->vback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dmode->clock = vm->pixelclock / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dmode->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dmode->flags |= DRM_MODE_FLAG_PHSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dmode->flags |= DRM_MODE_FLAG_NHSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dmode->flags |= DRM_MODE_FLAG_PVSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) else if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dmode->flags |= DRM_MODE_FLAG_NVSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (vm->flags & DISPLAY_FLAGS_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dmode->flags |= DRM_MODE_FLAG_INTERLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dmode->flags |= DRM_MODE_FLAG_DBLCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) drm_mode_set_name(dmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * drm_display_mode_to_videomode - fill in @vm using @dmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @dmode: drm_display_mode structure to use as source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @vm: videomode structure to use as destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Fills out @vm using the display mode specified in @dmode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct videomode *vm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) vm->hactive = dmode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) vm->hfront_porch = dmode->hsync_start - dmode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) vm->hsync_len = dmode->hsync_end - dmode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) vm->hback_porch = dmode->htotal - dmode->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) vm->vactive = dmode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) vm->vfront_porch = dmode->vsync_start - dmode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) vm->vsync_len = dmode->vsync_end - dmode->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) vm->vback_porch = dmode->vtotal - dmode->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vm->pixelclock = dmode->clock * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) vm->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (dmode->flags & DRM_MODE_FLAG_PHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else if (dmode->flags & DRM_MODE_FLAG_NHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) vm->flags |= DISPLAY_FLAGS_HSYNC_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (dmode->flags & DRM_MODE_FLAG_PVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) vm->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else if (dmode->flags & DRM_MODE_FLAG_NVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) vm->flags |= DISPLAY_FLAGS_VSYNC_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (dmode->flags & DRM_MODE_FLAG_INTERLACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) vm->flags |= DISPLAY_FLAGS_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (dmode->flags & DRM_MODE_FLAG_DBLSCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) vm->flags |= DISPLAY_FLAGS_DOUBLESCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (dmode->flags & DRM_MODE_FLAG_DBLCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) vm->flags |= DISPLAY_FLAGS_DOUBLECLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) EXPORT_SYMBOL_GPL(drm_display_mode_to_videomode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * drm_bus_flags_from_videomode - extract information about pixelclk and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * DE polarity from videomode and store it in a separate variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @vm: videomode structure to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @bus_flags: information about pixelclk, sync and DE polarity will be stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Sets DRM_BUS_FLAG_DE_(LOW|HIGH), DRM_BUS_FLAG_PIXDATA_DRIVE_(POS|NEG)EDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * and DISPLAY_FLAGS_SYNC_(POS|NEG)EDGE in @bus_flags according to DISPLAY_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * found in @vm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *bus_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) *bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) *bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *bus_flags |= DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (vm->flags & DISPLAY_FLAGS_SYNC_NEGEDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *bus_flags |= DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (vm->flags & DISPLAY_FLAGS_DE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *bus_flags |= DRM_BUS_FLAG_DE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *bus_flags |= DRM_BUS_FLAG_DE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) EXPORT_SYMBOL_GPL(drm_bus_flags_from_videomode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * of_get_drm_display_mode - get a drm_display_mode from devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * @np: device_node with the timing specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @dmode: will be set to the return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @bus_flags: information about pixelclk, sync and DE polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @index: index into the list of display timings in devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * This function is expensive and should only be used, if only one mode is to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * read from DT. To get multiple modes start with of_get_display_timings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * work with that instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * 0 on success, a negative errno code when no of videomode node was found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int of_get_drm_display_mode(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct drm_display_mode *dmode, u32 *bus_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct videomode vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = of_get_videomode(np, &vm, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) drm_display_mode_from_videomode(&vm, dmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (bus_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) drm_bus_flags_from_videomode(&vm, bus_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pr_debug("%pOF: got %dx%d display mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) np, vm.hactive, vm.vactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) drm_mode_debug_printmodeline(dmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) EXPORT_SYMBOL_GPL(of_get_drm_display_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #endif /* CONFIG_VIDEOMODE_HELPERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * drm_mode_set_name - set the name on a mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * @mode: name will be set in this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Set the name of @mode to a standard format which is <hdisplay>x<vdisplay>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * with an optional 'i' suffix for interlaced modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) void drm_mode_set_name(struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mode->hdisplay, mode->vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) interlaced ? "i" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) EXPORT_SYMBOL(drm_mode_set_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * drm_mode_vrefresh - get the vrefresh of a mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * @mode: mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * @modes's vrefresh rate in Hz, rounded to the nearest integer. Calculates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * value first if it is not yet set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int drm_mode_vrefresh(const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int num, den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (mode->htotal == 0 || mode->vtotal == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) num = mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) den = mode->htotal * mode->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (mode->flags & DRM_MODE_FLAG_INTERLACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) num *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) den *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (mode->vscan > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) den *= mode->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) EXPORT_SYMBOL(drm_mode_vrefresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * drm_mode_get_hv_timing - Fetches hdisplay/vdisplay for given mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * @mode: mode to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * @hdisplay: hdisplay value to fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * @vdisplay: vdisplay value to fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * The vdisplay value will be doubled if the specified mode is a stereo mode of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * the appropriate layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void drm_mode_get_hv_timing(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int *hdisplay, int *vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct drm_display_mode adjusted = *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) drm_mode_set_crtcinfo(&adjusted, CRTC_STEREO_DOUBLE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *hdisplay = adjusted.crtc_hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *vdisplay = adjusted.crtc_vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) EXPORT_SYMBOL(drm_mode_get_hv_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * @p: mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * @adjust_flags: a combination of adjustment flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * interlaced modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * buffers containing two eyes (only adjust the timings when needed, eg. for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * "frame packing" or "side by side full").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * be performed for doublescan and vscan > 1 modes respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) p->crtc_clock = p->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) p->crtc_hdisplay = p->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) p->crtc_hsync_start = p->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) p->crtc_hsync_end = p->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) p->crtc_htotal = p->htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) p->crtc_hskew = p->hskew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) p->crtc_vdisplay = p->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) p->crtc_vsync_start = p->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) p->crtc_vsync_end = p->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) p->crtc_vtotal = p->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (p->flags & DRM_MODE_FLAG_INTERLACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) p->crtc_vdisplay /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) p->crtc_vsync_start /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) p->crtc_vsync_end /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) p->crtc_vtotal /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) p->crtc_vdisplay *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) p->crtc_vsync_start *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) p->crtc_vsync_end *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) p->crtc_vtotal *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!(adjust_flags & CRTC_NO_VSCAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (p->vscan > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) p->crtc_vdisplay *= p->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) p->crtc_vsync_start *= p->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) p->crtc_vsync_end *= p->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) p->crtc_vtotal *= p->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (adjust_flags & CRTC_STEREO_DOUBLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) switch (layout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case DRM_MODE_FLAG_3D_FRAME_PACKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) p->crtc_clock *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) p->crtc_vdisplay += p->crtc_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) p->crtc_vsync_start += p->crtc_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) p->crtc_vsync_end += p->crtc_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) p->crtc_vtotal += p->crtc_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) EXPORT_SYMBOL(drm_mode_set_crtcinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * drm_mode_copy - copy the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @dst: mode to overwrite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * @src: mode to copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * Copy an existing mode into another mode, preserving the object id and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * list head of the destination mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct list_head head = dst->head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) *dst = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dst->head = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) EXPORT_SYMBOL(drm_mode_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * drm_mode_duplicate - allocate and duplicate an existing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * @dev: drm_device to allocate the duplicated mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * @mode: mode to duplicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Just allocate a new mode, copy the existing mode into it, and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * a pointer to it. Used to create new instances of established modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Pointer to duplicated mode on success, NULL on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct drm_display_mode *nmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) nmode = drm_mode_create(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!nmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) drm_mode_copy(nmode, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return nmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) EXPORT_SYMBOL(drm_mode_duplicate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static bool drm_mode_match_timings(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return mode1->hdisplay == mode2->hdisplay &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mode1->hsync_start == mode2->hsync_start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mode1->hsync_end == mode2->hsync_end &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mode1->htotal == mode2->htotal &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mode1->hskew == mode2->hskew &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mode1->vdisplay == mode2->vdisplay &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mode1->vsync_start == mode2->vsync_start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) mode1->vsync_end == mode2->vsync_end &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) mode1->vtotal == mode2->vtotal &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mode1->vscan == mode2->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static bool drm_mode_match_clock(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * do clock check convert to PICOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * so fb modes get matched the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (mode1->clock && mode2->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return KHZ2PICOS(mode1->clock) == KHZ2PICOS(mode2->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return mode1->clock == mode2->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static bool drm_mode_match_flags(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return (mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (mode2->flags & ~DRM_MODE_FLAG_3D_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static bool drm_mode_match_3d_flags(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return (mode1->flags & DRM_MODE_FLAG_3D_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) (mode2->flags & DRM_MODE_FLAG_3D_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static bool drm_mode_match_aspect_ratio(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return mode1->picture_aspect_ratio == mode2->picture_aspect_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * drm_mode_match - test modes for (partial) equality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * @mode1: first mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * @mode2: second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * @match_flags: which parts need to match (DRM_MODE_MATCH_*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Check to see if @mode1 and @mode2 are equivalent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * True if the modes are (partially) equal, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) bool drm_mode_match(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) const struct drm_display_mode *mode2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int match_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!mode1 && !mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!mode1 || !mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (match_flags & DRM_MODE_MATCH_TIMINGS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) !drm_mode_match_timings(mode1, mode2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (match_flags & DRM_MODE_MATCH_CLOCK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) !drm_mode_match_clock(mode1, mode2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (match_flags & DRM_MODE_MATCH_FLAGS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) !drm_mode_match_flags(mode1, mode2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (match_flags & DRM_MODE_MATCH_3D_FLAGS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) !drm_mode_match_3d_flags(mode1, mode2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (match_flags & DRM_MODE_MATCH_ASPECT_RATIO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) !drm_mode_match_aspect_ratio(mode1, mode2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) EXPORT_SYMBOL(drm_mode_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * drm_mode_equal - test modes for equality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * @mode1: first mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * @mode2: second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * Check to see if @mode1 and @mode2 are equivalent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * True if the modes are equal, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) bool drm_mode_equal(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return drm_mode_match(mode1, mode2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) DRM_MODE_MATCH_TIMINGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) DRM_MODE_MATCH_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) DRM_MODE_MATCH_FLAGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DRM_MODE_MATCH_3D_FLAGS|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) DRM_MODE_MATCH_ASPECT_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) EXPORT_SYMBOL(drm_mode_equal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * drm_mode_equal_no_clocks - test modes for equality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * @mode1: first mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * @mode2: second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Check to see if @mode1 and @mode2 are equivalent, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * don't check the pixel clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * True if the modes are equal, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return drm_mode_match(mode1, mode2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) DRM_MODE_MATCH_TIMINGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) DRM_MODE_MATCH_FLAGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) DRM_MODE_MATCH_3D_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) EXPORT_SYMBOL(drm_mode_equal_no_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * drm_mode_equal_no_clocks_no_stereo - test modes for equality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * @mode1: first mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * @mode2: second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * Check to see if @mode1 and @mode2 are equivalent, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * don't check the pixel clocks nor the stereo layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * True if the modes are equal, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const struct drm_display_mode *mode2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return drm_mode_match(mode1, mode2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) DRM_MODE_MATCH_TIMINGS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) DRM_MODE_MATCH_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) EXPORT_SYMBOL(drm_mode_equal_no_clocks_no_stereo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) drm_mode_validate_basic(const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (mode->type & ~DRM_MODE_TYPE_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (mode->flags & ~DRM_MODE_FLAG_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if ((mode->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (mode->clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return MODE_CLOCK_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (mode->hdisplay == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mode->hsync_start < mode->hdisplay ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mode->hsync_end < mode->hsync_start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mode->htotal < mode->hsync_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return MODE_H_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (mode->vdisplay == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mode->vsync_start < mode->vdisplay ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mode->vsync_end < mode->vsync_start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mode->vtotal < mode->vsync_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return MODE_V_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * drm_mode_validate_driver - make sure the mode is somewhat sane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * @dev: drm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * @mode: mode to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * First do basic validation on the mode, and then allow the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * to check for device/driver specific limitations via the optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * &drm_mode_config_helper_funcs.mode_valid hook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * The mode status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) drm_mode_validate_driver(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) enum drm_mode_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) status = drm_mode_validate_basic(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (status != MODE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (dev->mode_config.funcs->mode_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return dev->mode_config.funcs->mode_valid(dev, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) EXPORT_SYMBOL(drm_mode_validate_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * drm_mode_validate_size - make sure modes adhere to size constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * @mode: mode to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * @maxX: maximum width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * @maxY: maximum height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * This function is a helper which can be used to validate modes against size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * limitations of the DRM device/connector. If a mode is too big its status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * member is updated with the appropriate validation failure code. The list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * itself is not changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * The mode status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) drm_mode_validate_size(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int maxX, int maxY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (maxX > 0 && mode->hdisplay > maxX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return MODE_VIRTUAL_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (maxY > 0 && mode->vdisplay > maxY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return MODE_VIRTUAL_Y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) EXPORT_SYMBOL(drm_mode_validate_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * drm_mode_validate_ycbcr420 - add 'ycbcr420-only' modes only when allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * @mode: mode to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * @connector: drm connector under action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * This function is a helper which can be used to filter out any YCBCR420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * only mode, when the source doesn't support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * The mode status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) drm_mode_validate_ycbcr420(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u8 vic = drm_match_cea_mode(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) enum drm_mode_status status = MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (test_bit(vic, hdmi->y420_vdb_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!connector->ycbcr_420_allowed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) status = MODE_NO_420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) EXPORT_SYMBOL(drm_mode_validate_ycbcr420);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define MODE_STATUS(status) [MODE_ ## status + 3] = #status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const char * const drm_mode_status_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) MODE_STATUS(OK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) MODE_STATUS(HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) MODE_STATUS(VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MODE_STATUS(H_ILLEGAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) MODE_STATUS(V_ILLEGAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) MODE_STATUS(BAD_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) MODE_STATUS(NOMODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) MODE_STATUS(NO_INTERLACE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) MODE_STATUS(NO_DBLESCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) MODE_STATUS(NO_VSCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) MODE_STATUS(MEM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) MODE_STATUS(VIRTUAL_X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) MODE_STATUS(VIRTUAL_Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) MODE_STATUS(MEM_VIRT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) MODE_STATUS(NOCLOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) MODE_STATUS(CLOCK_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) MODE_STATUS(CLOCK_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) MODE_STATUS(CLOCK_RANGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) MODE_STATUS(BAD_HVALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) MODE_STATUS(BAD_VVALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) MODE_STATUS(BAD_VSCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) MODE_STATUS(HSYNC_NARROW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) MODE_STATUS(HSYNC_WIDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) MODE_STATUS(HBLANK_NARROW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) MODE_STATUS(HBLANK_WIDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) MODE_STATUS(VSYNC_NARROW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MODE_STATUS(VSYNC_WIDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) MODE_STATUS(VBLANK_NARROW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) MODE_STATUS(VBLANK_WIDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MODE_STATUS(PANEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) MODE_STATUS(INTERLACE_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) MODE_STATUS(ONE_WIDTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) MODE_STATUS(ONE_HEIGHT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) MODE_STATUS(ONE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) MODE_STATUS(NO_REDUCED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODE_STATUS(NO_STEREO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MODE_STATUS(NO_420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) MODE_STATUS(STALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MODE_STATUS(BAD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) MODE_STATUS(ERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #undef MODE_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) const char *drm_get_mode_status_name(enum drm_mode_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int index = status + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (WARN_ON(index < 0 || index >= ARRAY_SIZE(drm_mode_status_names)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return drm_mode_status_names[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * drm_mode_prune_invalid - remove invalid modes from mode list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * @dev: DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * @mode_list: list of modes to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * @verbose: be verbose about it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * This helper function can be used to prune a display mode list after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * validation has been completed. All modes whose status is not MODE_OK will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * removed from the list, and if @verbose the status code and mode name is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * printed to dmesg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) void drm_mode_prune_invalid(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct list_head *mode_list, bool verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct drm_display_mode *mode, *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) list_for_each_entry_safe(mode, t, mode_list, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (mode->status != MODE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) list_del(&mode->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (verbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) drm_mode_debug_printmodeline(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) DRM_DEBUG_KMS("Not using %s mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) mode->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) drm_get_mode_status_name(mode->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) drm_mode_destroy(dev, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) EXPORT_SYMBOL(drm_mode_prune_invalid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * drm_mode_compare - compare modes for favorability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * @priv: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * @lh_a: list_head for first mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * @lh_b: list_head for second mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * Compare two modes, given by @lh_a and @lh_b, returning a value indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * which is better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * positive if @lh_b is better than @lh_a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int drm_mode_compare(void *priv, struct list_head *lh_a, struct list_head *lh_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ((a->type & DRM_MODE_TYPE_PREFERRED) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) diff = b->hdisplay * b->vdisplay - a->hdisplay * a->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) diff = drm_mode_vrefresh(b) - drm_mode_vrefresh(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) diff = b->clock - a->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * drm_mode_sort - sort mode list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * @mode_list: list of drm_display_mode structures to sort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Sort @mode_list by favorability, moving good modes to the head of the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) void drm_mode_sort(struct list_head *mode_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) list_sort(NULL, mode_list, drm_mode_compare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) EXPORT_SYMBOL(drm_mode_sort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * drm_connector_list_update - update the mode list for the connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * @connector: the connector to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * This moves the modes from the @connector probed_modes list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * to the actual mode list. It compares the probed mode against the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * list and only adds different/new modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * This is just a helper functions doesn't validate any modes itself and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * doesn't prune any invalid modes. Callers need to do that themselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) void drm_connector_list_update(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct drm_display_mode *pmode, *pt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) list_for_each_entry_safe(pmode, pt, &connector->probed_modes, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) bool found_it = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* go through current modes checking for the new probed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) list_for_each_entry(mode, &connector->modes, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (!drm_mode_equal(pmode, mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) found_it = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * If the old matching mode is stale (ie. left over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * from a previous probe) just replace it outright.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * Otherwise just merge the type bits between all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * equal probed modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * If two probed modes are considered equal, pick the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * actual timings from the one that's marked as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * preferred (in case the match isn't 100%). If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * multiple or zero preferred modes are present, favor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * the mode added to the probed_modes list first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (mode->status == MODE_STALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) drm_mode_copy(mode, pmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) } else if ((mode->type & DRM_MODE_TYPE_PREFERRED) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) (pmode->type & DRM_MODE_TYPE_PREFERRED) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pmode->type |= mode->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) drm_mode_copy(mode, pmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mode->type |= pmode->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) list_del(&pmode->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) drm_mode_destroy(connector->dev, pmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!found_it) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) list_move_tail(&pmode->head, &connector->modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) EXPORT_SYMBOL(drm_connector_list_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int drm_mode_parse_cmdline_bpp(const char *str, char **end_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) unsigned int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (str[0] != '-')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) str++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) bpp = simple_strtol(str, end_ptr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (*end_ptr == str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) mode->bpp = bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) mode->bpp_specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static int drm_mode_parse_cmdline_refresh(const char *str, char **end_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (str[0] != '@')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) str++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) refresh = simple_strtol(str, end_ptr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (*end_ptr == str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mode->refresh = refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) mode->refresh_specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static int drm_mode_parse_cmdline_extra(const char *str, int length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) bool freestanding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) switch (str[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) case 'i':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (freestanding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mode->interlace = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case 'm':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (freestanding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mode->margins = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case 'D':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (mode->force != DRM_FORCE_UNSPECIFIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) mode->force = DRM_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mode->force = DRM_FORCE_ON_DIGITAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) case 'd':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (mode->force != DRM_FORCE_UNSPECIFIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) mode->force = DRM_FORCE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case 'e':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (mode->force != DRM_FORCE_UNSPECIFIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) mode->force = DRM_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) bool extras,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) const char *str_start = str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) bool rb = false, cvt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int xres = 0, yres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int remaining, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) char *end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) xres = simple_strtol(str, &end_ptr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (end_ptr == str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (end_ptr[0] != 'x')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) end_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) str = end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) yres = simple_strtol(str, &end_ptr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (end_ptr == str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) remaining = length - (end_ptr - str_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (remaining < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) for (i = 0; i < remaining; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) switch (end_ptr[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) case 'M':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) cvt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) case 'R':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) rb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * Try to pass that to our extras parsing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * function to handle the case where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * extras are directly after the resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (extras) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int ret = drm_mode_parse_cmdline_extra(end_ptr + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) mode->xres = xres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) mode->yres = yres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) mode->cvt = cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) mode->rb = rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int drm_mode_parse_cmdline_int(const char *delim, unsigned int *int_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) const char *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) char *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * delim must point to the '=', otherwise it is a syntax error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * if delim points to the terminating zero, then delim + 1 wil point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * past the end of the string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (*delim != '=')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) value = delim + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) *int_ret = simple_strtol(value, &endp, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* Make sure we have parsed something */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (endp == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static int drm_mode_parse_panel_orientation(const char *delim,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) const char *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (*delim != '=')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) value = delim + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) delim = strchr(value, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!delim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) delim = value + strlen(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (!strncmp(value, "normal", delim - value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) else if (!strncmp(value, "upside_down", delim - value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) else if (!strncmp(value, "left_side_up", delim - value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) else if (!strncmp(value, "right_side_up", delim - value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static int drm_mode_parse_cmdline_options(const char *str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) bool freestanding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) unsigned int deg, margin, rotation = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) const char *delim, *option, *sep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) option = str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) delim = strchr(option, '=');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (!delim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) delim = strchr(option, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (!delim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) delim = option + strlen(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (!strncmp(option, "rotate", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (drm_mode_parse_cmdline_int(delim, °))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) switch (deg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) rotation |= DRM_MODE_ROTATE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case 90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) rotation |= DRM_MODE_ROTATE_90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) rotation |= DRM_MODE_ROTATE_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) case 270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) rotation |= DRM_MODE_ROTATE_270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) } else if (!strncmp(option, "reflect_x", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) rotation |= DRM_MODE_REFLECT_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) } else if (!strncmp(option, "reflect_y", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) rotation |= DRM_MODE_REFLECT_Y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) } else if (!strncmp(option, "margin_right", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (drm_mode_parse_cmdline_int(delim, &margin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) mode->tv_margins.right = margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) } else if (!strncmp(option, "margin_left", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (drm_mode_parse_cmdline_int(delim, &margin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) mode->tv_margins.left = margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) } else if (!strncmp(option, "margin_top", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (drm_mode_parse_cmdline_int(delim, &margin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) mode->tv_margins.top = margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) } else if (!strncmp(option, "margin_bottom", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (drm_mode_parse_cmdline_int(delim, &margin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mode->tv_margins.bottom = margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) } else if (!strncmp(option, "panel_orientation", delim - option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (drm_mode_parse_panel_orientation(delim, mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) sep = strchr(delim, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) option = sep + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) } while (sep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (rotation && freestanding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!(rotation & DRM_MODE_ROTATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rotation |= DRM_MODE_ROTATE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Make sure there is exactly one rotation defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (!is_power_of_2(rotation & DRM_MODE_ROTATE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mode->rotation_reflection = rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const char * const drm_named_modes_whitelist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) "NTSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) "PAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * drm_mode_parse_command_line_for_connector - parse command line modeline for connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * @mode_option: optional per connector mode option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * @connector: connector to parse modeline for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * @mode: preallocated drm_cmdline_mode structure to fill out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * This parses @mode_option command line modeline for modes and options to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * configure the connector. If @mode_option is NULL the default command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * modeline in fb_mode_option will be parsed instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * This uses the same parameters as the fb modedb.c, except for an extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * force-enable, force-enable-digital and force-disable bit at the end::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * Additionals options can be provided following the mode, using a comma to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * separate each option. Valid options can be found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * Documentation/fb/modedb.rst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * The intermediate drm_cmdline_mode structure is required to store additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * options from the command line modline like the force-enable/disable flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * True if a valid modeline has been parsed, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) bool drm_mode_parse_command_line_for_connector(const char *mode_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct drm_cmdline_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) bool freestanding = false, parse_extras = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) unsigned int bpp_off = 0, refresh_off = 0, options_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) unsigned int mode_end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) const char *bpp_ptr = NULL, *refresh_ptr = NULL, *extra_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) const char *options_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) char *bpp_end_ptr = NULL, *refresh_end_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int i, len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) memset(mode, 0, sizeof(*mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) mode->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!mode_option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) name = mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* Try to locate the bpp and refresh specifiers, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) bpp_ptr = strchr(name, '-');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (bpp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) bpp_off = bpp_ptr - name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) refresh_ptr = strchr(name, '@');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (refresh_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) refresh_off = refresh_ptr - name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* Locate the start of named options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) options_ptr = strchr(name, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (options_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) options_off = options_ptr - name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /* Locate the end of the name / resolution, and parse it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (bpp_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) mode_end = bpp_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) } else if (refresh_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) mode_end = refresh_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) } else if (options_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) mode_end = options_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) parse_extras = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) mode_end = strlen(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) parse_extras = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* First check for a named mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) for (i = 0; i < ARRAY_SIZE(drm_named_modes_whitelist); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ret = str_has_prefix(name, drm_named_modes_whitelist[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (ret == mode_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (refresh_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return false; /* named + refresh is invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) strcpy(mode->name, drm_named_modes_whitelist[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) mode->specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* No named mode? Check for a normal mode argument, e.g. 1024x768 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (!mode->specified && isdigit(name[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ret = drm_mode_parse_cmdline_res_mode(name, mode_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) parse_extras,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) mode->specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* No mode? Check for freestanding extras and/or options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (!mode->specified) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) unsigned int len = strlen(mode_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (bpp_ptr || refresh_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return false; /* syntax error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (len == 1 || (len >= 2 && mode_option[1] == ','))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) extra_ptr = mode_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) options_ptr = mode_option - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) freestanding = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (bpp_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ret = drm_mode_parse_cmdline_bpp(bpp_ptr, &bpp_end_ptr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) mode->bpp_specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (refresh_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ret = drm_mode_parse_cmdline_refresh(refresh_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) &refresh_end_ptr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mode->refresh_specified = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * Locate the end of the bpp / refresh, and parse the extras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * if relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (bpp_ptr && refresh_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) extra_ptr = max(bpp_end_ptr, refresh_end_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) else if (bpp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) extra_ptr = bpp_end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) else if (refresh_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) extra_ptr = refresh_end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (extra_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (options_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) len = options_ptr - extra_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) len = strlen(extra_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret = drm_mode_parse_cmdline_extra(extra_ptr, len, freestanding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (options_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ret = drm_mode_parse_cmdline_options(options_ptr + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) freestanding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) connector, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) EXPORT_SYMBOL(drm_mode_parse_command_line_for_connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * drm_mode_create_from_cmdline_mode - convert a command line modeline into a DRM display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * @dev: DRM device to create the new mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * @cmd: input command line modeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * Pointer to converted mode on success, NULL on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct drm_display_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) drm_mode_create_from_cmdline_mode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct drm_cmdline_mode *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (cmd->cvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) mode = drm_cvt_mode(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) cmd->xres, cmd->yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) cmd->refresh_specified ? cmd->refresh : 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) cmd->rb, cmd->interlace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) cmd->margins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) mode = drm_gtf_mode(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) cmd->xres, cmd->yres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) cmd->refresh_specified ? cmd->refresh : 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) cmd->interlace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) cmd->margins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) mode->type |= DRM_MODE_TYPE_USERDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* fix up 1368x768: GFT/CVT can't express 1366 width due to alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (cmd->xres == 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) drm_mode_fixup_1366x768(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) EXPORT_SYMBOL(drm_mode_create_from_cmdline_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * drm_crtc_convert_to_umode - convert a drm_display_mode into a modeinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * @out: drm_mode_modeinfo struct to return to the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * @in: drm_display_mode to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * Convert a drm_display_mode into a drm_mode_modeinfo structure to return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) const struct drm_display_mode *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) out->clock = in->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) out->hdisplay = in->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) out->hsync_start = in->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) out->hsync_end = in->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) out->htotal = in->htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) out->hskew = in->hskew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) out->vdisplay = in->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) out->vsync_start = in->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) out->vsync_end = in->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) out->vtotal = in->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) out->vscan = in->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) out->vrefresh = drm_mode_vrefresh(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) out->flags = in->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) out->type = in->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) switch (in->picture_aspect_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) case HDMI_PICTURE_ASPECT_4_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) out->flags |= DRM_MODE_FLAG_PIC_AR_4_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) case HDMI_PICTURE_ASPECT_16_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) out->flags |= DRM_MODE_FLAG_PIC_AR_16_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) case HDMI_PICTURE_ASPECT_64_27:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) out->flags |= DRM_MODE_FLAG_PIC_AR_64_27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case HDMI_PICTURE_ASPECT_256_135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) WARN(1, "Invalid aspect ratio (0%x) on mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) in->picture_aspect_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) case HDMI_PICTURE_ASPECT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) EXPORT_SYMBOL_GPL(drm_mode_convert_to_umode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * drm_crtc_convert_umode - convert a modeinfo into a drm_display_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * @dev: drm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * @out: drm_display_mode to return to the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * @in: drm_mode_modeinfo to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * Zero on success, negative errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) int drm_mode_convert_umode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct drm_display_mode *out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) const struct drm_mode_modeinfo *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (in->clock > INT_MAX || in->vrefresh > INT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) out->clock = in->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) out->hdisplay = in->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) out->hsync_start = in->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) out->hsync_end = in->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) out->htotal = in->htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) out->hskew = in->hskew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) out->vdisplay = in->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) out->vsync_start = in->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) out->vsync_end = in->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) out->vtotal = in->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) out->vscan = in->vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) out->flags = in->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * Old xf86-video-vmware (possibly others too) used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * leave 'type' unititialized. Just ignore any bits we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * don't like. It's a just hint after all, and more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * useful for the kernel->userspace direction anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) out->type = in->type & DRM_MODE_TYPE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* Clearing picture aspect ratio bits from out flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * as the aspect-ratio information is not stored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) * flags for kernel-mode, but in picture_aspect_ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) out->flags &= ~DRM_MODE_FLAG_PIC_AR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) switch (in->flags & DRM_MODE_FLAG_PIC_AR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) case DRM_MODE_FLAG_PIC_AR_4_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) case DRM_MODE_FLAG_PIC_AR_16_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) case DRM_MODE_FLAG_PIC_AR_64_27:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case DRM_MODE_FLAG_PIC_AR_256_135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) case DRM_MODE_FLAG_PIC_AR_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) out->status = drm_mode_validate_driver(dev, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (out->status != MODE_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) drm_mode_set_crtcinfo(out, CRTC_INTERLACE_HALVE_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) EXPORT_SYMBOL_GPL(drm_mode_convert_umode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * drm_mode_is_420_only - if a given videomode can be only supported in YCBCR420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * output format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * @display: display under action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * @mode: video mode to be tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * true if the mode can be supported in YCBCR420 format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) bool drm_mode_is_420_only(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) u8 vic = drm_match_cea_mode(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return test_bit(vic, display->hdmi.y420_vdb_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) EXPORT_SYMBOL(drm_mode_is_420_only);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * output format also (along with RGB/YCBCR444/422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * @display: display under action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * @mode: video mode to be tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * true if the mode can be support YCBCR420 format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) bool drm_mode_is_420_also(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) u8 vic = drm_match_cea_mode(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return test_bit(vic, display->hdmi.y420_cmdb_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) EXPORT_SYMBOL(drm_mode_is_420_also);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) * output format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * @display: display under action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * @mode: video mode to be tested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * true if the mode can be supported in YCBCR420 format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) bool drm_mode_is_420(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return drm_mode_is_420_only(display, mode) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) drm_mode_is_420_also(display, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) EXPORT_SYMBOL(drm_mode_is_420);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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