Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: MIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright © 2018 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Manasi Navare <manasi.d.navare@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/byteorder/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <drm/drm_dsc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * DOC: dsc helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * VESA specification for DP 1.4 adds a new feature called Display Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Compression (DSC) used to compress the pixel bits before sending it on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * display interfaces can support high resolutions at higher frames rates uisng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * the maximum available link capacity of these interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * These functions contain some common logic and helpers to deal with VESA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Display Stream Compression standard required for DSC on Display Port/eDP or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * MIPI display interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * for DisplayPort as per the DP 1.4 spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @pps_header: Secondary data packet header for DSC Picture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *              Parameter Set as defined in &struct dp_sdp_header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * DP 1.4 spec defines the secondary data packet for sending the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * picture parameter infoframes from the source to the sink.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * This function populates the SDP header defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * &struct dp_sdp_header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	memset(pps_header, 0, sizeof(*pps_header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	pps_header->HB1 = DP_SDP_PPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @pps_payload:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * Bitwise struct for DSC Picture Parameter Set. This is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * by &struct drm_dsc_picture_parameter_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @dsc_cfg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * DSC Configuration data filled by driver as defined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * &struct drm_dsc_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * DSC source device sends a picture parameter set (PPS) containing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * information required by the sink to decode the compressed frame. Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * populates the DSC PPS struct using the DSC configuration parameters in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * the order expected by the DSC Display Sink device. For the DSC, the sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * device expects the PPS payload in big endian format for fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * that span more than 1 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				const struct drm_dsc_config *dsc_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Protect against someone accidently changing struct size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	BUILD_BUG_ON(sizeof(*pps_payload) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	memset(pps_payload, 0, sizeof(*pps_payload));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* PPS 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	pps_payload->dsc_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		dsc_cfg->dsc_version_minor |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* PPS 1, 2 is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* PPS 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	pps_payload->pps_3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		dsc_cfg->line_buf_depth |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* PPS 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pps_payload->pps_4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 DSC_PPS_MSB_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* PPS 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	pps_payload->bits_per_pixel_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * The DSC panel expects the PPS packet to have big endian format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * to big endian format. If format is little endian, it will swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * bytes to convert to Big endian else keep it unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* PPS 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* PPS 8, 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* PPS 10, 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* PPS 12, 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* PPS 14, 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* PPS 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pps_payload->initial_xmit_delay_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		((dsc_cfg->initial_xmit_delay &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		 DSC_PPS_MSB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* PPS 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pps_payload->initial_xmit_delay_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* PPS 18, 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pps_payload->initial_dec_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		cpu_to_be16(dsc_cfg->initial_dec_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* PPS 20 is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* PPS 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	pps_payload->initial_scale_value =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		dsc_cfg->initial_scale_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* PPS 22, 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	pps_payload->scale_increment_interval =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		cpu_to_be16(dsc_cfg->scale_increment_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* PPS 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	pps_payload->scale_decrement_interval_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		((dsc_cfg->scale_decrement_interval &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 DSC_PPS_MSB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* PPS 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	pps_payload->scale_decrement_interval_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* PPS 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	pps_payload->first_line_bpg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dsc_cfg->first_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* PPS 28, 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	pps_payload->nfl_bpg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* PPS 30, 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pps_payload->slice_bpg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		cpu_to_be16(dsc_cfg->slice_bpg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* PPS 32, 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	pps_payload->initial_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		cpu_to_be16(dsc_cfg->initial_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* PPS 34, 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* PPS 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* PPS 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* PPS 38, 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	pps_payload->rc_model_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* PPS 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* PPS 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	pps_payload->rc_quant_incr_limit0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dsc_cfg->rc_quant_incr_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* PPS 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	pps_payload->rc_quant_incr_limit1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dsc_cfg->rc_quant_incr_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* PPS 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* PPS 44 - 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		pps_payload->rc_buf_thresh[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			dsc_cfg->rc_buf_thresh[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* PPS 58 - 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * For DSC sink programming the RC Range parameter fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		pps_payload->rc_range_parameters[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				     DSC_PPS_RC_RANGE_MINQP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				    (dsc_cfg->rc_range_params[i].range_max_qp <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				     DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				    (dsc_cfg->rc_range_params[i].range_bpg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* PPS 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	pps_payload->native_422_420 = dsc_cfg->native_422 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* PPS 89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	pps_payload->second_line_bpg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dsc_cfg->second_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* PPS 90, 91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	pps_payload->nsl_bpg_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* PPS 92, 93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	pps_payload->second_line_offset_adj =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		cpu_to_be16(dsc_cfg->second_line_offset_adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* PPS 94 - 127 are O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * drm_dsc_compute_rc_parameters() - Write rate control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * parameters to the dsc configuration defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * &struct drm_dsc_config in accordance with the DSC 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * specification. Some configuration fields must be present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * beforehand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * @vdsc_cfg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * DSC Configuration data partially filled by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	unsigned long groups_per_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	unsigned long groups_total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	unsigned long num_extra_mux_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	unsigned long slice_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned long hrd_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	unsigned long final_scale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	unsigned long rbs_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		/* Number of groups used to code each line of a slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					       DSC_RC_PIXELS_PER_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		/* chunksize in Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 							  vdsc_cfg->bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 							  (8 * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		/* Number of groups used to code each line of a slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 					       DSC_RC_PIXELS_PER_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		/* chunksize in Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 							  vdsc_cfg->bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 							  (8 * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (vdsc_cfg->convert_rgb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 					  (4 * vdsc_cfg->bits_per_component + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					  - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	else if (vdsc_cfg->native_422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			(4 * vdsc_cfg->bits_per_component + 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			3 * (4 * vdsc_cfg->bits_per_component) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			(4 * vdsc_cfg->bits_per_component + 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			2 * (4 * vdsc_cfg->bits_per_component) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Number of bits in one Slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	while ((num_extra_mux_bits > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		num_extra_mux_bits--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		vdsc_cfg->initial_scale_value = groups_per_line + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* scale_decrement_interval calculation according to DSC spec 1.11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (vdsc_cfg->initial_scale_value > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		vdsc_cfg->scale_decrement_interval = groups_per_line /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			(vdsc_cfg->initial_scale_value - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		(vdsc_cfg->initial_xmit_delay *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	final_scale = (vdsc_cfg->rc_model_size * 8) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (vdsc_cfg->slice_height > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		 * NflBpgOffset is 16 bit value with 11 fractional bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		 * hence we multiply by 2^11 for preserving the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		 * fractional part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 							(vdsc_cfg->slice_height - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		vdsc_cfg->nfl_bpg_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* Number of groups used to code the entire slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	groups_total = groups_per_line * vdsc_cfg->slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 						    vdsc_cfg->initial_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 						    num_extra_mux_bits) << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 						  groups_total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (final_scale > 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		 * ScaleIncrementInterval =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		 * we need divide by 2^11 from pstDscCfg values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		vdsc_cfg->scale_increment_interval =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				(vdsc_cfg->final_offset * (1 << 11)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				((vdsc_cfg->nfl_bpg_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				vdsc_cfg->slice_bpg_offset) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				(final_scale - 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		 * If finalScaleValue is less than or equal to 9, a value of 0 should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		 * be used to disable the scale increment at the end of the slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		vdsc_cfg->scale_increment_interval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * DSC spec mentions that bits_per_pixel specifies the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * bits/pixel (bpp) rate that is used by the encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * in steps of 1/16 of a bit per pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			     vdsc_cfg->bits_per_pixel, 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		groups_per_line * vdsc_cfg->first_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);