^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SN_DEVICE_REV_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SN_DPPLL_SRC_REG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPPLL_CLK_SRC_DSICLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REFCLK_FREQ_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REFCLK_FREQ(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SN_PLL_ENABLE_REG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SN_DSI_LANES_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CHA_DSI_LANES_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHA_DSI_LANES(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SN_DSIA_CLK_FREQ_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHA_HSYNC_POLARITY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHA_VSYNC_POLARITY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SN_LN_ASSIGN_REG 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LN_ASSIGN_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SN_ENH_FRAME_REG 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VSTREAM_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LN_POLRS_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LN_POLRS_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SN_DATA_FORMAT_REG 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BPP_18_RGB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SN_HPD_DISABLE_REG 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HPD_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SN_GPIO_IO_REG 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SN_GPIO_INPUT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SN_GPIO_OUTPUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SN_GPIO_CTRL_REG 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SN_GPIO_MUX_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SN_GPIO_MUX_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SN_GPIO_MUX_SPECIAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SN_GPIO_MUX_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SN_AUX_WDATA_REG(x) (0x64 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SN_AUX_ADDR_19_16_REG 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SN_AUX_ADDR_15_8_REG 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SN_AUX_ADDR_7_0_REG 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SN_AUX_LENGTH_REG 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SN_AUX_CMD_REG 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUX_CMD_SEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUX_CMD_REQ(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SN_AUX_RDATA_REG(x) (0x79 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SN_SSC_CONFIG_REG 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DP_NUM_LANES_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DP_NUM_LANES(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SN_DATARATE_CONFIG_REG 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DP_DATARATE_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DP_DATARATE(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SN_ML_TX_MODE_REG 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ML_TX_MAIN_LINK_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ML_TX_NORMAL_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SN_AUX_CMD_STATUS_REG 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MIN_DSI_CLK_FREQ_MHZ 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* fudge factor required to account for 8b/10b encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DP_CLK_FUDGE_NUM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DP_CLK_FUDGE_DEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SN_AUX_MAX_PAYLOAD_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SN_REGULATOR_SUPPLY_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SN_MAX_DP_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SN_NUM_GPIOS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SN_GPIO_PHYSICAL_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @dev: Pointer to our device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @regmap: Regmap for accessing i2c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @aux: Our aux channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @bridge: Our bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @connector: Our connector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @debugfs: Used for managing our debugfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @host_node: Remote DSI node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @dsi: Our MIPI DSI source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @refclk: Our reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @panel: Our panel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @enable_gpio: The GPIO we toggle to enable the bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @supplies: Data for bulk enabling/disabling our regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @dp_lanes: Count of dp_lanes we're using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @ln_assign: Value to program to the LN_ASSIGN register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @gchip: If we expose our GPIOs, this is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @gchip_output: A cache of whether we've set GPIOs to output. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * serves double-duty of keeping track of the direction and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * also keeping track of whether we've incremented the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * pm_runtime reference count for this pin, which we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * whenever a pin is configured as an output. This is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * bitmap so we can do atomic ops on it without an extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * lock so concurrent users of our 4 GPIOs don't stomp on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * each other's read-modify-write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ti_sn_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct drm_dp_aux aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct device_node *host_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct gpio_desc *enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 ln_assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 ln_polrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #if defined(CONFIG_OF_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct gpio_chip gchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .range_min = 0, .range_max = 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct regmap_access_table ti_sn_bridge_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .yes_ranges = ti_sn_bridge_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct regmap_config ti_sn_bridge_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .volatile_table = &ti_sn_bridge_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .max_register = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regmap_write(pdata->regmap, reg, val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_write(pdata->regmap, reg + 1, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_ERROR("failed to enable supplies %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) gpiod_set_value(pdata->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) gpiod_set_value(pdata->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DRM_ERROR("failed to disable supplies %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int status_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ti_sn_bridge *pdata = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) seq_puts(s, "STATUS REGISTERS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pm_runtime_get_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* IRQ Status Registers, see Table 31 in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (reg = 0xf0; reg <= 0xf8; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_read(pdata->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pm_runtime_put(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DEFINE_SHOW_ATTRIBUTE(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) debugfs_create_file("status", 0600, pdata->debugfs, pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &status_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) debugfs_remove_recursive(pdata->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pdata->debugfs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Connector funcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct ti_sn_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) connector_to_ti_sn_bridge(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return container_of(connector, struct ti_sn_bridge, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return drm_panel_get_modes(pdata->panel, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* maximum supported resolution is 4K at 60 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (mode->clock > 594000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .get_modes = ti_sn_bridge_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .mode_valid = ti_sn_bridge_connector_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * TODO: Currently if drm_panel is present, then always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * return the status as connected. Need to add support to detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * device state for hot pluggable scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return connector_status_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .detect = ti_sn_bridge_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return container_of(bridge, struct ti_sn_bridge, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char * const ti_sn_bridge_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "vcca", "vcc", "vccio", "vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pdata->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int ti_sn_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct mipi_dsi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .node = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DRM_ERROR("Fix bridge driver to make connector optional!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = drm_connector_init(bridge->dev, &pdata->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &ti_sn_bridge_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DRM_MODE_CONNECTOR_eDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DRM_ERROR("Failed to initialize connector with drm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) drm_connector_helper_add(&pdata->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &ti_sn_bridge_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * TODO: ideally finding host resource and dsi dev registration needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * to be done in bridge probe. But some existing DSI host drivers will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * wait for any of the drm_bridge/drm_panel to get added to the global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * bridge/panel list, before completing their probe. So if we do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * dsi dev registration part in bridge probe, before populating in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * the global bridge list, then it will cause deadlock as dsi host probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * will never complete, neither our bridge probe. So keeping it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * will satisfy most of the existing host drivers. Once the host driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * is fixed we can move the below code to bridge probe safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) host = of_find_mipi_dsi_host_by_node(pdata->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DRM_ERROR("failed to find dsi host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto err_dsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dsi = mipi_dsi_device_register_full(host, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(dsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DRM_ERROR("failed to create dsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = PTR_ERR(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto err_dsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* TODO: setting to 4 MIPI lanes always for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* check if continuous dsi clock is required or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pm_runtime_get_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pm_runtime_put(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!(val & DPPLL_CLK_SRC_DSICLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DRM_ERROR("failed to attach dsi to host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pdata->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mipi_dsi_device_unregister(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err_dsi_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) drm_connector_cleanup(&pdata->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void ti_sn_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) drm_panel_disable(pdata->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* disable video stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* semi auto link training mode OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* disable DP PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) drm_panel_unprepare(pdata->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 bit_rate_khz, clk_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct drm_display_mode *mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &pdata->bridge.encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bit_rate_khz = mode->clock *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return clk_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const u32 ti_sn_bridge_refclk_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 26000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const u32 ti_sn_bridge_dsiclk_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 468000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 384000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 416000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 486000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 460800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 refclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const u32 *refclk_lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) size_t refclk_lut_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (pdata->refclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) refclk_rate = clk_get_rate(pdata->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) refclk_lut = ti_sn_bridge_refclk_lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk_prepare_enable(pdata->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) refclk_lut = ti_sn_bridge_dsiclk_lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* for i equals to refclk_lut_size means default frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < refclk_lut_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (refclk_lut[i] == refclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) REFCLK_FREQ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int bit_rate_mhz, clk_freq_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct drm_display_mode *mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &pdata->bridge.encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* set DSIA clk frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bit_rate_mhz = (mode->clock / 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* for each increment in val, frequency increases by 5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (pdata->connector.display_info.bpc <= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * LUT index corresponds to register value and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * LUT values corresponds to dp data rate supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * by the bridge in Mbps unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int bit_rate_khz, dp_rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct drm_display_mode *mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &pdata->bridge.encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Calculate minimum bit rate based on our pixel clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Calculate minimum DP data rate, taking 80% as per DP spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) bool rate_valid[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int rate_per_200khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 dpcd_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "Can't read eDP rev (%d), assuming 1.1\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dpcd_val = DP_EDP_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (dpcd_val >= DP_EDP_14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* eDP 1.4 devices must provide a custom table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sink_rates, sizeof(sink_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret != sizeof(sink_rates)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "Can't read supported rate table (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) memset(sink_rates, 0, sizeof(sink_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rate_per_200khz = le16_to_cpu(sink_rates[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!rate_per_200khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rate_mhz = rate_per_200khz * 200 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rate_valid[j] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (rate_valid[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "No matching eDP rates in table; falling back\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* On older versions best we can do is use DP_MAX_LINK_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "Can't read max rate (%d); assuming 5.4 GHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dpcd_val = DP_LINK_BW_5_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) switch (dpcd_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "Unexpected max rate (%#x); assuming 5.4 GHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (int)dpcd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case DP_LINK_BW_5_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rate_valid[7] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case DP_LINK_BW_2_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rate_valid[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case DP_LINK_BW_1_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rate_valid[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct drm_display_mode *mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &pdata->bridge.encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 hsync_polarity = 0, vsync_polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (mode->flags & DRM_MODE_FLAG_PHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hsync_polarity = CHA_HSYNC_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (mode->flags & DRM_MODE_FLAG_PVSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) vsync_polarity = CHA_VSYNC_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (mode->hsync_end - mode->hsync_start) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hsync_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) (mode->vsync_end - mode->vsync_start) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vsync_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (mode->htotal - mode->hsync_end) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) (mode->vtotal - mode->vsync_end) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (mode->hsync_start - mode->hdisplay) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (mode->vsync_start - mode->vdisplay) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) usleep_range(10000, 10500); /* 10ms delay recommended by spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DRM_DEV_ERROR(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "Can't read lane count (%d); assuming 4\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return data & DP_LANE_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const char **last_err_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* set dp clk frequency value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* enable DP PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val & DPPLL_SRC_DP_PLL_LOCK, 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 50 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *last_err_str = "DP_PLL_LOCK polling failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Semi auto link training mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val == ML_TX_MAIN_LINK_OFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) val == ML_TX_NORMAL_MODE, 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *last_err_str = "Training complete polling failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } else if (val == ML_TX_MAIN_LINK_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *last_err_str = "Link training failed, link is off";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Disable the PLL if we failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static void ti_sn_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const char *last_err_str = "No supported DP rate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int dp_rate_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int max_dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) max_dp_lanes = ti_sn_get_max_lanes(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* DSI_A lane config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) CHA_DSI_LANES_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pdata->ln_polrs << LN_POLRS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* set dsi clk frequency value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ti_sn_bridge_set_dsi_rate(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * The SN65DSI86 only supports ASSR Display Authentication method and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * this method is enabled by default. An eDP panel must support this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * authentication method. We need to enable this method in the eDP panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * at DisplayPort address 0x0010A prior to link training.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Set the DP output format (18 bpp or 24 bpp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* DP lane config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ti_sn_bridge_read_valid_rates(pdata, rate_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Train until we run out of rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dp_rate_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!rate_valid[dp_rate_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* config video parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ti_sn_bridge_set_video_timings(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* enable video stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) VSTREAM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) drm_panel_enable(pdata->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pm_runtime_get_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* configure bridge ref_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ti_sn_bridge_set_refclk_freq(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * HPD on this bridge chip is a bit useless. This is an eDP bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * so the HPD is an internal signal that's only there to signal that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * the panel is done powering up. ...but the bridge chip debounces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * this signal by between 100 ms and 400 ms (depending on process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * voltage, and temperate--I measured it at about 200 ms). One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * particular panel asserted HPD 84 ms after it was powered on meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * that we saw HPD 284 ms after power on. ...but the same panel said
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * that instead of looking at HPD you could just hardcode a delay of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * 200 ms. We'll assume that the panel driver will have the hardcoded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * delay in its prepare and always disable HPD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * If HPD somehow makes sense on some future panel we'll have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * change this to be conditional on someone specifying that HPD should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) HPD_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) drm_panel_prepare(pdata->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (pdata->refclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk_disable_unprepare(pdata->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pm_runtime_put_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .attach = ti_sn_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .pre_enable = ti_sn_bridge_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .enable = ti_sn_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .disable = ti_sn_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .post_disable = ti_sn_bridge_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return container_of(aux, struct ti_sn_bridge, aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct drm_dp_aux_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 request = msg->request & ~DP_AUX_I2C_MOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 request_val = AUX_CMD_REQ(msg->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u8 *buf = (u8 *)msg->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) switch (request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case DP_AUX_NATIVE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case DP_AUX_I2C_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case DP_AUX_NATIVE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case DP_AUX_I2C_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (msg->address >> 16) & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (msg->address >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) for (i = 0; i < msg->size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Clear old status bits before start so we don't get confused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) AUX_IRQ_STATUS_NAT_I2C_FAIL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) AUX_IRQ_STATUS_AUX_RPLY_TOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) AUX_IRQ_STATUS_AUX_SHORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) !(val & AUX_CMD_SEND), 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 50 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) || (val & AUX_IRQ_STATUS_AUX_SHORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return msg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) for (i = 0; i < msg->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) WARN_ON(val & ~0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) buf[i] = (u8)(val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return msg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct device_node *np = pdata->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pdata->host_node = of_graph_get_remote_node(np, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!pdata->host_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DRM_ERROR("remote dsi host node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #if defined(CONFIG_OF_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) const struct of_phandle_args *gpiospec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) *flags = gpiospec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * We already have to keep track of the direction because we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * that to figure out whether we've powered the device. We can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * just return that rather than (maybe) powering up the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * to ask its direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return test_bit(offset, pdata->gchip_output) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * When the pin is an input we don't forcibly keep the bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * powered--we just power it on to read the pin. NOTE: part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * the reason this works is that the bridge defaults (when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * powered back on) to all 4 GPIOs being configured as GPIO input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * Also note that if something else is keeping the chip powered the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * pm_runtime functions are lightweight increments of a refcount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) pm_runtime_get_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) pm_runtime_put(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!test_bit(offset, pdata->gchip_output)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(pdata->dev, "Ignoring GPIO set while input\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) val &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) BIT(SN_GPIO_OUTPUT_SHIFT + offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val << (SN_GPIO_OUTPUT_SHIFT + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_warn(pdata->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "Failed to set bridge GPIO %u: %d\n", offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int shift = offset * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!test_and_clear_bit(offset, pdata->gchip_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SN_GPIO_MUX_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SN_GPIO_MUX_INPUT << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) set_bit(offset, pdata->gchip_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * NOTE: if nobody else is powering the device this may fully power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * it off and when it comes back it will have lost all state, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * that's OK because the default is input and we're now an input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pm_runtime_put(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int shift = offset * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (test_and_set_bit(offset, pdata->gchip_output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pm_runtime_get_sync(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Set value first to avoid glitching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ti_sn_bridge_gpio_set(chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* Set direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SN_GPIO_MUX_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) SN_GPIO_MUX_OUTPUT << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clear_bit(offset, pdata->gchip_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pm_runtime_put(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* We won't keep pm_runtime if we're input, so switch there on free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ti_sn_bridge_gpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "GPIO1", "GPIO2", "GPIO3", "GPIO4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Only init if someone is going to use us as a GPIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pdata->gchip.label = dev_name(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pdata->gchip.parent = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pdata->gchip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pdata->gchip.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pdata->gchip.free = ti_sn_bridge_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) pdata->gchip.get = ti_sn_bridge_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pdata->gchip.set = ti_sn_bridge_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pdata->gchip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pdata->gchip.names = ti_sn_bridge_gpio_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pdata->gchip.ngpio = SN_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pdata->gchip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_err(pdata->dev, "can't add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u32 lane_polarities[SN_MAX_DP_LANES] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u8 ln_assign = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u8 ln_polrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * Read config from the device tree about lane remapping and lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * polarities. These are optional and we assume identity map and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * normal polarity if nothing is specified. It's OK to specify just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * data-lanes but not lane-polarities but not vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * Error checking is light (we just make sure we don't crash or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * buffer overrun) and we assume dts is well formed and specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * mappings that the hardware supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) of_property_read_u32_array(endpoint, "data-lanes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) lane_assignments, dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) of_property_read_u32_array(endpoint, "lane-polarities",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) lane_polarities, dp_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dp_lanes = SN_MAX_DP_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Convert into register format. Loop over all lanes even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * data-lanes had fewer elements so that we nicely initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * the LN_ASSIGN register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ln_polrs = ln_polrs << 1 | lane_polarities[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* Stash in our struct for when we power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pdata->dp_lanes = dp_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pdata->ln_assign = ln_assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pdata->ln_polrs = ln_polrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int ti_sn_bridge_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct ti_sn_bridge *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) DRM_ERROR("device doesn't support I2C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) pdata->regmap = devm_regmap_init_i2c(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) &ti_sn_bridge_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (IS_ERR(pdata->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) DRM_ERROR("regmap i2c init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return PTR_ERR(pdata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pdata->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) &pdata->panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) DRM_ERROR("could not find any panel node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_set_drvdata(&client->dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (IS_ERR(pdata->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) DRM_ERROR("failed to get enable gpio from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = PTR_ERR(pdata->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ti_sn_bridge_parse_lanes(pdata, client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = ti_sn_bridge_parse_regulators(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) DRM_ERROR("failed to parse regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pdata->refclk = devm_clk_get(pdata->dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (IS_ERR(pdata->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = PTR_ERR(pdata->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) DRM_DEBUG_KMS("refclk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) pdata->refclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = ti_sn_bridge_parse_dsi_host(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pm_runtime_enable(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = ti_sn_setup_gpio_controller(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pm_runtime_disable(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2c_set_clientdata(client, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pdata->aux.name = "ti-sn65dsi86-aux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pdata->aux.dev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pdata->aux.transfer = ti_sn_aux_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) drm_dp_aux_register(&pdata->aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pdata->bridge.funcs = &ti_sn_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pdata->bridge.of_node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) drm_bridge_add(&pdata->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ti_sn_debugfs_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int ti_sn_bridge_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ti_sn_debugfs_remove(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) of_node_put(pdata->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm_runtime_disable(pdata->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (pdata->dsi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mipi_dsi_detach(pdata->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mipi_dsi_device_unregister(pdata->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) drm_bridge_remove(&pdata->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static struct i2c_device_id ti_sn_bridge_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { "ti,sn65dsi86", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const struct of_device_id ti_sn_bridge_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {.compatible = "ti,sn65dsi86"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static struct i2c_driver ti_sn_bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .name = "ti_sn65dsi86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .of_match_table = ti_sn_bridge_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .pm = &ti_sn_bridge_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .probe = ti_sn_bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .remove = ti_sn_bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .id_table = ti_sn_bridge_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) module_i2c_driver(ti_sn_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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