^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TC358775 DSI to LVDS bridge driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 SMART Wireless Computing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Vinay Simha BN <simhavcs@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* #define DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_crtc_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DSI D-PHY Layer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLW_CNTRL 0x0040 /* Clock Lane Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define D2W_CNTRL 0x004C /* Data Lane 2 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* DSI PPI Layer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PPI_START_FUNCTION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PPI_BUSYPPI 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PPI_LPTXTIMECNT 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Analog timer function enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DSI_RX_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DSI_BUSYDSI 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DSI_INTSTATUS 0x0220 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DSI_INTMASK 0x0224 /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DSI_INTCLR 0x0228 /* Interrupt Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DSIERRCNT 0x0300 /* DSI Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define APLCTRL 0x0400 /* Application Layer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RDPKTLN 0x0404 /* Command Read Packet Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VPCTRL 0x0450 /* Video Path Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HTIM1 0x0454 /* Horizontal Timing Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HTIM2 0x0458 /* Horizontal Timing Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VTIM1 0x045C /* Vertical Timing Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VTIM2 0x0460 /* Vertical Timing Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VFUEN 0x0464 /* Video Frame Timing Update Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VFUEN_EN BIT(0) /* Upload Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Mux Input Select for LVDS LINK Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LV_MX0003 0x0480 /* Bit 0 to 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LV_MX0407 0x0484 /* Bit 4 to 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LV_MX0811 0x0488 /* Bit 8 to 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LV_MX1215 0x048C /* Bit 12 to 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LV_MX1619 0x0490 /* Bit 16 to 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LV_MX2023 0x0494 /* Bit 20 to 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LV_MX2427 0x0498 /* Bit 24 to 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Input bit numbers used in mux registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) LVI_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LVI_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) LVI_R2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) LVI_R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) LVI_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) LVI_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) LVI_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) LVI_R7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) LVI_G0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) LVI_G1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) LVI_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) LVI_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) LVI_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LVI_G5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) LVI_G6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) LVI_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) LVI_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) LVI_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LVI_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) LVI_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LVI_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) LVI_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) LVI_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) LVI_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) LVI_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) LVI_VS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LVI_DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) LVI_L0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LVCFG 0x049C /* LVDS Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LVPHY0 0x04A0 /* LVDS PHY 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LVPHY1 0x04A4 /* LVDS PHY 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SYSSTAT 0x0500 /* System Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SYSRST 0x0504 /* System Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SYS_RST_REG BIT(5) /* Reset Register module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* GPIO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPIOC 0x0520 /* GPIO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GPIOO 0x0524 /* GPIO Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GPIOI 0x0528 /* GPIO Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* I2C Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define I2CMADDR 0x0544 /* I2C Master Addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WDATAQ 0x0548 /* Write Data Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RDATAQ 0x054C /* Read Data Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Chip ID and Revision ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IDREG 0x0580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LPX_PERIOD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TTA_GET 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TTA_SURE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SINGLE_LINK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DUAL_LINK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TC358775XBG_ID 0x00007500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Debug Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DEBUG00 0x05A0 /* Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DEBUG01 0x05A4 /* LVDS Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DSI_CLEN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LVCFG_LVEN_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define L0EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TC358775_VPCTRL_VSDELAY__SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) TC358775_VPCTRL_VSDELAY__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TC358775_VPCTRL_OPXLFMT__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TC358775_VPCTRL_OPXLFMT__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TC358775_VPCTRL_MSF__MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TC358775_VPCTRL_MSF__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) TC358775_VPCTRL_MSF__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TC358775_LVCFG_PCLKDIV__SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TC358775_LVCFG_PCLKDIV__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TC358775_LVCFG_LVDLINK__MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TC358775_LVCFG_LVDLINK__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) TC358775_LVCFG_LVDLINK__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum tc358775_ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) TC358775_DSI_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TC358775_LVDS_OUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) TC358775_LVDS_OUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device_node *host_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 num_dsi_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct regulator *vddio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct gpio_desc *stby_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 lvds_link; /* single-link or dual-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 bpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return container_of(b, struct tc_data, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void tc_bridge_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct tc_data *tc = bridge_to_tc(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct device *dev = &tc->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = regulator_enable(tc->vddio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(dev, "regulator vddio enable failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = regulator_enable(tc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "regulator vdd enable failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) gpiod_set_value(tc->stby_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gpiod_set_value(tc->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void tc_bridge_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct tc_data *tc = bridge_to_tc(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct device *dev = &tc->dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpiod_set_value(tc->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) gpiod_set_value(tc->stby_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = regulator_disable(tc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(dev, "regulator vdd disable failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regulator_disable(tc->vddio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(dev, "regulator vddio disable failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 buf_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) put_unaligned_be16(addr, buf_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) put_unaligned_be16(addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) put_unaligned_le32(val, data + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* helper function to access bus_formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct drm_connector *get_connector(struct drm_encoder *encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct drm_device *dev = encoder->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct drm_connector *connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) list_for_each_entry(connector, &dev->mode_config.connector_list, head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (connector->encoder == encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void tc_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tc_data *tc = bridge_to_tc(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct drm_connector *connector = get_connector(bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mode = &bridge->encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hback_porch = mode->htotal - mode->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hsync_len = mode->hsync_end - mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) vback_porch = mode->vtotal - mode->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) vsync_len = mode->vsync_end - mode->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) htime1 = (hback_porch << 16) + hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) vtime1 = (vback_porch << 16) + vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hfront_porch = mode->hsync_start - mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hactive = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) vfront_porch = mode->vsync_start - mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) vactive = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) htime2 = (hfront_porch << 16) + hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) vtime2 = (vfront_porch << 16) + vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) d2l_read(tc->i2c, IDREG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (val >> 8) & 0xFF, val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) usleep_range(30000, 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) d2l_write(tc->i2c, PPI_LANEENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) d2l_write(tc->i2c, DSI_LANEENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (tc->bpc == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val = TC358775_VPCTRL_OPXLFMT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else /* bpc = 6; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val = TC358775_VPCTRL_MSF(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) byteclk = dsiclk / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tc->num_dsi_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) val |= TC358775_VPCTRL_VSDELAY(vsdelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) d2l_write(tc->i2c, VPCTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) d2l_write(tc->i2c, HTIM1, htime1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) d2l_write(tc->i2c, VTIM1, vtime1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) d2l_write(tc->i2c, HTIM2, htime2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) d2l_write(tc->i2c, VTIM2, vtime2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) d2l_write(tc->i2c, VFUEN, VFUEN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) connector->display_info.bus_formats[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tc->bpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Default hardware register settings of tc358775 configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (connector->display_info.bus_formats[0] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* VESA-24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) d2l_write(tc->i2c, VFUEN, VFUEN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val = LVCFG_LVEN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (tc->lvds_link == DUAL_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) val |= TC358775_LVCFG_LVDLINK(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) d2l_write(tc->i2c, LVCFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tc_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct tc_data *tc = bridge_to_tc(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Maximum pixel clock speed 135MHz for single-link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * 270MHz for dual-link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) switch (info->bus_formats[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* RGB888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) tc->bpc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* RGB666 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tc->bpc = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_warn(tc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "unsupported LVDS bus format 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) info->bus_formats[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return MODE_NOMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct device_node *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * To get the data-lanes of dsi, we need to access the dsi0_out of port1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * of dsi0 endpoint from bridge port0 of d2l_in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) TC358775_DSI_IN, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* dsi0_out node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) parent = of_graph_get_remote_port_parent(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* dsi0 port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) endpoint = of_graph_get_endpoint_by_regs(parent, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) prop = of_find_property(endpoint, "data-lanes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_err(tc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "failed to find data lane\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tc->num_dsi_lanes = len / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (tc->num_dsi_lanes < 1 || tc->num_dsi_lanes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tc->host_node = of_graph_get_remote_node(np, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!tc->host_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) of_node_put(tc->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tc->lvds_link = SINGLE_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TC358775_LVDS_OUT1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) remote = of_graph_get_remote_port_parent(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (of_device_is_available(remote))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tc->lvds_link = DUAL_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) of_node_put(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int tc_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct tc_data *tc = bridge_to_tc(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct device *dev = &tc->i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct mipi_dsi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) const struct mipi_dsi_device_info info = { .type = "tc358775",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .node = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) host = of_find_mipi_dsi_host_by_node(tc->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(dev, "failed to find dsi host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dsi = mipi_dsi_device_register_full(host, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (IS_ERR(dsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_err(dev, "failed to create dsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = PTR_ERR(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto err_dsi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) tc->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dsi->lanes = tc->num_dsi_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(dev, "failed to attach dsi to host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Attach the panel-bridge to the dsi bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &tc->bridge, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mipi_dsi_device_unregister(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) err_dsi_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct drm_bridge_funcs tc_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .attach = tc_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .pre_enable = tc_bridge_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .enable = tc_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .mode_valid = tc_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .post_disable = tc_bridge_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct tc_data *tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) tc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tc->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = drm_of_find_panel_or_bridge(dev->of_node, TC358775_LVDS_OUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 0, &panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tc->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (IS_ERR(tc->panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return PTR_ERR(tc->panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = tc358775_parse_dt(dev->of_node, tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) tc->vddio = devm_regulator_get(dev, "vddio-supply");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (IS_ERR(tc->vddio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = PTR_ERR(tc->vddio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(dev, "vddio-supply not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) tc->vdd = devm_regulator_get(dev, "vdd-supply");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (IS_ERR(tc->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = PTR_ERR(tc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(dev, "vdd-supply not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (IS_ERR(tc->stby_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = PTR_ERR(tc->stby_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(dev, "cannot get stby-gpio %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (IS_ERR(tc->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = PTR_ERR(tc->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(dev, "cannot get reset-gpios %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tc->bridge.funcs = &tc_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tc->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) drm_bridge_add(&tc->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i2c_set_clientdata(client, tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int tc_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct tc_data *tc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) drm_bridge_remove(&tc->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct i2c_device_id tc358775_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { "tc358775", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const struct of_device_id tc358775_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { .compatible = "toshiba,tc358775", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_DEVICE_TABLE(of, tc358775_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct i2c_driver tc358775_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .name = "tc358775",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .of_match_table = tc358775_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .id_table = tc358775_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .probe = tc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .remove = tc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) module_i2c_driver(tc358775_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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