^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_crtc_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <video/videomode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Global (16-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TC358768_CHIPID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TC358768_SYSCTL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TC358768_CONFCTL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TC358768_VSDLY 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TC358768_DATAFMT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TC358768_GPIOEN 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TC358768_GPIODIR 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TC358768_GPIOIN 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TC358768_GPIOOUT 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TC358768_PLLCTL0 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TC358768_PLLCTL1 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TC358768_CMDBYTE 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TC358768_PP_MISC 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TC358768_DSITX_DT 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TC358768_FIFOSTATUS 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Debug (16-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TC358768_VBUFCTRL 0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TC358768_DBG_WIDTH 0x00E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TC358768_DBG_VBLANK 0x00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TC358768_DBG_DATA 0x00E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* TX PHY (32-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TC358768_CLW_DPHYCONTTX 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TC358768_D0W_DPHYCONTTX 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TC358768_D1W_DPHYCONTTX 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TC358768_D2W_DPHYCONTTX 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TC358768_D3W_DPHYCONTTX 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TC358768_CLW_CNTRL 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TC358768_D0W_CNTRL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TC358768_D1W_CNTRL 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TC358768_D2W_CNTRL 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TC358768_D3W_CNTRL 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* TX PPI (32-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TC358768_STARTCNTRL 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TC358768_DSITXSTATUS 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TC358768_LINEINITCNT 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TC358768_LPTXTIMECNT 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TC358768_TCLK_HEADERCNT 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TC358768_TCLK_TRAILCNT 0x021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TC358768_THS_HEADERCNT 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TC358768_TWAKEUP 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TC358768_TCLK_POSTCNT 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TC358768_THS_TRAILCNT 0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TC358768_HSTXVREGCNT 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TC358768_HSTXVREGEN 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TC358768_TXOPTIONCNTRL 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TC358768_BTACNTRL1 0x023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* TX CTRL (32-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TC358768_DSI_CONTROL 0x040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TC358768_DSI_STATUS 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TC358768_DSI_INT 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TC358768_DSI_INT_ENA 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TC358768_DSICMD_RDFIFO 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TC358768_DSI_ACKERR 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TC358768_DSI_ACKERR_INTENA 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TC358768_DSI_ACKERR_HALT 0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TC358768_DSI_RXERR 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TC358768_DSI_RXERR_INTENA 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TC358768_DSI_RXERR_HALT 0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TC358768_DSI_ERR 0x044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TC358768_DSI_ERR_INTENA 0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TC358768_DSI_ERR_HALT 0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TC358768_DSI_CONFW 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TC358768_DSI_LPCMD 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TC358768_DSI_RESET 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TC358768_DSI_INT_CLR 0x050C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TC358768_DSI_START 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* DSITX CTRL (16-bit addressable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TC358768_DSICMD_TX 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TC358768_DSICMD_TYPE 0x0602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TC358768_DSICMD_WC 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TC358768_DSICMD_WD0 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TC358768_DSICMD_WD1 0x0612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TC358768_DSICMD_WD2 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TC358768_DSICMD_WD3 0x0616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TC358768_DSI_EVENT 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TC358768_DSI_VSW 0x0622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TC358768_DSI_VBPR 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TC358768_DSI_VACT 0x0626
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TC358768_DSI_HSW 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TC358768_DSI_HBPR 0x062A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TC358768_DSI_HACT 0x062C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* TC358768_DSI_CONTROL (0x040C) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TC358768_DSI_CONTROL_TXMD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TC358768_DSI_CONTROL_HSCKMD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TC358768_DSI_CONTROL_EOTDIS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* TC358768_DSI_CONFW (0x0500) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TC358768_DSI_CONFW_MODE_SET (5 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char * const tc358768_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "vddc", "vddmipi", "vddio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct tc358768_dsi_output {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mipi_dsi_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct drm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tc358768_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mipi_dsi_host dsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct tc358768_dsi_output output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 pd_lines; /* number of Parallel Port Input Data Lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 dsi_lanes; /* number of DSI Lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Parameters for PLL programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 fbd; /* PLL feedback divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 prd; /* PLL input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 frs; /* PLL Freqency range for HSCK (post divider) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 dsiclk; /* pll_clk / 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return container_of(host, struct tc358768_priv, dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return container_of(bridge, struct tc358768_priv, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int tc358768_clear_error(struct tc358768_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret = priv->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int tmpval = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) size_t count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (priv->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* 16-bit register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (reg < 0x100 || reg >= 0x600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) size_t count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (priv->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* 16-bit register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (reg < 0x100 || reg >= 0x600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 tmp, orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tc358768_read(priv, reg, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp = orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (tmp != orig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tc358768_write(priv, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int tc358768_sw_reset(struct tc358768_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Assert Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tc358768_write(priv, TC358768_SYSCTL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Release Reset, Exit Sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tc358768_write(priv, TC358768_SYSCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void tc358768_hw_enable(struct tc358768_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (priv->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (priv->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * The RESX is active low (GPIO_ACTIVE_LOW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * DEASSERT (value = 0) the reset_gpio to enable the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) gpiod_set_value_cansleep(priv->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* wait for encoder clocks to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) priv->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void tc358768_hw_disable(struct tc358768_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!priv->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * The RESX is active low (GPIO_ACTIVE_LOW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * ASSERT (value = 1) the reset_gpio to disable the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gpiod_set_value_cansleep(priv->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) priv->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int tc358768_calc_pll(struct tc358768_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bool verify_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const u32 frs_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 250000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 62500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 prd, target_pll, i, max_pll, min_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 frs, best_diff, best_pll, best_prd, best_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (target_pll >= frs_limits[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (i == ARRAY_SIZE(frs_limits) || i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) frs = i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) max_pll = frs_limits[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) min_pll = frs_limits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) refclk = clk_get_rate(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) best_diff = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) best_pll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) best_prd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) best_fbd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (prd = 0; prd < 16; ++prd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 divisor = (prd + 1) * (1 << frs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (fbd = 0; fbd < 512; ++fbd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 pll, diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (pll >= max_pll || pll < min_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) diff = max(pll, target_pll) - min(pll, target_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) best_pll = pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) best_prd = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) best_fbd = fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (best_diff == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (best_diff == UINT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(priv->dev, "could not find suitable PLL setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (verify_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->fbd = best_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->prd = best_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->frs = frs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) priv->dsiclk = best_pll / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct mipi_dsi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct tc358768_priv *priv = dsi_host_to_tc358768(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct drm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct device_node *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (dev->lanes > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * tc358768 supports both Video and Pulse mode, but the driver only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * implements Video (event) mode currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * RGB888 is verified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (dev->format != MIPI_DSI_FMT_RGB888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (panel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) bridge = drm_panel_bridge_add_typed(panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (IS_ERR(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PTR_ERR(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) priv->output.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) priv->output.bridge = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) priv->output.panel = panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) priv->dsi_lanes = dev->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* get input ep (port0/endpoint0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_node_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) drm_bridge_add(&priv->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct mipi_dsi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct tc358768_priv *priv = dsi_host_to_tc358768(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) drm_bridge_remove(&priv->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (priv->output.panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) drm_panel_bridge_remove(priv->output.bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const struct mipi_dsi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct tc358768_priv *priv = dsi_host_to_tc358768(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct mipi_dsi_packet packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(priv->dev, "Bridge is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (msg->rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_warn(priv->dev, "MIPI rx is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (msg->tx_len > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = mipi_dsi_create_packet(&packet, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (mipi_dsi_packet_format_is_short(msg->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tc358768_write(priv, TC358768_DSICMD_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (0x10 << 8) | (packet.header[0] & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tc358768_write(priv, TC358768_DSICMD_WC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tc358768_write(priv, TC358768_DSICMD_WD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (packet.header[2] << 8) | packet.header[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tc358768_write(priv, TC358768_DSICMD_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) (0x40 << 8) | (packet.header[0] & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) for (i = 0; i < packet.payload_length; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u16 val = packet.payload[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (i + 1 < packet.payload_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val |= packet.payload[i + 1] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) tc358768_write(priv, TC358768_DSICMD_TX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_warn(priv->dev, "Software disable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = packet.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .attach = tc358768_dsi_host_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .detach = tc358768_dsi_host_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .transfer = tc358768_dsi_host_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int tc358768_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(priv->dev, "needs atomic updates support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tc358768_bridge_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (tc358768_calc_pll(priv, mode, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return MODE_CLOCK_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void tc358768_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* set FrmStop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* wait at least for one frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* clear PP_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* set RstPtr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_warn(priv->dev, "Software disable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tc358768_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int tc358768_setup_pll(struct tc358768_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 fbd, prd, frs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = tc358768_calc_pll(priv, mode, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fbd = priv->fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) prd = priv->prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) frs = priv->frs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) clk_get_rate(priv->refclk), fbd, prd, frs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mode->clock * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* PRD[15:12] FBD[8:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) tc358768_write(priv, TC358768_PLLCTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* wait for lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tc358768_write(priv, TC358768_PLLCTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define TC358768_PRECISION 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static u32 tc358768_to_ns(u32 nsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return (nsk / TC358768_PRECISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct mipi_dsi_device *dsi_dev = priv->output.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 val, val2, lptxcnt, hact, data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 dsiclk, dsibclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tc358768_hw_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = tc358768_sw_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(priv->dev, "Software reset failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tc358768_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mode = &bridge->encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = tc358768_setup_pll(priv, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(priv->dev, "PLL setup failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tc358768_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dsiclk = priv->dsiclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dsibclk = dsiclk / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Data Format Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) switch (dsi_dev->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val |= (0x3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hact = mode->hdisplay * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val |= (0x4 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) hact = mode->hdisplay * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case MIPI_DSI_FMT_RGB666_PACKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) val |= (0x4 << 4) | BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hact = mode->hdisplay * 18 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val |= (0x5 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) hact = mode->hdisplay * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_err(priv->dev, "Invalid data format (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dsi_dev->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tc358768_hw_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* VSDly[9:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tc358768_write(priv, TC358768_VSDLY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) tc358768_write(priv, TC358768_DATAFMT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tc358768_write(priv, TC358768_DSITX_DT, data_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Enable D-PHY (HiZ->LP11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Enable lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) for (i = 0; i < dsi_dev->lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* DSI Timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dsibclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ui_nsk = dsiclk_nsk / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* LP11 > 100us for D-PHY Rx Init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tc358768_write(priv, TC358768_LINEINITCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* LPTimeCnt > 50ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) lptxcnt = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tc358768_write(priv, TC358768_LPTXTIMECNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* 38ns < TCLK_PREPARE < 95ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* TCLK_PREPARE > 300ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dsibclk_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* TCLK_TRAIL > 60ns + 3*UI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) val = 60 + tc358768_to_ns(3 * ui_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val = 50 + tc358768_to_ns(4 * ui_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* THS_ZERO > 145ns + 10*UI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tc358768_write(priv, TC358768_THS_HEADERCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* TWAKEUP > 1ms in lptxcnt steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val = val / (lptxcnt + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) tc358768_write(priv, TC358768_TWAKEUP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* TCLK_POSTCNT > 60ns + 52*UI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dsibclk_nsk) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dsibclk_nsk) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tc358768_write(priv, TC358768_THS_TRAILCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val = BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) for (i = 0; i < dsi_dev->lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) val |= BIT(i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tc358768_write(priv, TC358768_HSTXVREGEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dsibclk_nsk) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) val |= val2 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tc358768_write(priv, TC358768_BTACNTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* START[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) tc358768_write(priv, TC358768_STARTCNTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Set event mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) tc358768_write(priv, TC358768_DSI_EVENT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* vsw (+ vbp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) tc358768_write(priv, TC358768_DSI_VSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mode->vtotal - mode->vsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* vbp (not used in event mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) tc358768_write(priv, TC358768_DSI_VBPR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* vact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* (hsw + hbp) * byteclk * ndl / pclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) val = (u32)div_u64((mode->htotal - mode->hsync_start) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mode->clock * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) tc358768_write(priv, TC358768_DSI_HSW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* hbp (not used in event mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) tc358768_write(priv, TC358768_DSI_HBPR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* hact (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) tc358768_write(priv, TC358768_DSI_HACT, hact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* VSYNC polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* HSYNC polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (mode->flags & DRM_MODE_FLAG_PHSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Start DSI Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) tc358768_write(priv, TC358768_DSI_START, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Configure DSI_Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) tc358768_write(priv, TC358768_DSI_CONFW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val |= (dsi_dev->lanes - 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val |= TC358768_DSI_CONTROL_TXMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) val |= TC358768_DSI_CONTROL_HSCKMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val |= TC358768_DSI_CONTROL_EOTDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tc358768_write(priv, TC358768_DSI_CONFW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) tc358768_write(priv, TC358768_DSI_CONFW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) tc358768_bridge_disable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) tc358768_bridge_post_disable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static void tc358768_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct tc358768_priv *priv = bridge_to_tc358768(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(priv->dev, "Bridge is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* clear FrmStop and RstPtr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* set PP_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = tc358768_clear_error(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) tc358768_bridge_disable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) tc358768_bridge_post_disable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const struct drm_bridge_funcs tc358768_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .attach = tc358768_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .mode_valid = tc358768_bridge_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .pre_enable = tc358768_bridge_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .enable = tc358768_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .disable = tc358768_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .post_disable = tc358768_bridge_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct drm_bridge_timings default_tc358768_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) | DRM_BUS_FLAG_DE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static bool tc358768_is_reserved_reg(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case 0x114 ... 0x13f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case 0x200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case 0x20c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case 0x400 ... 0x408:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case 0x41c ... 0x42f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (tc358768_is_reserved_reg(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case TC358768_CHIPID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case TC358768_FIFOSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (tc358768_is_reserved_reg(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case TC358768_STARTCNTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case TC358768_DSI_START ... (TC358768_DSI_START + 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case TC358768_DBG_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const struct regmap_config tc358768_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .name = "tc358768",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .max_register = TC358768_DSI_HACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .writeable_reg = tc358768_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .readable_reg = tc358768_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .reg_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .val_format_endian = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const struct i2c_device_id tc358768_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { "tc358768", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { "tc358778", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const struct of_device_id tc358768_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { .compatible = "toshiba,tc358768", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { .compatible = "toshiba,tc358778", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) MODULE_DEVICE_TABLE(of, tc358768_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int tc358768_get_regulators(struct tc358768_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) priv->supplies[i].supply = tc358768_supplies[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_err(priv->dev, "failed to get regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int tc358768_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct tc358768_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = tc358768_get_regulators(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) priv->refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (IS_ERR(priv->refclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return PTR_ERR(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * RESX is low active, to disable tc358768 initially (keep in reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * the gpio line must be LOW. This is the ASSERTED state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (IS_ERR(priv->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return PTR_ERR(priv->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_err(dev, "Failed to init regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) priv->dsi_host.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) priv->dsi_host.ops = &tc358768_dsi_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) priv->bridge.funcs = &tc358768_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) priv->bridge.timings = &default_tc358768_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) priv->bridge.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) i2c_set_clientdata(client, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return mipi_dsi_host_register(&priv->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int tc358768_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct tc358768_priv *priv = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mipi_dsi_host_unregister(&priv->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static struct i2c_driver tc358768_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .name = "tc358768",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .of_match_table = tc358768_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .id_table = tc358768_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .probe = tc358768_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .remove = tc358768_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) module_i2c_driver(tc358768_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags