^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maciej Purski <m.purski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PPI layer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PPI_STARTPPI 0x0104 /* START control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PPI_LANEENABLE 0x0134 /* Enables each lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PPI_START_FUNCTION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* DSI layer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSI_LANEENABLE 0x0210 /* Enables each lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSI_RX_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Video path registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VP_CTRL 0x0450 /* Video Path Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* LVDS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Input bit numbers used in mux registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) LVI_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LVI_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LVI_R2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) LVI_R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) LVI_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) LVI_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) LVI_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) LVI_R7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) LVI_G0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) LVI_G1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) LVI_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) LVI_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LVI_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LVI_G5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LVI_G6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LVI_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LVI_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LVI_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) LVI_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) LVI_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LVI_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) LVI_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) LVI_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LVI_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LVI_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) LVI_VS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LVI_DE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LVI_L0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LV_CFG 0x049C /* LVDS Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LV_PHY0 0x04A0 /* LVDS PHY 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* System registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SYS_RST 0x0504 /* System Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SYS_ID 0x0580 /* System ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SYS_RST_REG BIT(5) /* Reset Register module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LPX_PERIOD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TTA_SURE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TTA_GET 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Lane enable PPI and DSI register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LANEENABLE_CLEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LANEENABLE_L0EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LANEENABLE_L1EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LANEENABLE_L2EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LANEENABLE_L3EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* LVCFG fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LV_CFG_LVEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LV_CFG_LVDLINK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LV_CFG_CLKPOL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LV_CFG_CLKPOL2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const tc358764_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "vddc", "vddio", "vddlvds"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct tc358764 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int tc358764_clear_error(struct tc358764 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret = ctx->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ctx->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ctx->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cpu_to_le16s(&addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) le32_to_cpus(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ctx->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) data[0] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) data[1] = addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) data[3] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) data[4] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) data[5] = val >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctx->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return container_of(bridge, struct tc358764, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int tc358764_init(struct tc358764 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tc358764_read(ctx, SYS_ID, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ctx->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return tc358764_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_info(ctx->dev, "ID: %#x\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* configure PPI counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* enable four data lanes and clock lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* configure video path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* reset PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LV_PHY0_ND(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* reset bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tc358764_write(ctx, SYS_RST, SYS_RST_LCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* set bit order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LV_CFG_LVEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return tc358764_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void tc358764_reset(struct tc358764 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) gpiod_set_value(ctx->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gpiod_set_value(ctx->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void tc358764_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct tc358764 *ctx = bridge_to_tc358764(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tc358764_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void tc358764_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct tc358764 *ctx = bridge_to_tc358764(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tc358764_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = tc358764_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int tc358764_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct tc358764 *ctx = bridge_to_tc358764(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bridge, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct drm_bridge_funcs tc358764_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .post_disable = tc358764_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .pre_enable = tc358764_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .attach = tc358764_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int tc358764_parse_dt(struct tc358764 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (IS_ERR(ctx->gpio_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(dev, "no reset GPIO pin provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return PTR_ERR(ctx->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) panel_bridge = devm_drm_panel_bridge_add(dev, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return PTR_ERR(panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ctx->panel_bridge = panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int tc358764_configure_regulators(struct tc358764 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ctx->supplies[i].supply = tc358764_supplies[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(ctx->dev, "failed to get regulators: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int tc358764_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct tc358764 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = tc358764_parse_dt(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = tc358764_configure_regulators(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ctx->bridge.funcs = &tc358764_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ctx->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) drm_bridge_add(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drm_bridge_remove(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(dev, "failed to attach dsi\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int tc358764_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) drm_bridge_remove(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct of_device_id tc358764_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { .compatible = "toshiba,tc358764" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_DEVICE_TABLE(of, tc358764_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct mipi_dsi_driver tc358764_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .probe = tc358764_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .remove = tc358764_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "tc358764",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .of_match_table = tc358764_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_mipi_dsi_driver(tc358764_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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