Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2020 Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on tc358764.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Maciej Purski <m.purski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on rpi_touchscreen.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Eric Anholt <eric@anholt.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <drm/drm_fb_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* PPI layer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PPI_STARTPPI		0x0104 /* START control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PPI_LPTXTIMECNT		0x0114 /* LPTX timing signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PPI_D0S_ATMR		0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PPI_D1S_ATMR		0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PPI_D0S_CLRSIPOCOUNT	0x0164 /* Assertion timer for Lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PPI_D1S_CLRSIPOCOUNT	0x0168 /* Assertion timer for Lane 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PPI_START_FUNCTION	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* DSI layer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DSI_STARTDSI		0x0204 /* START control bit of DSI-TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DSI_LANEENABLE		0x0210 /* Enables each lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DSI_RX_START		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* LCDC/DPI Host Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LCDCTRL			0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* SPI Master Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SPICMR			0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SPITCR			0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* System Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SYSCTRL			0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* System registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LPX_PERIOD		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* Lane enable PPI and DSI register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define LANEENABLE_CLEN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define LANEENABLE_L0EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LANEENABLE_L1EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct tc358762 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	bool pre_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int tc358762_clear_error(struct tc358762 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int ret = ctx->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ctx->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ctx->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	data[0] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	data[1] = addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	data[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	data[3] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	data[4] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	data[5] = val >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		ctx->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline struct tc358762 *bridge_to_tc358762(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return container_of(bridge, struct tc358762, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int tc358762_init(struct tc358762 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tc358762_write(ctx, DSI_LANEENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		       LANEENABLE_L0EN | LANEENABLE_CLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tc358762_write(ctx, PPI_D0S_ATMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	tc358762_write(ctx, PPI_D1S_ATMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tc358762_write(ctx, SPICMR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tc358762_write(ctx, LCDCTRL, 0x00100150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tc358762_write(ctx, SYSCTRL, 0x040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return tc358762_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void tc358762_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct tc358762 *ctx = bridge_to_tc358762(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * The post_disable hook might be called multiple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * We want to avoid regulator imbalance below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!ctx->pre_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ctx->pre_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ret = regulator_disable(ctx->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void tc358762_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct tc358762 *ctx = bridge_to_tc358762(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret = regulator_enable(ctx->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = tc358762_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ctx->pre_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int tc358762_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			   enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct tc358762 *ctx = bridge_to_tc358762(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				 bridge, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct drm_bridge_funcs tc358762_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.post_disable = tc358762_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.pre_enable = tc358762_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.attach = tc358762_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int tc358762_parse_dt(struct tc358762 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	panel_bridge = devm_drm_panel_bridge_add(dev, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (IS_ERR(panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return PTR_ERR(panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ctx->panel_bridge = panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int tc358762_configure_regulators(struct tc358762 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ctx->regulator = devm_regulator_get(ctx->dev, "vddc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (IS_ERR(ctx->regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return PTR_ERR(ctx->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int tc358762_probe(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct device *dev = &dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct tc358762 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mipi_dsi_set_drvdata(dsi, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ctx->pre_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* TODO: Find out how to get dual-lane mode working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	dsi->lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			  MIPI_DSI_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ret = tc358762_parse_dt(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ret = tc358762_configure_regulators(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ctx->bridge.funcs = &tc358762_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ctx->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	drm_bridge_add(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		drm_bridge_remove(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		dev_err(dev, "failed to attach dsi\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int tc358762_remove(struct mipi_dsi_device *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct tc358762 *ctx = mipi_dsi_get_drvdata(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mipi_dsi_detach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	drm_bridge_remove(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct of_device_id tc358762_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	{ .compatible = "toshiba,tc358762" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_DEVICE_TABLE(of, tc358762_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct mipi_dsi_driver tc358762_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.probe = tc358762_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.remove = tc358762_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.name = "tc358762",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.of_match_table = tc358762_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) module_mipi_dsi_driver(tc358762_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358762 DSI/DPI Bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_LICENSE("GPL v2");