^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015-2016 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015-2016 NextThing Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct simple_bridge_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const struct drm_bridge_timings *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int connector_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct simple_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const struct simple_bridge_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct drm_bridge *next_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct gpio_desc *enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline struct simple_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) drm_bridge_to_simple_bridge(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return container_of(bridge, struct simple_bridge, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline struct simple_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) drm_connector_to_simple_bridge(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return container_of(connector, struct simple_bridge, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int simple_bridge_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct simple_bridge *sbridge = drm_connector_to_simple_bridge(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (sbridge->next_bridge->ops & DRM_BRIDGE_OP_EDID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) edid = drm_bridge_get_edid(sbridge->next_bridge, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DRM_INFO("EDID read failed. Fallback to standard modes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * In case we cannot retrieve the EDIDs (missing or broken DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * bus from the next bridge), fallback on the XGA standards and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * prefer a mode pretty much anyone can handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = drm_add_modes_noedid(connector, 1920, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) drm_set_preferred_mode(connector, 1024, 768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) drm_connector_update_edid_property(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = drm_add_edid_modes(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct drm_connector_helper_funcs simple_bridge_con_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .get_modes = simple_bridge_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) simple_bridge_connector_detect(struct drm_connector *connector, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct simple_bridge *sbridge = drm_connector_to_simple_bridge(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return drm_bridge_detect(sbridge->next_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct drm_connector_funcs simple_bridge_con_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .detect = simple_bridge_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int simple_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct simple_bridge *sbridge = drm_bridge_to_simple_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = drm_bridge_attach(bridge->encoder, sbridge->next_bridge, bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DRM_BRIDGE_ATTACH_NO_CONNECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!bridge->encoder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DRM_ERROR("Missing encoder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) drm_connector_helper_add(&sbridge->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &simple_bridge_con_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = drm_connector_init_with_ddc(bridge->dev, &sbridge->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &simple_bridge_con_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) sbridge->info->connector_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sbridge->next_bridge->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DRM_ERROR("Failed to initialize connector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) drm_connector_attach_encoder(&sbridge->connector, bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void simple_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct simple_bridge *sbridge = drm_bridge_to_simple_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (sbridge->vdd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = regulator_enable(sbridge->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) gpiod_set_value_cansleep(sbridge->enable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void simple_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct simple_bridge *sbridge = drm_bridge_to_simple_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) gpiod_set_value_cansleep(sbridge->enable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (sbridge->vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regulator_disable(sbridge->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct drm_bridge_funcs simple_bridge_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .attach = simple_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .enable = simple_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .disable = simple_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int simple_bridge_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct simple_bridge *sbridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device_node *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sbridge = devm_kzalloc(&pdev->dev, sizeof(*sbridge), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!sbridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) platform_set_drvdata(pdev, sbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sbridge->info = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Get the next bridge in the pipeline. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) remote = of_graph_get_remote_node(pdev->dev.of_node, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!remote)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sbridge->next_bridge = of_drm_find_bridge(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) of_node_put(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!sbridge->next_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(&pdev->dev, "Next bridge not found, deferring probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Get the regulator and GPIO resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sbridge->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(sbridge->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret = PTR_ERR(sbridge->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sbridge->vdd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sbridge->enable = devm_gpiod_get_optional(&pdev->dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (IS_ERR(sbridge->enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (PTR_ERR(sbridge->enable) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(&pdev->dev, "Unable to retrieve enable GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return PTR_ERR(sbridge->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Register the bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sbridge->bridge.funcs = &simple_bridge_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sbridge->bridge.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sbridge->bridge.timings = sbridge->info->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) drm_bridge_add(&sbridge->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int simple_bridge_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct simple_bridge *sbridge = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) drm_bridge_remove(&sbridge->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * We assume the ADV7123 DAC is the "default" for historical reasons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Information taken from the ADV7123 datasheet, revision D.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * NOTE: the ADV7123EP seems to have other timings and need a new timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * set if used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct drm_bridge_timings default_bridge_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Timing specifications, datasheet page 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .setup_time_ps = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .hold_time_ps = 1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Information taken from the THS8134, THS8134A, THS8134B datasheet named
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * "SLVS205D", dated May 1990, revised March 2000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct drm_bridge_timings ti_ths8134_bridge_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* From timing diagram, datasheet page 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* From datasheet, page 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .setup_time_ps = 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* I guess this means latched input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .hold_time_ps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Information taken from the THS8135 datasheet named "SLAS343B", dated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * May 2001, revised April 2013.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct drm_bridge_timings ti_ths8135_bridge_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* From timing diagram, datasheet page 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* From datasheet, page 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .setup_time_ps = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .hold_time_ps = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct of_device_id simple_bridge_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .compatible = "dumb-vga-dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .data = &(const struct simple_bridge_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .connector_type = DRM_MODE_CONNECTOR_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .compatible = "adi,adv7123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .data = &(const struct simple_bridge_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .timings = &default_bridge_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .connector_type = DRM_MODE_CONNECTOR_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .compatible = "ti,opa362",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .data = &(const struct simple_bridge_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .connector_type = DRM_MODE_CONNECTOR_Composite,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .compatible = "ti,ths8135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .data = &(const struct simple_bridge_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .timings = &ti_ths8135_bridge_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .connector_type = DRM_MODE_CONNECTOR_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .compatible = "ti,ths8134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .data = &(const struct simple_bridge_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .timings = &ti_ths8134_bridge_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .connector_type = DRM_MODE_CONNECTOR_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DEVICE_TABLE(of, simple_bridge_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct platform_driver simple_bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .probe = simple_bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .remove = simple_bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "simple-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .of_match_table = simple_bridge_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) module_platform_driver(simple_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_DESCRIPTION("Simple DRM bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags