^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Registers of Silicon Image SiI8620 Mobile HD Transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on MHL driver for Android devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2013-2014 Silicon Image, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SIL_SII8620_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SIL_SII8620_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Vendor ID Low byte, default value: 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_VND_IDL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Vendor ID High byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_VND_IDH 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Device ID Low byte, default value: 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_DEV_IDL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Device ID High byte, default value: 0x86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_DEV_IDH 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Device Revision, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_DEV_REV 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* OTP DBYTE510, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_OTP_DBYTE510 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* System Control #1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_SYS_CTRL1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* System Control DPD, default value: 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_DPD 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BIT_DPD_PWRON_PLL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BIT_DPD_PDNTX12 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BIT_DPD_PDNRX12 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BIT_DPD_OSC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BIT_DPD_PWRON_HSIC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BIT_DPD_PDIDCK_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BIT_DPD_PD_MHL_CLK_N BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Dual link Control, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_DCTL 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BIT_DCTL_TDM_LCLK_PHASE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BIT_DCTL_HSIC_CLK_PHASE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BIT_DCTL_CTS_TCK_PHASE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BIT_DCTL_EXT_DDC_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BIT_DCTL_TRANSCODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BIT_DCTL_TCLKNX_PHASE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PWD Software Reset, default value: 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_PWD_SRST 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BIT_PWD_SRST_COC_DOC_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BIT_PWD_SRST_CBUS_RST_SW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BIT_PWD_SRST_CBUS_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BIT_PWD_SRST_SW_RST_AUTO BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BIT_PWD_SRST_SW_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* AKSV_1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_AKSV_1 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Video H Resolution #1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_H_RESL 0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Video Mode, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_VID_MODE 0x004a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BIT_VID_MODE_M1080P BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Video Input Mode, default value: 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_VID_OVRRD 0x0051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BIT_VID_OVRRD_M1080P_OVRRD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* I2C Address reassignment, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_PAGE_MHLSPEC_ADDR 0x0057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_PAGE7_ADDR 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_PAGE8_ADDR 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Fast Interrupt Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_FAST_INTR_STAT 0x005f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LEN_FAST_INTR_STAT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BIT_FAST_INTR_STAT_TIMR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BIT_FAST_INTR_STAT_INT2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BIT_FAST_INTR_STAT_DDC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BIT_FAST_INTR_STAT_SCDT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BIT_FAST_INTR_STAT_INFR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BIT_FAST_INTR_STAT_EDID 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BIT_FAST_INTR_STAT_HDCP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BIT_FAST_INTR_STAT_MSC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BIT_FAST_INTR_STAT_MERR 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BIT_FAST_INTR_STAT_G2WB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BIT_FAST_INTR_STAT_G2WB_ERR 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BIT_FAST_INTR_STAT_DISC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BIT_FAST_INTR_STAT_BLOCK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BIT_FAST_INTR_STAT_LTRN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BIT_FAST_INTR_STAT_HDCP2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BIT_FAST_INTR_STAT_TDM 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BIT_FAST_INTR_STAT_COC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* GPIO Control, default value: 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define REG_GPIO_CTRL1 0x006e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BIT_CTRL1_GPIO_I_8 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BIT_CTRL1_GPIO_OEN_8 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BIT_CTRL1_GPIO_I_7 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BIT_CTRL1_GPIO_OEN_7 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BIT_CTRL1_GPIO_I_6 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BIT_CTRL1_GPIO_OEN_6 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Interrupt Control, default value: 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_INT_CTRL 0x006f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BIT_INT_CTRL_SOFTWARE_WP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BIT_INT_CTRL_INTR_OD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BIT_INT_CTRL_INTR_POLARITY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Interrupt State, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_INTR_STATE 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BIT_INTR_STATE_INTR_STATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Interrupt Source #1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_INTR1 0x0071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Interrupt Source #2, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_INTR2 0x0072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Interrupt Source #3, default value: 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REG_INTR3 0x0073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BIT_DDC_CMD_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Interrupt Source #5, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define REG_INTR5 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Interrupt #1 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define REG_INTR1_MASK 0x0075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Interrupt #2 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REG_INTR2_MASK 0x0076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Interrupt #3 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define REG_INTR3_MASK 0x0077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Interrupt #5 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define REG_INTR5_MASK 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BIT_INTR_SCDT_CHANGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Hot Plug Connection Control, default value: 0x45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define REG_HPD_CTRL 0x0079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BIT_HPD_CTRL_HPD_HIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BIT_HPD_CTRL_GPIO_I_1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* GPIO Control, default value: 0x55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REG_GPIO_CTRL 0x007a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BIT_CTRL_GPIO_I_5 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BIT_CTRL_GPIO_OEN_5 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BIT_CTRL_GPIO_I_4 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BIT_CTRL_GPIO_OEN_4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BIT_CTRL_GPIO_I_3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BIT_CTRL_GPIO_OEN_3 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BIT_CTRL_GPIO_I_2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BIT_CTRL_GPIO_OEN_2 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Interrupt Source 7, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define REG_INTR7 0x007b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Interrupt Source 8, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define REG_INTR8 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Interrupt #7 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define REG_INTR7_MASK 0x007d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Interrupt #8 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define REG_INTR8_MASK 0x007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BIT_CEA_NEW_VSI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BIT_CEA_NEW_AVI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* IEEE, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define REG_TMDS_CCTRL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* TMDS Control #4, default value: 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define REG_TMDS_CTRL4 0x0085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* BIST CNTL, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define REG_BIST_CTRL 0x00bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BIT_RXBIST_VGB_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BIT_TXBIST_VGB_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BIT_BIST_START_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BIT_BIST_START_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BIT_BIST_ALWAYS_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BIT_BIST_TRANS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BIT_BIST_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BIT_BIST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* BIST DURATION0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define REG_BIST_TEST_SEL 0x00bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MSK_BIST_TEST_SEL_BIST_PATT_SEL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* BIST VIDEO_MODE, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define REG_BIST_VIDEO_MODE 0x00be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* BIST DURATION0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define REG_BIST_DURATION_0 0x00bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* BIST DURATION1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define REG_BIST_DURATION_1 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* BIST DURATION2, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define REG_BIST_DURATION_2 0x00c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* BIST 8BIT_PATTERN, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define REG_BIST_8BIT_PATTERN 0x00c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* LM DDC, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define REG_LM_DDC 0x00c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BIT_LM_DDC_DDC_TPI_SW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BIT_LM_DDC_DDC_GRANT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* DDC I2C Manual, default value: 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define REG_DDC_MANUAL 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define BIT_DDC_MANUAL_MAN_DDC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BIT_DDC_MANUAL_VP_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BIT_DDC_MANUAL_DSDA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BIT_DDC_MANUAL_DSCL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BIT_DDC_MANUAL_IO_DSDA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BIT_DDC_MANUAL_IO_DSCL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* DDC I2C Target Slave Address, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define REG_DDC_ADDR 0x00ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MSK_DDC_ADDR_DDC_ADDR 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* DDC I2C Target Segment Address, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define REG_DDC_SEGM 0x00ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* DDC I2C Target Offset Address, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define REG_DDC_OFFSET 0x00ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* DDC I2C Data In count #1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define REG_DDC_DIN_CNT1 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* DDC I2C Data In count #2, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define REG_DDC_DIN_CNT2 0x00f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* DDC I2C Status, default value: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define REG_DDC_STATUS 0x00f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BIT_DDC_STATUS_DDC_NO_ACK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* DDC I2C Command, default value: 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define REG_DDC_CMD 0x00f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BIT_DDC_CMD_HDCP_DDC_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BIT_DDC_CMD_SDA_DEL_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MSK_DDC_CMD_DDC_CMD 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define VAL_DDC_CMD_DDC_CMD_ABORT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* DDC I2C FIFO Data In/Out, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define REG_DDC_DATA 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* DDC I2C Data Out Counter, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define REG_DDC_DOUT_CNT 0x00f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* DDC I2C Delay Count, default value: 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define REG_DDC_DELAY_CNT 0x00f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Test Control, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define REG_TEST_TXCTRL 0x00f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MSK_TEST_TXCTRL_BYPASS_PLL_CLK 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define BIT_TEST_TXCTRL_TST_PLLCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* CBUS Address, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define REG_PAGE_CBUS_ADDR 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* I2C Device Address re-assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define REG_PAGE1_ADDR 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define REG_PAGE2_ADDR 0x00fd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define REG_PAGE3_ADDR 0x00fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define REG_HW_TPI_ADDR 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* USBT CTRL0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define REG_UTSRST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BIT_UTSRST_FC_SRST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define BIT_UTSRST_KEEPER_SRST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BIT_UTSRST_HTX_SRST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BIT_UTSRST_TRX_SRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BIT_UTSRST_TTX_SRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BIT_UTSRST_HRX_SRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* HSIC RX Control3, default value: 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define REG_HRXCTRL3 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MSK_HRXCTRL3_HRX_AFFCTRL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define BIT_HRXCTRL3_HRX_OUT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BIT_HRXCTRL3_STATUS_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* HSIC RX INT Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define REG_HRXINTL 0x0111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define REG_HRXINTH 0x0112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* TDM TX NUMBITS, default value: 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define REG_TTXNUMB 0x0116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MSK_TTXNUMB_TTX_NUMBPS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* TDM TX NUMSPISYM, default value: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define REG_TTXSPINUMS 0x0117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* TDM TX NUMHSICSYM, default value: 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define REG_TTXHSICNUMS 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* TDM TX NUMTOTSYM, default value: 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define REG_TTXTOTNUMS 0x0119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* TDM TX INT Low, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define REG_TTXINTL 0x0136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define BIT_TTXINTL_TTX_INTR7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define BIT_TTXINTL_TTX_INTR6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define BIT_TTXINTL_TTX_INTR5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define BIT_TTXINTL_TTX_INTR4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BIT_TTXINTL_TTX_INTR3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define BIT_TTXINTL_TTX_INTR2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BIT_TTXINTL_TTX_INTR1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BIT_TTXINTL_TTX_INTR0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* TDM TX INT High, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define REG_TTXINTH 0x0137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BIT_TTXINTH_TTX_INTR15 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define BIT_TTXINTH_TTX_INTR14 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define BIT_TTXINTH_TTX_INTR13 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define BIT_TTXINTH_TTX_INTR12 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BIT_TTXINTH_TTX_INTR11 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define BIT_TTXINTH_TTX_INTR10 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BIT_TTXINTH_TTX_INTR9 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define BIT_TTXINTH_TTX_INTR8 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* TDM RX Control, default value: 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define REG_TRXCTRL 0x013b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MSK_TRXCTRL_TRX_NUMBPS_2_0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* TDM RX NUMSPISYM, default value: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define REG_TRXSPINUMS 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* TDM RX NUMHSICSYM, default value: 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define REG_TRXHSICNUMS 0x013d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* TDM RX NUMTOTSYM, default value: 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define REG_TRXTOTNUMS 0x013e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* TDM RX Status 2nd, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define REG_TRXSTA2 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MSK_TDM_SYNCHRONIZED 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define VAL_TDM_SYNCHRONIZED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* TDM RX INT Low, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define REG_TRXINTL 0x0163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* TDM RX INT High, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define REG_TRXINTH 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BIT_TDM_INTR_SYNC_DATA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BIT_TDM_INTR_SYNC_WAIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* TDM RX INTMASK High, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define REG_TRXINTMH 0x0166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* HSIC TX CRTL, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define REG_HTXCTRL 0x0169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BIT_HTXCTRL_HTX_DRVRST1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* HSIC TX INT Low, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define REG_HTXINTL 0x017d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* HSIC TX INT High, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define REG_HTXINTH 0x017e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* HSIC Keeper, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define REG_KEEPER 0x0181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MSK_KEEPER_MODE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define VAL_KEEPER_MODE_HOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define VAL_KEEPER_MODE_DEVICE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* HSIC Flow Control General, default value: 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define REG_FCGC 0x0183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define BIT_FCGC_HSIC_HOSTMODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define BIT_FCGC_HSIC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* HSIC Flow Control CTR13, default value: 0xfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define REG_FCCTR13 0x0191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* HSIC Flow Control CTR14, default value: 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define REG_FCCTR14 0x0192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* HSIC Flow Control CTR15, default value: 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define REG_FCCTR15 0x0193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* HSIC Flow Control CTR50, default value: 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define REG_FCCTR50 0x01b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* HSIC Flow Control INTR0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define REG_FCINTR0 0x01ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define REG_FCINTR1 0x01ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define REG_FCINTR2 0x01ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define REG_FCINTR3 0x01ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define REG_FCINTR4 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define REG_FCINTR5 0x01f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define REG_FCINTR6 0x01f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define REG_FCINTR7 0x01f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* TDM Low Latency, default value: 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define REG_TDMLLCTL 0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MSK_TDMLLCTL_TRX_LL_SEL_MODE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* TMDS 0 Clock Control, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define REG_TMDS0_CCTRL1 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MSK_TMDS0_CCTRL1_TEST_SEL 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define MSK_TMDS0_CCTRL1_CLK1X_CTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* TMDS Clock Enable, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define REG_TMDS_CLK_EN 0x0211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define BIT_TMDS_CLK_EN_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* TMDS Channel Enable, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define REG_TMDS_CH_EN 0x0212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define BIT_TMDS_CH_EN_CH0_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define BIT_TMDS_CH_EN_CH12_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* BGR_BIAS, default value: 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define REG_BGR_BIAS 0x0215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define BIT_BGR_BIAS_BGR_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MSK_BGR_BIAS_BIAS_BGR_D 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* TMDS 0 Digital I2C BW, default value: 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define REG_ALICE0_BW_I2C 0x0231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* TMDS 0 Digital Zone Control, default value: 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define REG_ALICE0_ZONE_CTRL 0x024c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MSK_ALICE0_ZONE_CTRL_SZONE_I2C 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* TMDS 0 Digital PLL Mode Control, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define REG_ALICE0_MODE_CTRL 0x024d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define MSK_ALICE0_MODE_CTRL_DIV20_CTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* MHL Tx Control 6th, default value: 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define REG_MHLTX_CTL6 0x0285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MSK_MHLTX_CTL6_EMI_SEL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Packet Filter0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define REG_PKT_FILTER_0 0x0290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Packet Filter1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define REG_PKT_FILTER_1 0x0291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* TMDS Clock Status, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define REG_TMDS_CSTAT_P3 0x02a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define BIT_TMDS_CSTAT_P3_CKDT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* RX_HDMI Control, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define REG_RX_HDMI_CTRL0 0x02a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* RX_HDMI Control, default value: 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define REG_RX_HDMI_CTRL2 0x02a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* RX_HDMI Control, default value: 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define REG_RX_HDMI_CTRL3 0x02a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* rx_hdmi Clear Buffer, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define REG_RX_HDMI_CLR_BUFFER 0x02ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* RX_HDMI VSI Header1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define REG_RX_HDMI_MON_PKT_HEADER1 0x02b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* RX_HDMI VSI MHL Monitor, default value: 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define REG_RX_HDMI_VSIF_MHL_MON 0x02d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Interrupt Source 9, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define REG_INTR9 0x02e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define BIT_INTR9_EDID_ERROR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define BIT_INTR9_EDID_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define BIT_INTR9_DEVCAP_DONE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Interrupt 9 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define REG_INTR9_MASK 0x02e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* TPI CBUS Start, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define REG_TPI_CBUS_START 0x02e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* EDID Control, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define REG_EDID_CTRL 0x02e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define BIT_EDID_CTRL_XDEVCAP_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define BIT_EDID_CTRL_EDID_MODE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* EDID FIFO Addr, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define REG_EDID_FIFO_ADDR 0x02e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* EDID FIFO Write Data, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define REG_EDID_FIFO_WR_DATA 0x02ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define REG_EDID_FIFO_ADDR_MON 0x02eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* EDID FIFO Read Data, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define REG_EDID_FIFO_RD_DATA 0x02ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* EDID DDC Segment Pointer, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define REG_EDID_START_EXT 0x02ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* TX IP BIST CNTL and Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define REG_TX_IP_BIST_CNTLSTA 0x02f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* TX IP BIST INST LOW, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define REG_TX_IP_BIST_INST_LOW 0x02f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define REG_TX_IP_BIST_INST_HIGH 0x02f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* TX IP BIST PATTERN LOW, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define REG_TX_IP_BIST_PAT_LOW 0x02f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define REG_TX_IP_BIST_PAT_HIGH 0x02f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* TX IP BIST CONFIGURE LOW, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define REG_TX_IP_BIST_CONF_LOW 0x02f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define REG_TX_IP_BIST_CONF_HIGH 0x02f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* E-MSC General Control, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define REG_GENCTL 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define BIT_GENCTL_SPEC_TRANS_DIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define BIT_GENCTL_SPI_MISO_EDGE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define BIT_GENCTL_EMSC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* E-MSC Comma ErrorCNT, default value: 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define REG_COMMECNT 0x0305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MSK_COMMECNT_COMMA_CHAR_ERR_CNT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* E-MSC RFIFO ByteCnt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define REG_EMSCRFIFOBCNTL 0x031a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define REG_EMSCRFIFOBCNTH 0x031b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* SPI Burst Cnt Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define REG_SPIBURSTCNT 0x031e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* SPI Burst Status and SWRST, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define REG_SPIBURSTSTAT 0x0322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define BIT_SPIBURSTSTAT_SPI_SRST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* E-MSC 1st Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define REG_EMSCINTR 0x0323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define BIT_EMSCINTR_SPI_DVLD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* E-MSC Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define REG_EMSCINTRMASK 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define REG_EMSC_XMIT_WRITE_PORT 0x032a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define REG_EMSC_RCV_READ_PORT 0x032b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* E-MSC 2nd Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define REG_EMSCINTR1 0x032c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* E-MSC Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define REG_EMSCINTRMASK1 0x032d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* MHL Top Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define REG_MHL_TOP_CTL 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MSK_MHL_TOP_CTL_IF_TIMING_CTL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* MHL DataPath 1st Ctl, default value: 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define REG_MHL_DP_CTL0 0x0331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define BIT_MHL_DP_CTL0_DP_OE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define MSK_MHL_DP_CTL0_TX_OE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* MHL DataPath 2nd Ctl, default value: 0xbb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define REG_MHL_DP_CTL1 0x0332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define MSK_MHL_DP_CTL1_CK_SWING_CTL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define MSK_MHL_DP_CTL1_DT_SWING_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* MHL DataPath 3rd Ctl, default value: 0x2f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define REG_MHL_DP_CTL2 0x0333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define MSK_MHL_DP_CTL2_DAMP_TERM_SEL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define MSK_MHL_DP_CTL2_CK_TERM_SEL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define MSK_MHL_DP_CTL2_DT_TERM_SEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* MHL DataPath 4th Ctl, default value: 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define REG_MHL_DP_CTL3 0x0334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* MHL DataPath 5th Ctl, default value: 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define REG_MHL_DP_CTL4 0x0335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* MHL DataPath 6th Ctl, default value: 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define REG_MHL_DP_CTL5 0x0336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define BIT_MHL_DP_CTL5_RSEN_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* MHL PLL 1st Ctl, default value: 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define REG_MHL_PLL_CTL0 0x0337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* MHL PLL 3rd Ctl, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define REG_MHL_PLL_CTL2 0x0339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define MSK_MHL_PLL_CTL2_PLL_LF_SEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* MHL CBUS 1st Ctl, default value: 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define REG_MHL_CBUS_CTL0 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* MHL CBUS 2nd Ctl, default value: 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define REG_MHL_CBUS_CTL1 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define VAL_MHL_CBUS_CTL1_0888_OHM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define VAL_MHL_CBUS_CTL1_1115_OHM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define VAL_MHL_CBUS_CTL1_1378_OHM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* MHL CoC 1st Ctl, default value: 0xc3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define REG_MHL_COC_CTL0 0x0342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define MSK_MHL_COC_CTL0_COC_BIAS_CTL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MSK_MHL_COC_CTL0_COC_TERM_CTL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* MHL CoC 2nd Ctl, default value: 0x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define REG_MHL_COC_CTL1 0x0343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define BIT_MHL_COC_CTL1_COC_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define MSK_MHL_COC_CTL1_COC_DRV_CTL 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* MHL CoC 4th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define REG_MHL_COC_CTL3 0x0345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* MHL CoC 5th Ctl, default value: 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define REG_MHL_COC_CTL4 0x0346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MSK_MHL_COC_CTL4_COC_IF_CTL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MSK_MHL_COC_CTL4_COC_SLEW_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* MHL CoC 6th Ctl, default value: 0x0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define REG_MHL_COC_CTL5 0x0347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* MHL DoC 1st Ctl, default value: 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define REG_MHL_DOC_CTL0 0x0349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MSK_MHL_DOC_CTL0_DOC_DM_TERM 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MSK_MHL_DOC_CTL0_DOC_OPMODE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* MHL DataPath 7th Ctl, default value: 0x2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define REG_MHL_DP_CTL6 0x0350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* MHL DataPath 8th Ctl, default value: 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define REG_MHL_DP_CTL7 0x0351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define REG_MHL_DP_CTL8 0x0352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Tx Zone Ctl1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define REG_TX_ZONE_CTL1 0x0361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* MHL3 Tx Zone Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define REG_MHL3_TX_ZONE_CTL 0x0364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MSK_TX_ZONE_CTL3_TX_ZONE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* HDCP Polling Control and Status, default value: 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define REG_HDCP2X_POLL_CS 0x0391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define MSK_HDCP2X_POLL_CS_ 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* HDCP Interrupt 0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define REG_HDCP2X_INTR0 0x0398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* HDCP Interrupt 0 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define REG_HDCP2X_INTR0_MASK 0x0399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* HDCP General Control 0, default value: 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define REG_HDCP2X_CTRL_0 0x03a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* HDCP General Control 1, default value: 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define REG_HDCP2X_CTRL_1 0x03a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* HDCP Misc Control, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define REG_HDCP2X_MISC_CTRL 0x03a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* HDCP RPT SMNG K, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define REG_HDCP2X_RPT_SMNG_K 0x03a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* HDCP RPT SMNG In, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define REG_HDCP2X_RPT_SMNG_IN 0x03a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* HDCP Auth Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define REG_HDCP2X_AUTH_STAT 0x03aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* HDCP RPT RCVID Out, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define REG_HDCP2X_RPT_RCVID_OUT 0x03ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* HDCP TP1, default value: 0x62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define REG_HDCP2X_TP1 0x03b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* HDCP GP Out 0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define REG_HDCP2X_GP_OUT0 0x03c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* HDCP Repeater RCVR ID 0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define REG_HDCP2X_RPT_RCVR_ID0 0x03d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* HDCP DDCM Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define REG_HDCP2X_DDCM_STS 0x03d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* HDMI2MHL3 Control, default value: 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define REG_M3_CTRL 0x03e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define BIT_M3_CTRL_H2M_SWRST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define BIT_M3_CTRL_SW_MHL3_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define BIT_M3_CTRL_M3AV_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define BIT_M3_CTRL_ENC_TMDS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define VAL_M3_CTRL_MHL1_2_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) | BIT_M3_CTRL_ENC_TMDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define VAL_M3_CTRL_MHL3_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) | BIT_M3_CTRL_M3AV_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) | BIT_M3_CTRL_ENC_TMDS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) | BIT_M3_CTRL_MHL3_MASTER_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* HDMI2MHL3 Port0 Control, default value: 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define REG_M3_P0CTRL 0x03e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define REG_M3_POSTM 0x03e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define MSK_M3_POSTM_RRP_DECODE 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define MSK_M3_POSTM_MHL3_P0_STM_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* HDMI2MHL3 Scramble Control, default value: 0x41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define REG_M3_SCTRL 0x03e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define MSK_M3_SCTRL_MHL3_SR_LENGTH 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* HSIC Div Ctl, default value: 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define REG_DIV_CTL_MAIN 0x03f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* MHL Capability 1st Byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define REG_MHL_DEVCAP_0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* MHL Interrupt 1st Byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define REG_MHL_INT_0 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Device Status 1st byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define REG_MHL_STAT_0 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* CBUS Scratch Pad 1st Byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define REG_MHL_SCRPAD_0 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* MHL Extended Capability 1st Byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define REG_MHL_EXTDEVCAP_0 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* Device Extended Status 1st byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define REG_MHL_EXTSTAT_0 0x0490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* TPI DTD Byte2, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define REG_TPI_DTD_B2 0x0602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define VAL_TPI_QUAN_RANGE_LIMITED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define VAL_TPI_QUAN_RANGE_FULL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define VAL_TPI_FORMAT_RGB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define VAL_TPI_FORMAT_YCBCR444 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define VAL_TPI_FORMAT_YCBCR422 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define VAL_TPI_FORMAT_INTERNAL_RGB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define VAL_TPI_FORMAT(_fmt, _qr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) (VAL_TPI_FORMAT_##_fmt | (VAL_TPI_QUAN_RANGE_##_qr << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Input Format, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define REG_TPI_INPUT 0x0609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define BIT_TPI_INPUT_ENDITHER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define MSK_TPI_INPUT_INPUT_QUAN_RANGE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define MSK_TPI_INPUT_INPUT_FORMAT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Output Format, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define REG_TPI_OUTPUT 0x060a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define MSK_TPI_OUTPUT_OUTPUT_FORMAT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* TPI AVI Check Sum, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define REG_TPI_AVI_CHSUM 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* TPI System Control, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define REG_TPI_SC 0x061a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define BIT_TPI_SC_DDC_TPI_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* TPI COPP Query Data, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define REG_TPI_COPP_DATA1 0x0629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define VAL_TPI_COPP_LINK_STATUS_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define VAL_TPI_COPP_LINK_STATUS_LINK_LOST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* TPI COPP Control Data, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define REG_TPI_COPP_DATA2 0x062a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* TPI Interrupt Enable, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define REG_TPI_INTR_EN 0x063c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* TPI Interrupt Status Low Byte, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define REG_TPI_INTR_ST0 0x063d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* TPI DS BCAPS Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define REG_TPI_DS_BCAPS 0x0644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* TPI BStatus1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define REG_TPI_BSTATUS1 0x0645
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define MSK_TPI_BSTATUS1_DS_DEV_CNT 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* TPI BStatus2, default value: 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define REG_TPI_BSTATUS2 0x0646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define MSK_TPI_BSTATUS2_DS_BSTATUS 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define MSK_TPI_BSTATUS2_DS_DEPTH 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* TPI HW Optimization Control #3, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define REG_TPI_HW_OPT3 0x06bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* TPI Info Frame Select, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define REG_TPI_INFO_FSEL 0x06bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define BIT_TPI_INFO_FSEL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define BIT_TPI_INFO_FSEL_RPT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define MSK_TPI_INFO_FSEL_PKT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define VAL_TPI_INFO_FSEL_AVI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define VAL_TPI_INFO_FSEL_SPD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define VAL_TPI_INFO_FSEL_AUD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define VAL_TPI_INFO_FSEL_MPG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define VAL_TPI_INFO_FSEL_GEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define VAL_TPI_INFO_FSEL_GEN2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define VAL_TPI_INFO_FSEL_VSI 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* TPI Info Byte #0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define REG_TPI_INFO_B0 0x06c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* CoC Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define REG_COC_STAT_0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define BIT_COC_STAT_0_PLL_LOCKED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define MSK_COC_STAT_0_FSM_STATE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define REG_COC_STAT_1 0x0701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define REG_COC_STAT_2 0x0702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define REG_COC_STAT_3 0x0703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define REG_COC_STAT_4 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define REG_COC_STAT_5 0x0705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* CoC 1st Ctl, default value: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define REG_COC_CTL0 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* CoC 2nd Ctl, default value: 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define REG_COC_CTL1 0x0711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define MSK_COC_CTL1_COC_CTRL1_7_6 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define MSK_COC_CTL1_COC_CTRL1_5_0 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* CoC 3rd Ctl, default value: 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define REG_COC_CTL2 0x0712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define MSK_COC_CTL2_COC_CTRL2_7_6 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define MSK_COC_CTL2_COC_CTRL2_5_0 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* CoC 4th Ctl, default value: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define REG_COC_CTL3 0x0713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define BIT_COC_CTL3_COC_CTRL3_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define MSK_COC_CTL3_COC_CTRL3_6_0 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* CoC 7th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define REG_COC_CTL6 0x0716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define BIT_COC_CTL6_COC_CTRL6_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define BIT_COC_CTL6_COC_CTRL6_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define MSK_COC_CTL6_COC_CTRL6_5_0 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* CoC 8th Ctl, default value: 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define REG_COC_CTL7 0x0717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define BIT_COC_CTL7_COC_CTRL7_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define BIT_COC_CTL7_COC_CTRL7_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define BIT_COC_CTL7_COC_CTRL7_5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define MSK_COC_CTL7_COC_CTRL7_4_3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define MSK_COC_CTL7_COC_CTRL7_2_0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* CoC 10th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define REG_COC_CTL9 0x0719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* CoC 11th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define REG_COC_CTLA 0x071a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* CoC 12th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define REG_COC_CTLB 0x071b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* CoC 13th Ctl, default value: 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define REG_COC_CTLC 0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* CoC 14th Ctl, default value: 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define REG_COC_CTLD 0x071d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define BIT_COC_CTLD_COC_CTRLD_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define MSK_COC_CTLD_COC_CTRLD_6_0 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* CoC 15th Ctl, default value: 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define REG_COC_CTLE 0x071e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define BIT_COC_CTLE_COC_CTRLE_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MSK_COC_CTLE_COC_CTRLE_6_0 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* CoC 16th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define REG_COC_CTLF 0x071f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define MSK_COC_CTLF_COC_CTRLF_7_3 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define MSK_COC_CTLF_COC_CTRLF_2_0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* CoC 18th Ctl, default value: 0x32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define REG_COC_CTL11 0x0721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define MSK_COC_CTL11_COC_CTRL11_7_4 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define MSK_COC_CTL11_COC_CTRL11_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* CoC 21st Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define REG_COC_CTL14 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define MSK_COC_CTL14_COC_CTRL14_7_4 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define MSK_COC_CTL14_COC_CTRL14_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* CoC 22nd Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define REG_COC_CTL15 0x0725
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define BIT_COC_CTL15_COC_CTRL15_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define MSK_COC_CTL15_COC_CTRL15_6_4 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define MSK_COC_CTL15_COC_CTRL15_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* CoC Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define REG_COC_INTR 0x0726
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* CoC Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define REG_COC_INTR_MASK 0x0727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define BIT_COC_CALIBRATION_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* CoC Misc Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define REG_COC_MISC_CTL0 0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define BIT_COC_MISC_CTL0_FSM_MON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* CoC 24th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define REG_COC_CTL17 0x072a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define MSK_COC_CTL17_COC_CTRL17_7_4 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define MSK_COC_CTL17_COC_CTRL17_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* CoC 25th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define REG_COC_CTL18 0x072b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define MSK_COC_CTL18_COC_CTRL18_7_4 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define MSK_COC_CTL18_COC_CTRL18_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* CoC 26th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define REG_COC_CTL19 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define MSK_COC_CTL19_COC_CTRL19_7_4 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define MSK_COC_CTL19_COC_CTRL19_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* CoC 27th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define REG_COC_CTL1A 0x072d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define MSK_COC_CTL1A_COC_CTRL1A_7_2 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define MSK_COC_CTL1A_COC_CTRL1A_1_0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* DoC 9th Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define REG_DOC_STAT_8 0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* DoC 10th Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define REG_DOC_STAT_9 0x0741
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* DoC 5th CFG, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define REG_DOC_CFG4 0x074e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define MSK_DOC_CFG4_DBG_STATE_DOC_FSM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* DoC 1st Ctl, default value: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define REG_DOC_CTL0 0x0751
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* DoC 7th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define REG_DOC_CTL6 0x0757
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define MSK_DOC_CTL6_DOC_CTRL6_5_4 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define MSK_DOC_CTL6_DOC_CTRL6_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* DoC 8th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define REG_DOC_CTL7 0x0758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define MSK_DOC_CTL7_DOC_CTRL7_4_3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define MSK_DOC_CTL7_DOC_CTRL7_2_0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* DoC 9th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define REG_DOC_CTL8 0x076c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define MSK_DOC_CTL8_DOC_CTRL8_6_4 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define MSK_DOC_CTL8_DOC_CTRL8_3_2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define MSK_DOC_CTL8_DOC_CTRL8_1_0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* DoC 10th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define REG_DOC_CTL9 0x076d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* DoC 11th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define REG_DOC_CTLA 0x076e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* DoC 15th Ctl, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define REG_DOC_CTLE 0x0772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define MSK_DOC_CTLE_DOC_CTRLE_5_4 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define MSK_DOC_CTLE_DOC_CTRLE_3_0 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Interrupt Mask 1st, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define REG_MHL_INT_0_MASK 0x0580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Interrupt Mask 2nd, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define REG_MHL_INT_1_MASK 0x0581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Interrupt Mask 3rd, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define REG_MHL_INT_2_MASK 0x0582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Interrupt Mask 4th, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define REG_MHL_INT_3_MASK 0x0583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* MDT Receive Time Out, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define REG_MDT_RCV_TIMEOUT 0x0584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /* MDT Transmit Time Out, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define REG_MDT_XMIT_TIMEOUT 0x0585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* MDT Receive Control, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define REG_MDT_RCV_CTRL 0x0586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* MDT Receive Read Port, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define REG_MDT_RCV_READ_PORT 0x0587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* MDT Transmit Control, default value: 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define REG_MDT_XMIT_CTRL 0x0588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define BIT_MDT_XMIT_CTRL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* MDT Receive WRITE Port, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define REG_MDT_XMIT_WRITE_PORT 0x0589
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* MDT RFIFO Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define REG_MDT_RFIFO_STAT 0x058a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* MDT XFIFO Status, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define REG_MDT_XFIFO_STAT 0x058b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* MDT Interrupt 0, default value: 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define REG_MDT_INT_0 0x058c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define BIT_MDT_RFIFO_DATA_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define BIT_MDT_XFIFO_EMPTY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* MDT Interrupt 0 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define REG_MDT_INT_0_MASK 0x058d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* MDT Interrupt 1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define REG_MDT_INT_1 0x058e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define BIT_MDT_RCV_TIMEOUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define BIT_MDT_RCV_SM_ERROR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define BIT_MDT_XMIT_TIMEOUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define BIT_MDT_XMIT_SM_ERROR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* MDT Interrupt 1 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define REG_MDT_INT_1_MASK 0x058f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* CBUS Vendor ID, default value: 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define REG_CBUS_VENDOR_ID 0x0590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* CBUS Connection Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define REG_CBUS_STATUS 0x0591
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define BIT_CBUS_STATUS_CBUS_HPD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define BIT_CBUS_STATUS_MHL_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* CBUS Interrupt 1st, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define REG_CBUS_INT_0 0x0592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define BIT_CBUS_MSC_MT_DONE_NACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define BIT_CBUS_MSC_MR_SET_INT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define BIT_CBUS_HPD_CHG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define BIT_CBUS_MSC_MT_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define BIT_CBUS_CNX_CHG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* CBUS Interrupt Mask 1st, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define REG_CBUS_INT_0_MASK 0x0593
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* CBUS Interrupt 2nd, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define REG_CBUS_INT_1 0x0594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define BIT_CBUS_CMD_ABORT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define BIT_CBUS_MSC_ABORT_RCVD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define BIT_CBUS_DDC_ABORT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define BIT_CBUS_CEC_ABORT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* CBUS Interrupt Mask 2nd, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define REG_CBUS_INT_1_MASK 0x0595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* CBUS DDC Abort Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define REG_DDC_ABORT_INT 0x0598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* CBUS DDC Abort Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define REG_DDC_ABORT_INT_MASK 0x0599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* CBUS MSC Requester Abort Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define REG_MSC_MT_ABORT_INT 0x059a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define REG_MSC_MT_ABORT_INT_MASK 0x059b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* CBUS MSC Responder Abort Interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define REG_MSC_MR_ABORT_INT 0x059c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define REG_MSC_MR_ABORT_INT_MASK 0x059d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* CBUS RX DISCOVERY interrupt, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define REG_CBUS_RX_DISC_INT0 0x059e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define REG_CBUS_RX_DISC_INT0_MASK 0x059f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* CBUS_Link_Layer Control #8, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define REG_CBUS_LINK_CTRL_8 0x05a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* MDT State Machine Status, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define REG_MDT_SM_STAT 0x05b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define MSK_MDT_SM_STAT_MDT_RCV_STATE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define MSK_MDT_SM_STAT_MDT_XMIT_STATE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* CBUS MSC command trigger, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define REG_MSC_COMMAND_START 0x05b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define BIT_MSC_COMMAND_START_DEBUG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define BIT_MSC_COMMAND_START_PEER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* CBUS MSC Command/Offset, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define REG_MSC_CMD_OR_OFFSET 0x05b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* CBUS MSC Transmit Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define REG_MSC_1ST_TRANSMIT_DATA 0x05ba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define REG_MSC_2ND_TRANSMIT_DATA 0x05bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* CBUS MSC Requester Received Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define REG_MSC_MT_RCVD_DATA0 0x05bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define REG_MSC_MT_RCVD_DATA1 0x05bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* CBUS MSC Responder MSC_MSG Received Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA 0x05bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA 0x05c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* CBUS MSC Heartbeat Control, default value: 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define REG_MSC_HEARTBEAT_CTRL 0x05c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* CBUS MSC Compatibility Control, default value: 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define REG_CBUS_MSC_COMPAT_CTRL 0x05c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* CBUS3 Converter Control, default value: 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define REG_CBUS3_CNVT 0x05dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define MSK_CBUS3_CNVT_CBUS3_RETRYLMT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* Discovery Control1, default value: 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define REG_DISC_CTRL1 0x05e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define BIT_DISC_CTRL1_HB_ONLY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define MSK_DISC_CTRL1_DISC_ATT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define MSK_DISC_CTRL1_DISC_CYC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define BIT_DISC_CTRL1_DISC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define VAL_PUP_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define VAL_PUP_20K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define VAL_PUP_5K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* Discovery Control4, default value: 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define REG_DISC_CTRL4 0x05e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* Discovery Control5, default value: 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define REG_DISC_CTRL5 0x05e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* Discovery Control8, default value: 0x81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define REG_DISC_CTRL8 0x05e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Discovery Control9, default value: 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define REG_DISC_CTRL9 0x05e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define BIT_DISC_CTRL9_NOMHL_EST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* Discovery Status1, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define REG_DISC_STAT1 0x05eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define BIT_DISC_STAT1_PSM_OVRIDE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define MSK_DISC_STAT1_DISC_SM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Discovery Status2, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define REG_DISC_STAT2 0x05ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define BIT_DISC_STAT2_CBUS_OE_POL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define BIT_DISC_STAT2_CBUS_SATUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define BIT_DISC_STAT2_RSEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define MSK_DISC_STAT2_MHL_VRSN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define VAL_DISC_STAT2_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define VAL_DISC_STAT2_MHL1_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define VAL_DISC_STAT2_MHL3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define VAL_DISC_STAT2_RESERVED 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define MSK_DISC_STAT2_RGND 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define VAL_RGND_OPEN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define VAL_RGND_2K 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define VAL_RGND_1K 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define VAL_RGND_SHORT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* Interrupt CBUS_reg1 INTR0, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define REG_CBUS_DISC_INTR0 0x05ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define BIT_RGND_READY_INT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define BIT_CBUS_MHL12_DISCON_INT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define BIT_CBUS_MHL3_DISCON_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define BIT_NOT_MHL_EST_INT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define BIT_MHL_EST_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define BIT_MHL3_EST_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define VAL_CBUS_MHL_DISCON (BIT_CBUS_MHL12_DISCON_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) | BIT_CBUS_MHL3_DISCON_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) | BIT_NOT_MHL_EST_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define REG_CBUS_DISC_INTR0_MASK 0x05ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #endif /* __SIL_SII8620_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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