^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Samsung Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tomasz Stanislawski <t.stanislaws@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maciej Purski <m.purski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on sii9234 driver created by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Adam Hampson <ahampson@sta.samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Erik Gilling <konkers@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Shankar Bandal <shankar.b@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Dharam Kumar <dharam.kr@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/bridge/mhl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_edid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CBUS_DEVCAP_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SII9234_MHL_VERSION 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SII9234_SCRATCHPAD_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SII9234_INT_STAT_SIZE 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MHL_HPD_OUT_OVR_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MHL_HPD_OUT_OVR_VAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MHL_INIT_TIMEOUT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* MHL Tx registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MHL_TX_SRST 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MHL_TX_SYSSTAT_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MHL_TX_INTR1_REG 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MHL_TX_INTR4_REG 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MHL_TX_INTR1_ENABLE_REG 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MHL_TX_INTR4_ENABLE_REG 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MHL_TX_INT_CTRL_REG 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MHL_TX_TMDS_CCTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MHL_TX_DISC_CTRL1_REG 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MHL_TX_DISC_CTRL2_REG 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MHL_TX_DISC_CTRL3_REG 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MHL_TX_DISC_CTRL4_REG 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MHL_TX_DISC_CTRL5_REG 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MHL_TX_DISC_CTRL6_REG 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MHL_TX_DISC_CTRL7_REG 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MHL_TX_DISC_CTRL8_REG 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MHL_TX_STAT2_REG 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MHL_TX_MHLTX_CTL1_REG 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MHL_TX_MHLTX_CTL2_REG 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MHL_TX_MHLTX_CTL4_REG 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MHL_TX_MHLTX_CTL6_REG 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MHL_TX_MHLTX_CTL7_REG 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RSEN_STATUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HPD_CHANGE_INT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RSEN_CHANGE_INT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RGND_READY_INT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VBUS_LOW_INT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CBUS_LKOUT_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MHL_DISC_FAIL_INT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MHL_EST_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HPD_CHANGE_INT_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RSEN_CHANGE_INT_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RGND_READY_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CBUS_LKOUT_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MHL_DISC_FAIL_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MHL_EST_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SKIP_GND BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ATT_THRESH_SHIFT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ATT_THRESH_MASK (0x03 << ATT_THRESH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USB_D_OEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DEGLITCH_TIME_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEGLITCH_TIME_2MS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEGLITCH_TIME_4MS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEGLITCH_TIME_8MS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEGLITCH_TIME_16MS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEGLITCH_TIME_40MS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEGLITCH_TIME_50MS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DEGLITCH_TIME_60MS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DEGLITCH_TIME_128MS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define USB_D_OVR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define USB_ID_OVR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DVRFLT_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BLOCK_RGND_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SKIP_DEG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CI2CA_POL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CI2CA_WKUP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SINGLE_ATT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define USB_D_ODN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VBUS_CHECK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RGND_INTP_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RGND_INTP_OPEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RGND_INTP_2K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RGND_INTP_1K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RGND_INTP_SHORT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* HDMI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HDMI_RX_TMDS0_CCTRL1_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HDMI_RX_TMDS_CLK_EN_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HDMI_RX_TMDS_CH_EN_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HDMI_RX_PLL_CALREFSEL_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HDMI_RX_PLL_VCOCAL_REG 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HDMI_RX_EQ_DATA0_REG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HDMI_RX_EQ_DATA1_REG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HDMI_RX_EQ_DATA2_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HDMI_RX_EQ_DATA3_REG 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HDMI_RX_EQ_DATA4_REG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HDMI_RX_TMDS_ZONE_CTRL_REG 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HDMI_RX_TMDS_MODE_CTRL_REG 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* CBUS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CBUS_INT_STATUS_1_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CBUS_INTR1_ENABLE_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CBUS_MSC_REQ_ABORT_REASON_REG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CBUS_INT_STATUS_2_REG 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CBUS_INTR2_ENABLE_REG 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CBUS_LINK_CONTROL_2_REG 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CBUS_MHL_STATUS_REG_0 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CBUS_MHL_STATUS_REG_1 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BIT_CBUS_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SET_HPD_DOWNSTREAM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* TPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TPI_DPD_REG 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Timeouts in msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define T_SRC_VBUS_CBUS_TO_STABLE 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define T_SRC_CBUS_FLOAT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define T_SRC_CBUS_DEGLITCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define T_SRC_RXSENSE_DEGLITCH 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MHL1_MAX_CLK 75000 /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define I2C_TPI_ADDR 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I2C_HDMI_ADDR 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define I2C_CBUS_ADDR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum sii9234_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ST_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ST_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ST_RGND_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ST_RGND_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ST_RSEN_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ST_MHL_ESTABLISHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ST_FAILURE_DISCOVERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ST_FAILURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct sii9234 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i2c_client *client[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct regulator_bulk_data supplies[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mutex lock; /* Protects fields below and device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum sii9234_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum sii9234_client_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) I2C_MHL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) I2C_TPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) I2C_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) I2C_CBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const sii9234_client_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [I2C_MHL] = "MHL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [I2C_TPI] = "TPI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [I2C_HDMI] = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [I2C_CBUS] = "CBUS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int sii9234_writeb(struct sii9234 *ctx, int id, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct i2c_client *client = ctx->client[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ctx->i2c_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ctx->i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = i2c_smbus_write_byte_data(client, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sii9234_client_name[id], offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int sii9234_writebm(struct sii9234 *ctx, int id, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int value, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2c_client *client = ctx->client[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ctx->i2c_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ctx->i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = i2c_smbus_write_byte(client, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) sii9234_client_name[id], offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sii9234_client_name[id], offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) value = (value & mask) | (ret & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = i2c_smbus_write_byte_data(client, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sii9234_client_name[id], offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int sii9234_readb(struct sii9234 *ctx, int id, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct i2c_client *client = ctx->client[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ctx->i2c_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ctx->i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = i2c_smbus_write_byte(client, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sii9234_client_name[id], offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sii9234_client_name[id], offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ctx->i2c_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int sii9234_clear_error(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret = ctx->i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctx->i2c_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define mhl_tx_writeb(sii9234, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sii9234_writeb(sii9234, I2C_MHL, offset, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define mhl_tx_writebm(sii9234, offset, value, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sii9234_writebm(sii9234, I2C_MHL, offset, value, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define mhl_tx_readb(sii9234, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) sii9234_readb(sii9234, I2C_MHL, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define cbus_writeb(sii9234, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sii9234_writeb(sii9234, I2C_CBUS, offset, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define cbus_writebm(sii9234, offset, value, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sii9234_writebm(sii9234, I2C_CBUS, offset, value, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define cbus_readb(sii9234, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sii9234_readb(sii9234, I2C_CBUS, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define hdmi_writeb(sii9234, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sii9234_writeb(sii9234, I2C_HDMI, offset, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define hdmi_writebm(sii9234, offset, value, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sii9234_writebm(sii9234, I2C_HDMI, offset, value, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define hdmi_readb(sii9234, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sii9234_readb(sii9234, I2C_HDMI, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define tpi_writeb(sii9234, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sii9234_writeb(sii9234, I2C_TPI, offset, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define tpi_writebm(sii9234, offset, value, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) sii9234_writebm(sii9234, I2C_TPI, offset, value, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define tpi_readb(sii9234, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sii9234_readb(sii9234, I2C_TPI, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static u8 sii9234_tmds_control(struct sii9234 *ctx, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mhl_tx_writebm(ctx, MHL_TX_TMDS_CCTRL, enable ? ~0 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) BIT_TMDS_CCTRL_TMDS_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, enable ? ~0 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MHL_HPD_OUT_OVR_EN | MHL_HPD_OUT_OVR_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int sii9234_cbus_reset(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mhl_tx_writebm(ctx, MHL_TX_SRST, ~0, BIT_CBUS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msleep(T_SRC_CBUS_DEGLITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mhl_tx_writebm(ctx, MHL_TX_SRST, 0, BIT_CBUS_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Enable WRITE_STAT interrupt for writes to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 4 MSC Status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cbus_writeb(ctx, 0xE0 + i, 0xF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Enable SET_INT interrupt for writes to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * 4 MSC Interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cbus_writeb(ctx, 0xF0 + i, 0xF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Require to chek mhl imformation of samsung in cbus_init_register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int sii9234_cbus_init(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cbus_writeb(ctx, 0x07, 0xF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cbus_writeb(ctx, 0x40, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cbus_writeb(ctx, 0x42, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cbus_writeb(ctx, 0x36, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cbus_writeb(ctx, 0x3D, 0xFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cbus_writeb(ctx, 0x1C, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cbus_writeb(ctx, 0x1D, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cbus_writeb(ctx, 0x44, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Setup our devcap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SII9234_MHL_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MHL_DCAP_CAT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MHL_DCAP_VID_LINK_RGB444 | MHL_DCAP_VID_LINK_YCBCR444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MHL_DCAP_VT_GRAPHICS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MHL_DCAP_LD_GUI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MHL_DCAP_FEATURE_RCP_SUPPORT | MHL_DCAP_FEATURE_RAP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) | MHL_DCAP_FEATURE_SP_SUPPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SII9234_SCRATCHPAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SII9234_INT_STAT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cbus_writebm(ctx, 0x31, 0x0C, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cbus_writeb(ctx, 0x30, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cbus_writebm(ctx, 0x3C, 0x30, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cbus_writebm(ctx, 0x22, 0x0D, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cbus_writebm(ctx, 0x2E, 0x15, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void force_usb_id_switch_open(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Disable CBUS discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Force USB ID switch to open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Force upstream HPD to 0 when not in MHL mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void release_usb_id_switch_open(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msleep(T_SRC_CBUS_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Clear USB ID switch to open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Enable CBUS discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int sii9234_power_init(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Force the SiI9234 into the D0 state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tpi_writeb(ctx, TPI_DPD_REG, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Enable TxPLL Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) hdmi_writeb(ctx, HDMI_RX_TMDS_CLK_EN_REG, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Enable Tx Clock Path & Equalizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hdmi_writeb(ctx, HDMI_RX_TMDS_CH_EN_REG, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Power Up TMDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mhl_tx_writeb(ctx, 0x08, 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int sii9234_hdmi_init(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hdmi_writeb(ctx, HDMI_RX_PLL_CALREFSEL_REG, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hdmi_writeb(ctx, HDMI_RX_PLL_VCOCAL_REG, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) hdmi_writeb(ctx, HDMI_RX_EQ_DATA0_REG, 0x8A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) hdmi_writeb(ctx, HDMI_RX_EQ_DATA1_REG, 0x6A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) hdmi_writeb(ctx, HDMI_RX_EQ_DATA2_REG, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) hdmi_writeb(ctx, HDMI_RX_EQ_DATA3_REG, 0xCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) hdmi_writeb(ctx, HDMI_RX_EQ_DATA4_REG, 0xEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hdmi_writeb(ctx, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) hdmi_writeb(ctx, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mhl_tx_writeb(ctx, MHL_TX_TMDS_CCTRL, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hdmi_writeb(ctx, 0x45, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hdmi_writeb(ctx, 0x31, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int sii9234_mhl_tx_ctl_int(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0xD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL2_REG, 0xFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL4_REG, 0xEB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL7_REG, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int sii9234_reset(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = sii9234_power_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = sii9234_cbus_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = sii9234_hdmi_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = sii9234_mhl_tx_ctl_int(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Enable HDCP Compliance safety */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mhl_tx_writeb(ctx, 0x2B, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* CBUS discovery cycle time for each drive and float = 150us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0x04, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Clear bit 6 (reg_skip_rgnd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) | 2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * 1.8V CBUS VTH & GND threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * to meet CTS 3.3.7.2 spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cbus_writebm(ctx, CBUS_LINK_CONTROL_2_REG, ~0, MHL_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL6_REG, 0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* RGND & single discovery attempt (RGND blocking) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DVRFLT_SEL | SINGLE_ATT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Use VBUS path of discovery state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL8_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* 0x92[3] sets the CBUS / ID switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * To allow RGND engine to operate correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * When moving the chip from D2 to D0 (power up, init regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * the values should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * 94[1:0] = 01 reg_cbusmhl_pup_sel[1:0] should be set for 5k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * 93[7:6] = 10 reg_cbusdisc_pup_sel[1:0] should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * set for 10k (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * 93[5:4] = 00 reg_cbusidle_pup_sel[1:0] = open (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Change from CC to 8C to match 5K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * to meet CTS 3.3.72 spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Configure the interrupt as active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Release usb_id switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL1_REG, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = sii9234_cbus_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Enable Auto soft reset on SCDT = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mhl_tx_writeb(ctx, 0x05, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* HDMI Transcode mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mhl_tx_writeb(ctx, 0x0D, 0x1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mhl_tx_writeb(ctx, MHL_TX_INTR4_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) RGND_READY_MASK | CBUS_LKOUT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) | MHL_DISC_FAIL_MASK | MHL_EST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* This point is very important before measure RGND impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) force_usb_id_switch_open(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, 0, 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL5_REG, 0, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) release_usb_id_switch_open(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Force upstream HPD to 0 when not in MHL mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, ~0, 1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int sii9234_goto_d3(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_dbg(ctx->dev, "sii9234: detection started d3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = sii9234_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hdmi_writeb(ctx, 0x01, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* I2C above is expected to fail because power goes down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ctx->state = ST_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(ctx->dev, "%s failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int sii9234_hw_on(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void sii9234_hw_off(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) gpiod_set_value(ctx->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void sii9234_hw_reset(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) gpiod_set_value(ctx->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) gpiod_set_value(ctx->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void sii9234_cable_in(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mutex_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ctx->state != ST_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = sii9234_hw_on(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sii9234_hw_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sii9234_goto_d3(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* To avoid irq storm, when hw is in meta state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) enable_irq(to_i2c_client(ctx->dev)->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mutex_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void sii9234_cable_out(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mutex_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ctx->state == ST_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) disable_irq(to_i2c_client(ctx->dev)->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tpi_writeb(ctx, TPI_DPD_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Turn on&off hpd festure for only QCT HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sii9234_hw_off(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ctx->state = ST_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mutex_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static enum sii9234_state sii9234_rgnd_ready_irq(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ctx->state == ST_D3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(ctx->dev, "RGND_READY_INT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sii9234_hw_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = sii9234_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(ctx->dev, "sii9234_reset() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ST_RGND_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Got interrupt in inappropriate state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ctx->state != ST_RGND_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) value = mhl_tx_readb(ctx, MHL_TX_STAT2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (sii9234_clear_error(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if ((value & RGND_INTP_MASK) != RGND_INTP_1K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_warn(ctx->dev, "RGND is not 1k\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ST_RGND_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(ctx->dev, "RGND 1K!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (sii9234_clear_error(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) msleep(T_SRC_VBUS_CBUS_TO_STABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return ST_RGND_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static enum sii9234_state sii9234_mhl_established(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_dbg(ctx->dev, "mhl est interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Discovery override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Increase DDC translation layer timer (byte mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cbus_writeb(ctx, 0x07, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) cbus_writebm(ctx, 0x44, ~0, 1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Keep the discovery enabled. Need RGND interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RSEN_CHANGE_INT_MASK | HPD_CHANGE_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (sii9234_clear_error(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ST_MHL_ESTABLISHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static enum sii9234_state sii9234_hpd_change(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) value = cbus_readb(ctx, CBUS_MSC_REQ_ABORT_REASON_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (sii9234_clear_error(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (value & SET_HPD_DOWNSTREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Downstream HPD High, Enable TMDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sii9234_tmds_control(ctx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Downstream HPD Low, Disable TMDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sii9234_tmds_control(ctx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ctx->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static enum sii9234_state sii9234_rsen_change(struct sii9234 *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Work_around code to handle wrong interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ctx->state != ST_RGND_1K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(ctx->dev, "RSEN_HIGH without RGND_1K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (value & RSEN_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_dbg(ctx->dev, "MHL cable connected.. RSEN High\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ST_RSEN_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_dbg(ctx->dev, "RSEN lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * Once RSEN loss is confirmed,we need to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * based on cable status and chip power status,whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * it is SINK Loss(HDMI cable not connected, TV Off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * or MHL cable disconnection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * TODO: Define the below mhl_disconnection()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) msleep(T_SRC_RXSENSE_DEGLITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_dbg(ctx->dev, "sys_stat: %x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (value & RSEN_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_dbg(ctx->dev, "RSEN recovery\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ST_RSEN_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_dbg(ctx->dev, "RSEN Really LOW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* To meet CTS 3.3.22.2 spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) sii9234_tmds_control(ctx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) force_usb_id_switch_open(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) release_usb_id_switch_open(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static irqreturn_t sii9234_irq_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct sii9234 *ctx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int intr1, intr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int intr1_en, intr4_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int cbus_intr1, cbus_intr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_dbg(ctx->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mutex_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) intr1 = mhl_tx_readb(ctx, MHL_TX_INTR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) intr4 = mhl_tx_readb(ctx, MHL_TX_INTR4_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) intr1_en = mhl_tx_readb(ctx, MHL_TX_INTR1_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) intr4_en = mhl_tx_readb(ctx, MHL_TX_INTR4_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cbus_intr1 = cbus_readb(ctx, CBUS_INT_STATUS_1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) cbus_intr2 = cbus_readb(ctx, CBUS_INT_STATUS_2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (sii9234_clear_error(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_dbg(ctx->dev, "irq %02x/%02x %02x/%02x %02x/%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) intr1, intr1_en, intr4, intr4_en, cbus_intr1, cbus_intr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (intr4 & RGND_READY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ctx->state = sii9234_rgnd_ready_irq(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (intr1 & RSEN_CHANGE_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ctx->state = sii9234_rsen_change(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (intr4 & MHL_EST_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ctx->state = sii9234_mhl_established(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (intr1 & HPD_CHANGE_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ctx->state = sii9234_hpd_change(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (intr4 & CBUS_LKOUT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ctx->state = ST_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (intr4 & MHL_DISC_FAIL_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ctx->state = ST_FAILURE_DISCOVERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Clean interrupt status and pending flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mhl_tx_writeb(ctx, MHL_TX_INTR1_REG, intr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mhl_tx_writeb(ctx, MHL_TX_INTR4_REG, intr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sii9234_clear_error(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ctx->state == ST_FAILURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_dbg(ctx->dev, "try to reset after failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sii9234_hw_reset(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) sii9234_goto_d3(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ctx->state == ST_FAILURE_DISCOVERY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(ctx->dev, "discovery failed, no power for MHL?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ctx->state = ST_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int sii9234_init_resources(struct sii9234 *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!ctx->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(ctx->dev, "not DT device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ctx->gpio_reset = devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (IS_ERR(ctx->gpio_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(ctx->dev, "failed to get reset gpio from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return PTR_ERR(ctx->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ctx->supplies[0].supply = "avcc12";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ctx->supplies[1].supply = "avcc33";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ctx->supplies[2].supply = "iovcc18";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ctx->supplies[3].supply = "cvcc12";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = devm_regulator_bulk_get(ctx->dev, 4, ctx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(ctx->dev, "regulator_bulk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ctx->client[I2C_MHL] = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ctx->client[I2C_TPI] = devm_i2c_new_dummy_device(&client->dev, adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) I2C_TPI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (IS_ERR(ctx->client[I2C_TPI])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(ctx->dev, "failed to create TPI client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return PTR_ERR(ctx->client[I2C_TPI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ctx->client[I2C_HDMI] = devm_i2c_new_dummy_device(&client->dev, adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) I2C_HDMI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ERR(ctx->client[I2C_HDMI])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(ctx->dev, "failed to create HDMI RX client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return PTR_ERR(ctx->client[I2C_HDMI]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ctx->client[I2C_CBUS] = devm_i2c_new_dummy_device(&client->dev, adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) I2C_CBUS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (IS_ERR(ctx->client[I2C_CBUS])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(ctx->dev, "failed to create CBUS client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return PTR_ERR(ctx->client[I2C_CBUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static inline struct sii9234 *bridge_to_sii9234(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return container_of(bridge, struct sii9234, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static enum drm_mode_status sii9234_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (mode->clock > MHL1_MAX_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const struct drm_bridge_funcs sii9234_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .mode_valid = sii9234_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int sii9234_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct sii9234 *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mutex_init(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_err(dev, "I2C adapter lacks SMBUS feature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_err(dev, "no irq provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sii9234_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "sii9234", ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(dev, "failed to install IRQ handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = sii9234_init_resources(ctx, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) i2c_set_clientdata(client, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ctx->bridge.funcs = &sii9234_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ctx->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) drm_bridge_add(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) sii9234_cable_in(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int sii9234_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct sii9234 *ctx = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) sii9234_cable_out(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) drm_bridge_remove(&ctx->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct of_device_id sii9234_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { .compatible = "sil,sii9234" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_DEVICE_TABLE(of, sii9234_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct i2c_device_id sii9234_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { "SII9234", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) MODULE_DEVICE_TABLE(i2c, sii9234_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static struct i2c_driver sii9234_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "sii9234",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .of_match_table = sii9234_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = sii9234_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .remove = sii9234_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .id_table = sii9234_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) module_i2c_driver(sii9234_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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