^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Algea Cao <algea.cao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/rk630.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_crtc_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../rockchip/rockchip_drm_drv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct drm_display_mode rk630_tve_mode[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 816, 864, 0, 576, 580, 586, 625, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 815, 858, 0, 480, 483, 489, 525, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct rk630_tve {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct drm_encoder *encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct regmap *tvemap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct rk630 *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int is_4x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct rockchip_drm_sub_dev sub_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CVBS_NTSC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CVBS_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct env_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct env_config ntsc_bt656_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { BT656_DECODER_CTRL, 0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { BT656_DECODER_CROP, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { BT656_DECODER_SIZE, 0x01e002d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { BT656_DECODER_HTOTAL_HS_END, 0x035a003e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { BT656_DECODER_VACT_ST_HACT_ST, 0x00150069 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { BT656_DECODER_VS_ST_END_F1, 0x01060109 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { BT656_DECODER_DBG_REG, 0x024002d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct env_config ntsc_tve_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { TVE_MODE_CTRL, 0x000af906 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { TVE_HOR_TIMING1, 0x00c07a81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { TVE_HOR_TIMING2, 0x169810fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { TVE_HOR_TIMING3, 0x96b40000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { TVE_SUB_CAR_FRQ, 0x21f07bd7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { TVE_LUMA_FILTER1, 0x000a0ffa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { TVE_LUMA_FILTER2, 0x0ff4001a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { TVE_LUMA_FILTER3, 0x00110fd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { TVE_LUMA_FILTER4, 0x0fe80051 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { TVE_LUMA_FILTER5, 0x001a0f74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { TVE_LUMA_FILTER6, 0x0fe600ec },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { TVE_LUMA_FILTER7, 0x0ffa0e43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { TVE_LUMA_FILTER8, 0x08200527 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { TVE_IMAGE_POSITION, 0x001500d6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { TVE_ROUTING, 0x10088880 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { TVE_SYNC_ADJUST, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { TVE_STATUS, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { TVE_CTRL, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { TVE_INTR_STATUS, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { TVE_INTR_EN, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { TVE_INTR_CLR, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { TVE_COLOR_BUSRT_SAT, 0x0052543c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { TVE_CHROMA_BANDWIDTH, 0x00000002 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { TVE_BRIGHTNESS_CONTRAST, 0x00008300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { TVE_ID, 0x0a010000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { TVE_REVISION, 0x00010108 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { TVE_CLAMP, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct env_config pal_bt656_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { BT656_DECODER_CTRL, 0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { BT656_DECODER_CROP, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { BT656_DECODER_SIZE, 0x024002d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { BT656_DECODER_HTOTAL_HS_END, 0x0360003f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { BT656_DECODER_VTOTAL_VS_END, 0x02710003 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { BT656_DECODER_VS_ST_END_F1, 0x0138013b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { BT656_DECODER_DBG_REG, 0x024002d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct env_config pal_tve_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { TVE_MODE_CTRL, 0x010ab906 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { TVE_HOR_TIMING1, 0x00c28381 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { TVE_HOR_TIMING2, 0x267d111d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { TVE_HOR_TIMING3, 0x76c00880 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { TVE_SUB_CAR_FRQ, 0x2a098acb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { TVE_LUMA_FILTER1, 0x000a0ffa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { TVE_LUMA_FILTER2, 0x0ff4001a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { TVE_LUMA_FILTER3, 0x00110fd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { TVE_LUMA_FILTER4, 0x0fe80051 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { TVE_LUMA_FILTER5, 0x001a0f74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { TVE_LUMA_FILTER6, 0x0fe600ec },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { TVE_LUMA_FILTER7, 0x0ffa0e43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { TVE_LUMA_FILTER8, 0x08200527 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { TVE_IMAGE_POSITION, 0x001500f6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { TVE_ROUTING, 0x1000088a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { TVE_SYNC_ADJUST, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { TVE_STATUS, 0x000000b0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { TVE_CTRL, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { TVE_INTR_STATUS, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { TVE_INTR_EN, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { TVE_INTR_CLR, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { TVE_COLOR_BUSRT_SAT, 0x002e553c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { TVE_CHROMA_BANDWIDTH, 0x00000022 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { TVE_BRIGHTNESS_CONTRAST, 0x00008900 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { TVE_ID, 0x0a010000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { TVE_REVISION, 0x00010108 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { TVE_CLAMP, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct regmap_range rk630_tve_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_reg_range(BT656_DECODER_CTRL, BT656_DECODER_DBG_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regmap_reg_range(TVE_MODE_CTRL, TVE_ROUTING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) regmap_reg_range(TVE_SYNC_ADJUST, TVE_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) regmap_reg_range(TVE_CTRL, TVE_COLOR_BUSRT_SAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) regmap_reg_range(TVE_CHROMA_BANDWIDTH, TVE_BRIGHTNESS_CONTRAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) regmap_reg_range(TVE_ID, TVE_CLAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regmap_access_table rk630_tve_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .yes_ranges = rk630_tve_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .n_yes_ranges = ARRAY_SIZE(rk630_tve_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const struct regmap_config rk630_tve_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "tve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .max_register = TVE_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .val_format_endian = REGMAP_ENDIAN_NATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .rd_table = &rk630_tve_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXPORT_SYMBOL_GPL(rk630_tve_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct rk630_tve *bridge_to_tve(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return container_of(bridge, struct rk630_tve, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct rk630_tve *connector_to_tve(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return container_of(connector, struct rk630_tve, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int rk630_tve_write_block(struct rk630_tve *tve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct env_config *config, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = regmap_write(tve->tvemap, config[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) config[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int rk630_tve_cfg_set(struct rk630_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct env_config *bt656_cfg, *tve_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (tve->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case CVBS_PAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(tve->dev, "rk630 PAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bt656_cfg = pal_bt656_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tve_cfg = pal_tve_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case CVBS_NTSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(tve->dev, "rk630 NTSC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bt656_cfg = ntsc_bt656_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tve_cfg = ntsc_tve_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_dbg(tve->dev, "mode select err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = rk630_tve_write_block(tve, bt656_cfg, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(tve->dev, "rk630 bt656 write err!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (tve->mode == CVBS_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SW_TVE_DCLK_POL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SW_TVE_DCLK_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SW_DCLK_UPSAMPLE_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SW_TVE_MODE_MASK | SW_TVE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SW_DCLK_UPSAMPLE_EN(tve->is_4x) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SW_TVE_MODE(1) | SW_TVE_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SW_TVE_DCLK_POL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SW_TVE_DCLK_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SW_DCLK_UPSAMPLE_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SW_TVE_MODE_MASK | SW_TVE_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SW_DCLK_UPSAMPLE_EN(tve->is_4x) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SW_TVE_MODE(0) | SW_TVE_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = rk630_tve_write_block(tve, tve_cfg, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(tve->dev, "rk630 tve write err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int rk630_tve_disable(struct rk630_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) VDAC_ENDAC0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int rk630_tve_enable(struct rk630_tve *tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_dbg(tve->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* config bt656 input gpio*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_write(tve->grf, PLUMAGE_GRF_GPIO0A_IOMUX, 0x55555555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, GPIO0B0_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GPIO0B0_SEL(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) VDAC_ENDAC0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = rk630_tve_cfg_set(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*config clk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!tve->is_4x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CLK_SPLL_MODE(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PLLPD0(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CLK_SPLL_MODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PLLPD0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_read(tve->cru, CRU_SPLL_CON1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (val & PLL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(tve->dev, "rk630 pll locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!(val & PLL_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(tve->dev, "rk630 pll unlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* enable vdac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) VDAC_ENVBG_MASK | VDAC_ENDAC0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) VDAC_ENVBG(1) | VDAC_ENDAC0(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rk630_tve_mode_valid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rk630_tve_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 bus_format = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct rk630_tve *tve = connector_to_tve(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (count = 0; count < ARRAY_SIZE(rk630_tve_mode); count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct drm_display_mode *mode_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mode_ptr = drm_mode_duplicate(connector->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &rk630_tve_mode[count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!mode_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_err(tve->dev, "mode duplicate failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) drm_mode_probed_add(connector, mode_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) drm_display_info_set_bus_formats(&connector->display_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &bus_format, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rk630_tve_connector_detect(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return connector_status_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct drm_encoder *rk630_tve_best_encoder(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct rk630_tve *tve = connector_to_tve(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return tve->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) const struct drm_connector_helper_funcs rk630_tve_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .get_modes = rk630_tve_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .mode_valid = rk630_tve_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .best_encoder = rk630_tve_best_encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct drm_connector_funcs rk630_tve_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .detect = rk630_tve_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rk630_tve_bridge_mode_set(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct rk630_tve *tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tve = bridge_to_tve(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (adjusted_mode->vdisplay == 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tve->mode = CVBS_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tve->mode = CVBS_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void rk630_tve_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct rk630_tve *tve = bridge_to_tve(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(tve->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = rk630_tve_enable(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(tve->dev, "rk630 enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void rk630_tve_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct rk630_tve *tve = bridge_to_tve(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_dbg(tve->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rk630_tve_disable(tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int rk630_tve_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct rk630_tve *tve = bridge_to_tve(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!bridge->encoder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(tve->dev, "Parent encoder object not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tve->encoder = bridge->encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = drm_connector_init(bridge->dev, &tve->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &rk630_tve_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DRM_MODE_CONNECTOR_TV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(tve->dev, "Failed to initialize connector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) drm_connector_helper_add(&tve->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &rk630_tve_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = drm_connector_attach_encoder(&tve->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(tve->dev, "rk630 attach failed ret:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tve->sub_dev.connector = &tve->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tve->sub_dev.of_node = tve->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rockchip_drm_register_sub_dev(&tve->sub_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tve->connector.interlace_allowed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void rk1000_bridge_detach(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct rk630_tve *tve = bridge_to_tve(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rockchip_drm_unregister_sub_dev(&tve->sub_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct drm_bridge_funcs rk630_tve_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .enable = rk630_tve_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .disable = rk630_tve_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mode_set = rk630_tve_bridge_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .attach = rk630_tve_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .detach = rk1000_bridge_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int rk630_tve_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct rk630 *rk630 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct rk630_tve *tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!of_device_is_available(dev->of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!tve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tve->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tve->parent = rk630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) platform_set_drvdata(pdev, tve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tve->grf = rk630->grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tve->cru = rk630->cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tve->tvemap = rk630->tve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!tve->grf | !tve->cru | !tve->tvemap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tve->mode = CVBS_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tve->bridge.funcs = &rk630_tve_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tve->bridge.of_node = tve->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) drm_bridge_add(&tve->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_dbg(tve->dev, "rk630 probe tve ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int rk630_tve_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct rk630_tve *tve = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) drm_bridge_remove(&tve->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct of_device_id rk630_tve_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .compatible = "rockchip,rk630-tve" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DEVICE_TABLE(of, rk630_tve_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct platform_driver rk630_tve_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "rk630-tve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .of_match_table = of_match_ptr(rk630_tve_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .probe = rk630_tve_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .remove = rk630_tve_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) module_platform_driver(rk630_tve_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_DESCRIPTION("ROCKCHIP rk630 TVE Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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