^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PAGE2_GPIO_H 0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PS_GPIO9 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PAGE2_I2C_BYPASS 0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_BYPASS_EN 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PAGE2_MCS_EN 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAGE3_SET_ADD 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VDO_CTL_ADD 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VDO_DIS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VDO_EN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DP_NUM_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * PS8640 uses multiple addresses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * page[0]: for DP control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * page[1]: for VIDEO Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * page[2]: for control top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * page[3]: for DSI Link Control1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * page[4]: for MIPI Phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * page[5]: for VPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * page[6]: for DSI Link Control2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * page[7]: for SPI ROM mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum page_addr_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PAGE0_DP_CNTL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PAGE1_VDO_BDG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PAGE2_TOP_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PAGE3_DSI_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PAGE4_MIPI_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PAGE5_VPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PAGE6_DSI_CNTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PAGE7_SPI_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MAX_DEVS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum ps8640_vdo_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DISABLE = VDO_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ENABLE = VDO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ps8640 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct i2c_client *page[MAX_DEVS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regulator_bulk_data supplies[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct gpio_desc *gpio_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool powered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return container_of(e, struct ps8640, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const enum ps8640_vdo_control ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) sizeof(vdo_ctrl_buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) vdo_ctrl_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DRM_ERROR("failed to %sable VDO: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ctrl == ENABLE ? "en" : "dis", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ps_bridge->powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ps_bridge->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DRM_ERROR("cannot enable regulators %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) gpiod_set_value(ps_bridge->gpio_powerdown, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gpiod_set_value(ps_bridge->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) usleep_range(2000, 2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gpiod_set_value(ps_bridge->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Wait for the ps8640 embedded MCU to be ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * First wait 200ms and then check the MCU ready flag every 20ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) timeout = jiffies + msecs_to_jiffies(200) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) while (time_is_after_jiffies(timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto err_regulators_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((status & PS_GPIO9) == PS_GPIO9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The Manufacturer Command Set (MCS) is a device dependent interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * intended for factory programming of the display module default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * parameters. Once the display module is configured, the MCS shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * disabled by the manufacturer. Once disabled, all MCS commands are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * ignored by the display interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto err_regulators_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) status & ~MCS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto err_regulators_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Switch access edp panel's edid through i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) I2C_BYPASS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err_regulators_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ps_bridge->powered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err_regulators_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ps_bridge->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!ps_bridge->powered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpiod_set_value(ps_bridge->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) gpiod_set_value(ps_bridge->gpio_powerdown, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ps_bridge->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DRM_ERROR("cannot disable regulators %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ps_bridge->powered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void ps8640_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ps8640_bridge_poweron(ps_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ps8640_bridge_poweroff(ps_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void ps8640_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ps8640_bridge_vdo_control(ps_bridge, DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ps8640_bridge_poweroff(ps_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int ps8640_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct device *dev = &ps_bridge->page[0]->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device_node *in_ep, *dsi_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mipi_dsi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct mipi_dsi_device_info info = { .type = "ps8640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .node = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* port@0 is ps8640 dsi input port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!in_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dsi_node = of_graph_get_remote_port_parent(in_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) of_node_put(in_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!dsi_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) host = of_find_mipi_dsi_host_by_node(dsi_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) of_node_put(dsi_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dsi = mipi_dsi_device_register_full(host, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (IS_ERR(dsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(dev, "failed to create dsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = PTR_ERR(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ps_bridge->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dsi->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dsi->lanes = DP_NUM_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Attach the panel-bridge to the dsi bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) &ps_bridge->bridge, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mipi_dsi_device_unregister(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bool poweroff = !ps_bridge->powered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * When we end calling get_edid() triggered by an ioctl, i.e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * drm_mode_getconnector (ioctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * -> drm_helper_probe_single_connector_modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * -> drm_bridge_connector_get_modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * -> ps8640_bridge_get_edid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * We need to make sure that what we need is enabled before reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * EDID, for this chip, we need to do a full poweron, otherwise it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) drm_bridge_chain_pre_enable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) edid = drm_get_edid(connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ps_bridge->page[PAGE0_DP_CNTL]->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * If we call the get_edid() function without having enabled the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * before, return the chip to its original power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) drm_bridge_chain_post_disable(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct drm_bridge_funcs ps8640_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .attach = ps8640_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .get_edid = ps8640_bridge_get_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .post_disable = ps8640_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .pre_enable = ps8640_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int ps8640_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct ps8640 *ps_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!ps_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* port@1 is ps8640 output port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (IS_ERR(ps_bridge->panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PTR_ERR(ps_bridge->panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ps_bridge->supplies[0].supply = "vdd33";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ps_bridge->supplies[1].supply = "vdd12";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ps_bridge->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (IS_ERR(ps_bridge->gpio_powerdown))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return PTR_ERR(ps_bridge->gpio_powerdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Assert the reset to avoid the bridge being initialized prematurely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (IS_ERR(ps_bridge->gpio_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return PTR_ERR(ps_bridge->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ps_bridge->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ps_bridge->page[PAGE0_DP_CNTL] = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) client->addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(ps_bridge->page[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(dev, "failed i2c dummy device, address %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) client->addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return PTR_ERR(ps_bridge->page[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i2c_set_clientdata(client, ps_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) drm_bridge_add(&ps_bridge->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int ps8640_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ps8640 *ps_bridge = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) drm_bridge_remove(&ps_bridge->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct of_device_id ps8640_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .compatible = "parade,ps8640" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_DEVICE_TABLE(of, ps8640_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct i2c_driver ps8640_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .probe_new = ps8640_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .remove = ps8640_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "ps8640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .of_match_table = ps8640_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) module_i2c_driver(ps8640_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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