^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Parade PS8622 eDP/LVDS bridge driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Brightness scale on the Parade chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PS8622_MAX_BRIGHTNESS 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Timings taken from the version 1.7 datasheet for the PS8622/PS8625 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PS8622_POWER_RISE_T1_MIN_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PS8622_POWER_RISE_T1_MAX_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PS8622_RST_HIGH_T2_MIN_US 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PS8622_RST_HIGH_T2_MAX_US 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PS8622_PWMO_END_T12_MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PS8622_POWER_FALL_T16_MAX_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PS8622_POWER_OFF_T17_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #if ((PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US) > \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #error "T2.min + T1.max must be less than T2.max + T1.min"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ps8622_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regulator *v12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct backlight_device *bl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gpio_desc *gpio_slp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct gpio_desc *gpio_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 max_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline struct ps8622_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bridge_to_ps8622(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return container_of(bridge, struct ps8622_bridge, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 data[] = {reg, val};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) msg.addr = client->addr + page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) msg.len = sizeof(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) msg.buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = i2c_transfer(adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pr_warn("PS8622 I2C write (0x%02x,0x%02x,0x%02x) failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) client->addr + page, reg, val, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return !(ret == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int ps8622_send_config(struct ps8622_bridge *ps8622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_client *cl = ps8622->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* HPD low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) err = ps8622_set(cl, 0x02, 0xa1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* SW setting: [1:0] SW output 1.2V voltage is lower to 96% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err = ps8622_set(cl, 0x04, 0x14, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err = ps8622_set(cl, 0x04, 0xe3, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* [7] RCO SS enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) err = ps8622_set(cl, 0x04, 0xe2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* RPHY Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * [3:2] CDR tune wait cycle before measure for fine tune
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * b00: 1us b01: 0.5us b10:2us, b11: 4us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err = ps8622_set(cl, 0x04, 0x8a, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* [3] RFD always on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = ps8622_set(cl, 0x04, 0x89, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* CTN lock in/out: 20000ppm/80000ppm. Lock out 2 times. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = ps8622_set(cl, 0x04, 0x71, 0x2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 2.7G CDR settings: NOF=40LSB for HBR CDR setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err = ps8622_set(cl, 0x04, 0x7d, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* [1:0] Fmin=+4bands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = ps8622_set(cl, 0x04, 0x7b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* [7:5] DCO_FTRNG=+-40% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) err = ps8622_set(cl, 0x04, 0x7a, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) err = ps8622_set(cl, 0x04, 0xc0, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Gitune=-37% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) err = ps8622_set(cl, 0x04, 0xc1, 0x92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Fbstep=100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) err = ps8622_set(cl, 0x04, 0xc2, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* [7] LOS signal disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) err = ps8622_set(cl, 0x04, 0x32, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* RPIO Setting: [7:4] LVDS driver bias current : 75% (250mV swing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) err = ps8622_set(cl, 0x04, 0x00, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* [7:6] Right-bar GPIO output strength is 8mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = ps8622_set(cl, 0x04, 0x15, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* EQ Training State Machine Setting, RCO calibration start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err = ps8622_set(cl, 0x04, 0x54, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Logic, needs more than 10 I2C command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* [4:0] MAX_LANE_COUNT set to max supported lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* [4:0] LANE_COUNT_SET set to chosen lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) err = ps8622_set(cl, 0x00, 0x52, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* HPD CP toggle enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err = ps8622_set(cl, 0x00, 0xf1, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = ps8622_set(cl, 0x00, 0x62, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Counter number, add 1ms counter delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) err = ps8622_set(cl, 0x00, 0xf6, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* [6]PWM function control by DPCD0040f[7], default is PWM block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) err = ps8622_set(cl, 0x00, 0x77, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 04h Adjust VTotal toleranceto fix the 30Hz no display issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) err = ps8622_set(cl, 0x00, 0x4c, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* DPCD00400='h00, Parade OUI ='h001cf8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) err = ps8622_set(cl, 0x01, 0xc0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* DPCD00401='h1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = ps8622_set(cl, 0x01, 0xc1, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* DPCD00402='hf8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err = ps8622_set(cl, 0x01, 0xc2, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* DPCD403~408 = ASCII code, D2SLV5='h4432534c5635 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err = ps8622_set(cl, 0x01, 0xc3, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* DPCD404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err = ps8622_set(cl, 0x01, 0xc4, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* DPCD405 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = ps8622_set(cl, 0x01, 0xc5, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* DPCD406 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) err = ps8622_set(cl, 0x01, 0xc6, 0x4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* DPCD407 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) err = ps8622_set(cl, 0x01, 0xc7, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* DPCD408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) err = ps8622_set(cl, 0x01, 0xc8, 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* DPCD40A, Initial Code major revision '01' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = ps8622_set(cl, 0x01, 0xca, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* DPCD40B, Initial Code minor revision '05' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = ps8622_set(cl, 0x01, 0xcb, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ps8622->bl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* DPCD720, internal PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err = ps8622_set(cl, 0x01, 0xa5, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* FFh for 100% brightness, 0h for 0% brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) err = ps8622_set(cl, 0x01, 0xa7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ps8622->bl->props.brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* DPCD720, external PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) err = ps8622_set(cl, 0x01, 0xa5, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Set LVDS output as 6bit-VESA mapping, single LVDS channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err = ps8622_set(cl, 0x01, 0xcc, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Enable SSC set by register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err = ps8622_set(cl, 0x02, 0xb1, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Set SSC enabled and +/-1% central spreading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) err = ps8622_set(cl, 0x04, 0x10, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Logic end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* MPU Clock source: LC => RCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err = ps8622_set(cl, 0x04, 0x59, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* LC -> RCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err = ps8622_set(cl, 0x04, 0x54, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* HPD high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err = ps8622_set(cl, 0x02, 0xa1, 0x91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return err ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int ps8622_backlight_update(struct backlight_device *bl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct ps8622_bridge *ps8622 = dev_get_drvdata(&bl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int ret, brightness = bl->props.brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (bl->props.power != FB_BLANK_UNBLANK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) brightness = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!ps8622->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = ps8622_set(ps8622->client, 0x01, 0xa7, brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct backlight_ops ps8622_backlight_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .update_status = ps8622_backlight_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void ps8622_pre_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ps8622->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) gpiod_set_value(ps8622->gpio_rst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ps8622->v12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = regulator_enable(ps8622->v12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DRM_ERROR("fails to enable ps8622->v12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) gpiod_set_value(ps8622->gpio_slp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * T1 is the range of time that it takes for the power to rise after we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * enable the lcd/ps8622 fet. T2 is the range of time in which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * data sheet specifies we should deassert the reset pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * If it takes T1.max for the power to rise, we need to wait atleast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * T2.min before deasserting the reset pin. If it takes T1.min for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * power to rise, we need to wait at most T2.max before deasserting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * reset pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) usleep_range(PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) gpiod_set_value(ps8622->gpio_rst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* wait 20ms after RST high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) usleep_range(20000, 30000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = ps8622_send_config(ps8622);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DRM_ERROR("Failed to send config to bridge (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ps8622->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void ps8622_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Delay after panel is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) msleep(PS8622_PWMO_END_T12_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void ps8622_post_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!ps8622->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ps8622->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * This doesn't matter if the regulators are turned off, but something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * else might keep them on. In that case, we want to assert the slp gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * to lower power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gpiod_set_value(ps8622->gpio_slp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ps8622->v12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regulator_disable(ps8622->v12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Sleep for at least the amount of time that it takes the power rail to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * fall to prevent asserting the rst gpio from doing anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) usleep_range(PS8622_POWER_FALL_T16_MAX_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 2 * PS8622_POWER_FALL_T16_MAX_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gpiod_set_value(ps8622->gpio_rst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) msleep(PS8622_POWER_OFF_T17_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int ps8622_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return drm_bridge_attach(ps8622->bridge.encoder, ps8622->panel_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &ps8622->bridge, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct drm_bridge_funcs ps8622_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pre_enable = ps8622_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .disable = ps8622_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .post_disable = ps8622_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .attach = ps8622_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct of_device_id ps8622_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {.compatible = "parade,ps8622",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {.compatible = "parade,ps8625",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DEVICE_TABLE(of, ps8622_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int ps8622_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct ps8622_bridge *ps8622;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ps8622 = devm_kzalloc(dev, sizeof(*ps8622), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!ps8622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) panel_bridge = devm_drm_panel_bridge_add(dev, panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (IS_ERR(panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return PTR_ERR(panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ps8622->panel_bridge = panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ps8622->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ps8622->v12 = devm_regulator_get(dev, "vdd12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(ps8622->v12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_info(dev, "no 1.2v regulator found for PS8622\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ps8622->v12 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ps8622->gpio_slp = devm_gpiod_get(dev, "sleep", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (IS_ERR(ps8622->gpio_slp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = PTR_ERR(ps8622->gpio_slp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(dev, "cannot get gpio_slp %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Assert the reset pin high to avoid the bridge being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * initialized prematurely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ps8622->gpio_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (IS_ERR(ps8622->gpio_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = PTR_ERR(ps8622->gpio_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "cannot get gpio_rst %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ps8622->max_lane_count = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (of_property_read_u32(dev->of_node, "lane-count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &ps8622->lane_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ps8622->lane_count = ps8622->max_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else if (ps8622->lane_count > ps8622->max_lane_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_info(dev, "lane-count property is too high,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "using max_lane_count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ps8622->lane_count = ps8622->max_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!of_find_property(dev->of_node, "use-external-pwm", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ps8622->bl = backlight_device_register("ps8622-backlight",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev, ps8622, &ps8622_backlight_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_ERR(ps8622->bl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DRM_ERROR("failed to register backlight\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = PTR_ERR(ps8622->bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ps8622->bl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ps8622->bl->props.max_brightness = PS8622_MAX_BRIGHTNESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ps8622->bl->props.brightness = PS8622_MAX_BRIGHTNESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ps8622->bridge.funcs = &ps8622_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ps8622->bridge.type = DRM_MODE_CONNECTOR_LVDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ps8622->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) drm_bridge_add(&ps8622->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) i2c_set_clientdata(client, ps8622);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int ps8622_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ps8622_bridge *ps8622 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) backlight_device_unregister(ps8622->bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) drm_bridge_remove(&ps8622->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct i2c_device_id ps8622_i2c_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Device type, max_lane_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {"ps8622", 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {"ps8625", 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_DEVICE_TABLE(i2c, ps8622_i2c_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct i2c_driver ps8622_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .id_table = ps8622_i2c_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .probe = ps8622_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .remove = ps8622_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "ps8622",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .of_match_table = ps8622_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) module_i2c_driver(ps8622_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_AUTHOR("Vincent Palatin <vpalatin@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_DESCRIPTION("Parade ps8622/ps8625 eDP-LVDS converter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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