^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NWL MIPI DSI host driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Purism SPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __NWL_DSI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __NWL_DSI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* DSI HOST registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NWL_DSI_CFG_NUM_LANES 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NWL_DSI_CFG_T_PRE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NWL_DSI_CFG_T_POST 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NWL_DSI_CFG_TX_GAP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NWL_DSI_CFG_TWAKEUP 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NWL_DSI_CFG_STATUS_OUT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NWL_DSI_RX_ERROR_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* DSI DPI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NWL_DSI_PIXEL_PAYLOAD_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NWL_DSI_PIXEL_FIFO_SEND_LEVEL 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NWL_DSI_INTERFACE_COLOR_CODING 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NWL_DSI_PIXEL_FORMAT 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NWL_DSI_VSYNC_POLARITY 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NWL_DSI_HSYNC_POLARITY 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NWL_DSI_VIDEO_MODE 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NWL_DSI_HFP 0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NWL_DSI_HBP 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NWL_DSI_HSA 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NWL_DSI_ENABLE_MULT_PKTS 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NWL_DSI_VBP 0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NWL_DSI_VFP 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NWL_DSI_BLLP_MODE 0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NWL_DSI_USE_NULL_PKT_BLLP 0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NWL_DSI_VACTIVE 0x23c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NWL_DSI_VC 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* DSI APB PKT control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NWL_DSI_TX_PAYLOAD 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NWL_DSI_PKT_CONTROL 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NWL_DSI_SEND_PACKET 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NWL_DSI_PKT_STATUS 0x28c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NWL_DSI_PKT_FIFO_WR_LEVEL 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NWL_DSI_PKT_FIFO_RD_LEVEL 0x294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NWL_DSI_RX_PAYLOAD 0x298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NWL_DSI_RX_PKT_HEADER 0x29c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* DSI IRQ handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NWL_DSI_IRQ_STATUS 0x2a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NWL_DSI_SM_NOT_IDLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NWL_DSI_TX_PKT_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define NWL_DSI_DPHY_DIRECTION BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NWL_DSI_TX_FIFO_OVFLW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NWL_DSI_TX_FIFO_UDFLW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NWL_DSI_RX_FIFO_OVFLW BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NWL_DSI_RX_FIFO_UDFLW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NWL_DSI_RX_PKT_HDR_RCVD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NWL_DSI_BTA_TIMEOUT BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NWL_DSI_LP_RX_TIMEOUT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NWL_DSI_HS_TX_TIMEOUT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NWL_DSI_IRQ_STATUS2 0x2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NWL_DSI_SINGLE_BIT_ECC_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NWL_DSI_MULTI_BIT_ECC_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NWL_DSI_CRC_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NWL_DSI_IRQ_MASK 0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NWL_DSI_SM_NOT_IDLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NWL_DSI_TX_PKT_DONE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NWL_DSI_DPHY_DIRECTION_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NWL_DSI_TX_FIFO_OVFLW_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NWL_DSI_TX_FIFO_UDFLW_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NWL_DSI_RX_FIFO_OVFLW_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NWL_DSI_RX_FIFO_UDFLW_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NWL_DSI_RX_PKT_HDR_RCVD_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NWL_DSI_BTA_TIMEOUT_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NWL_DSI_LP_RX_TIMEOUT_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NWL_DSI_HS_TX_TIMEOUT_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NWL_DSI_IRQ_MASK2 0x2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NWL_DSI_MULTI_BIT_ECC_ERR_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NWL_DSI_CRC_ERR_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * PKT_CONTROL format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * [15: 0] - word count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * [17:16] - virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * [23:18] - data type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * [24] - LP or HS select (0 - LP, 1 - HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * [25] - perform BTA after packet is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * [26] - perform BTA only, no packet tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * RX_PKT_HEADER format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * [15: 0] - word count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * [21:16] - data type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * [23:22] - virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* DSI Video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NWL_DSI_VM_BURST_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* * DPI color coding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NWL_DSI_DPI_16_BIT_565_PACKED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NWL_DSI_DPI_16_BIT_565_ALIGNED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define NWL_DSI_DPI_16_BIT_565_SHIFTED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define NWL_DSI_DPI_18_BIT_PACKED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NWL_DSI_DPI_18_BIT_ALIGNED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NWL_DSI_DPI_24_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* * DPI Pixel format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define NWL_DSI_PIXEL_FORMAT_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define NWL_DSI_PIXEL_FORMAT_18 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NWL_DSI_PIXEL_FORMAT_18L BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NWL_DSI_PIXEL_FORMAT_24 (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* __NWL_DSI_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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