^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX8 NWL MIPI DSI host driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2020 Purism SPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mux/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/time64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <drm/drm_atomic_state_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "nwl-dsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_NAME "nwl-dsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* i.MX8 NWL quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* i.MX8MQ errata E11418 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define E11418_HS_MODE_QUIRK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum transfer_direction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DSI_PACKET_SEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DSI_PACKET_RECEIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NWL_DSI_ENDPOINT_LCDIF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NWL_DSI_ENDPOINT_DCSS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct nwl_dsi_plat_clk_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const char *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct nwl_dsi_transfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct mipi_dsi_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mipi_dsi_packet packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct completion completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int status; /* status of transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bool need_bta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 rx_word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) size_t tx_len; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) size_t rx_len; /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct nwl_dsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mipi_dsi_host dsi_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) union phy_configure_opts phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The DSI host controller needs this reset sequence according to NWL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 1. Deassert pclk reset to get access to DSI regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 2. Configure DSI Host and DPHY and enable DPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 3. Deassert ESC and BYTE resets to allow host TX operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 4. Send DSI cmds to configure peripheral (handled by panel drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 5. Deassert DPI reset so DPI receives pixels and starts sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * DSI data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * TODO: Since panel_bridges do their DSI setup in enable we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * currently have 4. and 5. swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct reset_control *rst_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct reset_control *rst_esc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct reset_control *rst_dpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct reset_control *rst_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct mux_control *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* DSI clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *phy_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *rx_esc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk *tx_esc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * hardware bug: the i.MX8MQ needs this clock on during reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * even when not using LCDIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk *lcdif_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* dsi lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum mipi_dsi_pixel_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long dsi_mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct nwl_dsi_transfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct regmap_config nwl_dsi_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .max_register = NWL_DSI_IRQ_MASK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return container_of(bridge, struct nwl_dsi, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret = dsi->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dsi->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (dsi->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = regmap_write(dsi->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "Failed to write NWL DSI reg 0x%x: %d\n", reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dsi->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (dsi->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = regmap_read(dsi->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dsi->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return NWL_DSI_PIXEL_FORMAT_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return NWL_DSI_PIXEL_FORMAT_18L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case MIPI_DSI_FMT_RGB666_PACKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return NWL_DSI_PIXEL_FORMAT_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return NWL_DSI_PIXEL_FORMAT_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * ps2bc - Picoseconds to byte clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dsi->lanes * 8ULL * NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * ui2bc - UI time periods to byte clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return DIV64_U64_ROUND_UP(ui * dsi->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dsi->mode.clock * 1000 * bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * us2bc - micro seconds to lp clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static u32 us2lp(u32 lp_clk_rate, unsigned long us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int nwl_dsi_config_host(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (dsi->lanes < 1 || dsi->lanes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* values in byte clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cycles = ui2bc(dsi, cfg->clk_pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cycles += ui2bc(dsi, cfg->clk_pre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cycles = ps2bc(dsi, cfg->hs_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* In LP clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return nwl_dsi_clear_error(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int color_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bool burst_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int hfront_porch, hback_porch, vfront_porch, vback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int hsync_len, vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (color_format < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return color_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Adjusting input polarity based on the video mode results in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * a black screen so always pick active low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (burst_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dsi->mode.hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return nwl_dsi_clear_error(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) NWL_DSI_RX_PKT_HDR_RCVD_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) NWL_DSI_TX_FIFO_OVFLW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) NWL_DSI_HS_TX_TIMEOUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return nwl_dsi_clear_error(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct mipi_dsi_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) device->format, device->mode_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (device->lanes < 1 || device->lanes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dsi->lanes = device->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dsi->format = device->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dsi->dsi_mode_flags = device->mode_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct nwl_dsi_transfer *xfer = dsi->xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 *payload = xfer->msg->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) xfer->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (xfer->rx_word_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Get the RX header and parse it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) err = nwl_dsi_clear_error(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) xfer->status = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) word_count = NWL_DSI_WC(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) channel = NWL_DSI_RX_VC(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) data_type = NWL_DSI_RX_DT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (channel != xfer->msg->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DRM_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "[%02X] Channel mismatch (%u != %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) xfer->cmd, channel, xfer->msg->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) xfer->status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (data_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (xfer->msg->rx_len > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* read second byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) payload[1] = word_count >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ++xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (xfer->msg->rx_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* read first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) payload[0] = word_count & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ++xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) xfer->status = xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) word_count &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) xfer->cmd, word_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) xfer->status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (word_count > xfer->msg->rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DRM_DEV_ERROR(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "[%02X] Receive buffer too small: %zu (< %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) xfer->cmd, xfer->msg->rx_len, word_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) xfer->status = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) xfer->rx_word_count = word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Set word_count from previous header read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) word_count = xfer->rx_word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* If RX payload is not yet received, wait for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Read the RX payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) while (word_count >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) payload[0] = (val >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) payload[1] = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) payload[2] = (val >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) payload[3] = (val >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) payload += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) xfer->rx_len += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) word_count -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (word_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch (word_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) payload[2] = (val >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ++xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) payload[1] = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ++xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) payload[0] = (val >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ++xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) xfer->status = xfer->rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err = nwl_dsi_clear_error(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) xfer->status = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct nwl_dsi_transfer *xfer = dsi->xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bool end_packet = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (xfer->direction == DSI_PACKET_SEND &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) status & NWL_DSI_TX_PKT_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) xfer->status = xfer->tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) end_packet = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else if (status & NWL_DSI_DPHY_DIRECTION &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) end_packet = nwl_dsi_read_packet(dsi, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (end_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) complete(&xfer->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct nwl_dsi_transfer *xfer = dsi->xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct mipi_dsi_packet *pkt = &xfer->packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const u8 *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u16 word_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 hs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 hs_workaround = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Send the payload, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) length = pkt->payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) payload = pkt->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) while (length >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = *(u32 *)payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hs_workaround |= !(val & 0xFFFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) payload += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) length -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Send the rest of the payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) switch (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) val |= payload[2] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val |= payload[1] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hs_workaround |= !(val & 0xFFFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val |= payload[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) xfer->tx_len = pkt->payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * Send the header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * header[0] = Virtual Channel + Data Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * header[1] = Word Count LSB (LP) or first param (SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * header[2] = Word Count MSB (LP) or second param (SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) word_count = pkt->header[1] | (pkt->header[2] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DRM_DEV_DEBUG_DRIVER(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "Using hs mode workaround for cmd 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) xfer->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hs_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) NWL_DSI_BTA_TX(xfer->need_bta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Send packet command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const struct mipi_dsi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct nwl_dsi_transfer xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ssize_t ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Create packet to be sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dsi->xfer = &xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = mipi_dsi_create_packet(&xfer.packet, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dsi->xfer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msg->type & MIPI_DSI_DCS_READ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msg->rx_len > 0 && msg->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) xfer.direction = DSI_PACKET_RECEIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) xfer.direction = DSI_PACKET_SEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) xfer.msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) xfer.status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) xfer.rx_word_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) xfer.rx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) xfer.cmd = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (msg->tx_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) xfer.cmd = ((u8 *)(msg->tx_buf))[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) init_completion(&xfer.completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = clk_prepare_enable(dsi->rx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) clk_get_rate(dsi->rx_esc_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Initiate the DSI packet transmision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) nwl_dsi_begin_transmission(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!wait_for_completion_timeout(&xfer.completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) NWL_DSI_MIPI_FIFO_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) xfer.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = xfer.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) clk_disable_unprepare(dsi->rx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .attach = nwl_dsi_host_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .transfer = nwl_dsi_host_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct nwl_dsi *dsi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (irq_status & NWL_DSI_TX_PKT_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) nwl_dsi_finish_transmission(dsi, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int nwl_dsi_enable(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!dsi->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = phy_init(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = phy_configure(dsi->phy, phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto uninit_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = clk_prepare_enable(dsi->tx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto uninit_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) clk_get_rate(dsi->tx_esc_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = nwl_dsi_config_host(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto disable_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = nwl_dsi_config_dpi(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto disable_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = phy_power_on(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto disable_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = nwl_dsi_init_interrupts(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto power_off_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) power_off_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) phy_power_off(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) disable_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) clk_disable_unprepare(dsi->tx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) uninit_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) phy_exit(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int nwl_dsi_disable(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) phy_power_off(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) phy_exit(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Disabling the clock before the phy breaks enabling dsi again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_disable_unprepare(dsi->tx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) nwl_dsi_disable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = reset_control_assert(dsi->rst_dpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = reset_control_assert(dsi->rst_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = reset_control_assert(dsi->rst_esc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = reset_control_assert(dsi->rst_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) clk_disable_unprepare(dsi->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clk_disable_unprepare(dsi->lcdif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pm_runtime_put(dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) union phy_configure_opts *phy_opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (dsi->lanes < 1 || dsi->lanes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * So far the DPHY spec minimal timings work for both mixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * dphy and nwl dsi host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &phy_opts->mipi_dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rate = clk_get_rate(dsi->tx_esc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) phy_opts->mipi_dphy.lp_clk_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (mode->clock * bpp > 15000000 * dsi->lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (mode->clock * bpp < 80000 * dsi->lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return MODE_CLOCK_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct drm_bridge_state *bridge_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct drm_connector_state *conn_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* At least LCDIF + NWL needs active high sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Do a full modeset if crtc_state->active is changed to be true. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (crtc_state->active_changed && crtc_state->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) crtc_state->mode_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) const struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct device *dev = dsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) union phy_configure_opts new_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned long phy_ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * If hs clock is unchanged, we're all good - all parameters are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * derived from it atm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Save the new desired phy config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) drm_mode_debug_printmodeline(adjusted_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) nwl_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pm_runtime_get_sync(dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (clk_prepare_enable(dsi->lcdif_clk) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (clk_prepare_enable(dsi->core_clk) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Step 1 from DSI reset-out instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = reset_control_deassert(dsi->rst_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Step 2 from DSI reset-out instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) nwl_dsi_enable(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Step 3 from DSI reset-out instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = reset_control_deassert(dsi->rst_esc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ret = reset_control_deassert(dsi->rst_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Step 5 from DSI reset-out instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = reset_control_deassert(dsi->rst_dpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct drm_bridge *panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (panel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) panel_bridge = drm_panel_bridge_add(panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (IS_ERR(panel_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return PTR_ERR(panel_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dsi->panel_bridge = panel_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!dsi->panel_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { struct nwl_dsi *dsi = bridge_to_dsi(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .atomic_reset = drm_atomic_helper_bridge_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .atomic_check = nwl_dsi_bridge_atomic_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .atomic_pre_enable = nwl_dsi_bridge_atomic_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .atomic_enable = nwl_dsi_bridge_atomic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .atomic_disable = nwl_dsi_bridge_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .mode_set = nwl_dsi_bridge_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .mode_valid = nwl_dsi_bridge_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .attach = nwl_dsi_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .detach = nwl_dsi_bridge_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct platform_device *pdev = to_platform_device(dsi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dsi->phy = devm_phy_get(dsi->dev, "dphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (IS_ERR(dsi->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = PTR_ERR(dsi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) clk = devm_clk_get(dsi->dev, "lcdif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dsi->lcdif_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) clk = devm_clk_get(dsi->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dsi->core_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) clk = devm_clk_get(dsi->dev, "phy_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dsi->phy_ref_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clk = devm_clk_get(dsi->dev, "rx_esc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dsi->rx_esc_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) clk = devm_clk_get(dsi->dev, "tx_esc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dsi->tx_esc_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dsi->mux = devm_mux_control_get(dsi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (IS_ERR(dsi->mux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = PTR_ERR(dsi->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dsi->regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (IS_ERR(dsi->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = PTR_ERR(dsi->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dsi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (dsi->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dsi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return dsi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (IS_ERR(dsi->rst_pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PTR_ERR(dsi->rst_pclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return PTR_ERR(dsi->rst_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (IS_ERR(dsi->rst_byte)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PTR_ERR(dsi->rst_byte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return PTR_ERR(dsi->rst_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (IS_ERR(dsi->rst_esc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PTR_ERR(dsi->rst_esc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return PTR_ERR(dsi->rst_esc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (IS_ERR(dsi->rst_dpi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PTR_ERR(dsi->rst_dpi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return PTR_ERR(dsi->rst_dpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int nwl_dsi_select_input(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct device_node *remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 use_dcss = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) NWL_DSI_ENDPOINT_LCDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) use_dcss = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) NWL_DSI_ENDPOINT_DCSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!remote) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) DRM_DEV_ERROR(dsi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "No valid input endpoint found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) (use_dcss) ? "DCSS" : "LCDIF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = mux_control_try_select(dsi->mux, use_dcss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) of_node_put(remote);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = mux_control_deselect(dsi->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const struct drm_bridge_timings nwl_dsi_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const struct of_device_id nwl_dsi_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) { .compatible = "fsl,imx8mq-nwl-dsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) { .soc_id = "i.MX8MQ", .revision = "2.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .data = (void *)E11418_HS_MODE_QUIRK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) { /* sentinel. */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int nwl_dsi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) const struct soc_device_attribute *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct nwl_dsi *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (!dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dsi->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = nwl_dsi_parse_dt(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_name(dev), dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dsi->dsi_host.ops = &nwl_dsi_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dsi->dsi_host.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = mipi_dsi_host_register(&dsi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) attr = soc_device_match(nwl_dsi_quirks_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dsi->quirks = (uintptr_t)attr->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dsi->bridge.driver_private = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dsi->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dsi->bridge.timings = &nwl_dsi_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_set_drvdata(dev, dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = nwl_dsi_select_input(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mipi_dsi_host_unregister(&dsi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) drm_bridge_add(&dsi->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static int nwl_dsi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct nwl_dsi *dsi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) nwl_dsi_deselect_input(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mipi_dsi_host_unregister(&dsi->dsi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) drm_bridge_remove(&dsi->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static struct platform_driver nwl_dsi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .probe = nwl_dsi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .remove = nwl_dsi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .of_match_table = nwl_dsi_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) module_platform_driver(nwl_dsi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) MODULE_AUTHOR("NXP Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) MODULE_AUTHOR("Purism SPC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) MODULE_LICENSE("GPL"); /* GPLv2 or later */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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