^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim max96776 GMSL2 Deserializer with eDP Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/max96776.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum link_lane_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) USE_ONE_LINK = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) USE_TWO_LINK = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) USE_FOUR_LINK = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum link_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BW_1_62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) BW_2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BW_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct max96776_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct drm_bridge *next_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct max96776 *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct drm_dp_aux aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int max_link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum link_lane_count max_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct reg_sequence max96776_clk_ref[3][14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* 1.62Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0xe7b2, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 0xe7b3, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 0xe7b4, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 0xe7b5, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 0xe7b6, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 0xe7b7, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0xe7b8, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0xe7b9, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0xe7ba, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 0xe7bb, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0xe7bc, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0xe7bd, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0xe7be, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0xe7bf, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 2.7Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0xe7b2, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0xe7b3, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0xe7b4, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0xe7b5, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0xe7b6, 0x6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0xe7b7, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0xe7b8, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0xe7b9, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0xe7ba, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0xe7bb, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0xe7bc, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0xe7bd, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0xe7be, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0xe7bf, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* 5.4Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0xe7b2, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 0xe7b3, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0xe7b4, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0xe7b5, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0xe7b6, 0x6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0xe7b7, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0xe7b8, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0xe7b9, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0xe7ba, 0x2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0xe7bb, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0xe7bc, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0xe7bd, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0xe7be, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0xe7bf, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define to_max96776_bridge(x) container_of(x, struct max96776_bridge, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) max96776_dp_aux_dpcd_addr_sel(struct max96776_bridge *des, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg = AUX_ADDR_7_0(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_write(des->regmap, 0xe778, FIELD_PREP(USER_DATA1_B0, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg = AUX_ADDR_15_8(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_write(des->regmap, 0xe779, FIELD_PREP(USER_DATA1_B1, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Most significant four bits of DPCD register address when performing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * a twenty bit AUX read or write command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = AUX_ADDR_19_16(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regmap_write(des->regmap, 0xe77c, FIELD_PREP(USER_DATA3_B0, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static ssize_t max96776_dp_aux_transfer(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct drm_dp_aux_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct max96776_bridge *des = to_max96776_bridge(aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int num_transferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 *buffer = msg->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * as Spec if Burst data transfer is supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * The burst data size must be limited to a maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * of 16 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (WARN_ON(msg->size > 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Write AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * this command writes a DPCD register on the eDP/DP sink device. The register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * address is specified by the user in address 0xe778 and 0xe779. The data (a byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * to be written is specified in 0xe77a. The AUX channel must be configured prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * using the command(this occurs at power-up). The example below writes DPCD sink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * register 0x0100 with data 0x0a, To issue command, write the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 1. LSBs of write address: 0xe778 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 2. MSBs of write address: 0xe779 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 3. LSBs of data to write: 0xe77a 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * 4. command select: 0xe776 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 5. Execute command: 0xe777 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!(msg->request & DP_AUX_I2C_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < msg->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg = buffer[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_write(des->regmap, 0xe77a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FIELD_PREP(USER_DATA2_B0, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) regmap_update_bits(des->regmap, 0xe776, AUX_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FIELD_PREP(AUX_WRITE, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FIELD_PREP(RUN_COMMAND, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) num_transferred++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Read AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * this command read DPCD register on the eDP/DP sink device. The register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * address is specified by the user in address 0xe778 and 0xe779. Once the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * command has executed, the return data (a byte) is stored in 0xe77a. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * AUX channel must be configured prior to using the command(this occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * at power-up). The example, to read DPCD sink register 0x100 (main link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * bandwidth setting), write the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * 1. LSBs of write address: 0xe778 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * 2. MSBs of write address: 0xe779 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * 3. command select: 0xe776 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * 4. Execute command: 0xe777 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 5. LSBs of return value read: 0xe77a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (msg->request & DP_AUX_I2C_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (i = 0; i < msg->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) regmap_update_bits(des->regmap, 0xe776, AUX_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FIELD_PREP(AUX_READ, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FIELD_PREP(RUN_COMMAND, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regmap_read(des->regmap, 0xe77a, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) buffer[i] = (u8)reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) num_transferred++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) msg->reply = DP_AUX_I2C_REPLY_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return (num_transferred == msg->size) ? num_transferred : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int max96776_bridge_get_modes(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (des->next_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return drm_bridge_get_modes(des->next_bridge, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (des->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return drm_panel_get_modes(des->panel, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return drm_add_modes_noedid(connector, 1920, 1080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void max96776_edp_timing_config(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct drm_display_mode *mode = &des->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 hfp, hsa, hbp, hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 vact, vsa, vfp, vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 hwords, mvid, link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bool hsync_pol, vsync_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) vact = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vsa = mode->vsync_end - mode->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vfp = mode->vsync_start - mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vbp = mode->vtotal - mode->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hact = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hsa = mode->hsync_end - mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hfp = mode->hsync_start - mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) hbp = mode->htotal - mode->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) regmap_write(des->regmap, 0xe794, FIELD_PREP(HRES_B0, hact));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regmap_write(des->regmap, 0xe795, FIELD_PREP(HRES_B1, hact >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_write(des->regmap, 0xe796, FIELD_PREP(HFP_B0, hfp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regmap_write(des->regmap, 0xe797, FIELD_PREP(HFP_B1, hfp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regmap_write(des->regmap, 0xe798, FIELD_PREP(HSW_B0, hsa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) regmap_write(des->regmap, 0xe799, FIELD_PREP(HSW_B1, hsa >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) regmap_write(des->regmap, 0xe79a, FIELD_PREP(HBP_B0, hbp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regmap_write(des->regmap, 0xe79b, FIELD_PREP(HBP_B1, hbp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_write(des->regmap, 0xe79c, FIELD_PREP(VRES_B0, vact));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) regmap_write(des->regmap, 0xe79d, FIELD_PREP(VRES_B1, vact >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regmap_write(des->regmap, 0xe79e, FIELD_PREP(VFP_B0, vfp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_write(des->regmap, 0xe79f, FIELD_PREP(VFP_B1, vfp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regmap_write(des->regmap, 0xe7a0, FIELD_PREP(VSW_B0, vsa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regmap_write(des->regmap, 0xe7a1, FIELD_PREP(VSW_B1, vsa >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_write(des->regmap, 0xe7a2, FIELD_PREP(VBP_B0, vbp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regmap_write(des->regmap, 0xe7a3, FIELD_PREP(VBP_B1, vbp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regmap_update_bits(des->regmap, 0xe7ac, HSYNC_POL | VSYNC_POL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FIELD_PREP(HSYNC_POL, hsync_pol) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FIELD_PREP(VSYNC_POL, vsync_pol));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* NVID should always be set to 0x8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) regmap_write(des->regmap, 0xe7a8, FIELD_PREP(NVID_B0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regmap_write(des->regmap, 0xe7a9, FIELD_PREP(NVID_B1, 0x80));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* HWORDS = ((HRES x bits/pixel)/16) - LANE_COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - des->lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regmap_write(des->regmap, 0xe7a4, FIELD_PREP(HWORDS_B0, hwords));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_write(des->regmap, 0xe7a5, FIELD_PREP(HWORDS_B1, hwords >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* MVID = (PCLK x NVID) x 10 / Link Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) link_rate = drm_dp_bw_code_to_link_rate(des->link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768, link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) regmap_write(des->regmap, 0xe7a6, FIELD_PREP(HWORDS_B0, mvid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) regmap_write(des->regmap, 0xe7a7, FIELD_PREP(HWORDS_B1, mvid >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) regmap_write(des->regmap, 0xe7aa, FIELD_PREP(TUC_VALUE_B0, 0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regmap_write(des->regmap, 0xe7ab, FIELD_PREP(TUC_VALUE_B1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void max96776_get_edp_sink_max_lane_count(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * For DP rev.1.1, Maximum number of Main Link lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) drm_dp_dpcd_readb(&des->aux, DP_MAX_LANE_COUNT, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) des->lane_count = DPCD_MAX_LANE_COUNT(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void max96776_get_edp_sink_max_bw(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * For DP rev.1.1, Maximum link rate of Main Link lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * For DP rev.1.2, Maximum link rate of Main Link lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * For DP rev.1.4, Maximum link rate of Main Link lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 0x1e = 8.1 Gbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) drm_dp_dpcd_readb(&des->aux, DP_MAX_LINK_RATE, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) des->link_rate = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void max96776_edp_link_config(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) max96776_get_edp_sink_max_bw(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) max96776_get_edp_sink_max_lane_count(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if ((des->link_rate != DP_LINK_BW_1_62) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (des->link_rate != DP_LINK_BW_2_7) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) (des->link_rate != DP_LINK_BW_5_4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) (des->link_rate != DP_LINK_BW_8_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(des->dev, "Rx Max Link Rate is abnormal :%x !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) des->link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) des->link_rate = DP_LINK_BW_1_62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (des->lane_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(des->dev, "Rx Max Lane count is abnormal :%x !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) des->lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) des->lane_count = (u8)USE_ONE_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Setup TX lane count & rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (des->lane_count > (u8)des->max_lane_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) des->lane_count = (u8)des->max_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (des->link_rate > des->max_link_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) des->link_rate = des->max_link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regmap_write(des->regmap, 0xe790, FIELD_PREP(LINK_RATE, des->link_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) regmap_write(des->regmap, 0xe792, FIELD_PREP(LANE_COUNT, des->lane_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_info(des->dev, "final bandwidth: 0x%02x, lane count: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) des->link_rate, des->lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void max96776_edp_pll_config(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* provides control for eDP PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (des->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case DP_LINK_BW_5_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_5_4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ARRAY_SIZE(max96776_clk_ref[BW_5_4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case DP_LINK_BW_2_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_2_7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ARRAY_SIZE(max96776_clk_ref[BW_2_7]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case DP_LINK_BW_1_62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_1_62],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ARRAY_SIZE(max96776_clk_ref[BW_1_62]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void max96776_edp_full_training(struct max96776_bridge *des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 status[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) regmap_update_bits(des->regmap, 0xe776, RUN_LINK_TRAINING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FIELD_PREP(RUN_LINK_TRAINING, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FIELD_PREP(RUN_COMMAND, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = regmap_read_poll_timeout(des->regmap, 0x07f0, sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FIELD_PREP(TRAINING_SUCCESSFUL, sts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MSEC_PER_SEC, 200 * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(des->dev, "Link Training not successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) drm_dp_dpcd_read(&des->aux, DP_LANE0_1_STATUS, status, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_info(des->dev, "SINK LANE0_1_STATUS:0x%02x LANE2_3_STATUS:0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) status[0], status[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) max96776_bridge_atomic_pre_enable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 dpcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* disable HDCP 2.2 on eDP Deserializer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) regmap_update_bits(des->regmap, 0x1700, CMD_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FIELD_PREP(CMD_RESET, 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * This bit must be set to allow waiting for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * CMU to lock. It also should be set when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * SSC. Otherwise, a fixed wait time of 20μS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regmap_update_bits(des->regmap, 0xe7b0, SS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FIELD_PREP(SS_ENABLE, 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Determines whether spread spectrum clocking (SSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * is used with the DP sink device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) drm_dp_dpcd_readb(&des->aux, DP_MAX_DOWNSPREAD, &dpcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!!(dpcd & DP_MAX_DOWNSPREAD_0_5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regmap_update_bits(des->regmap, 0xe7b1, SSC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FIELD_PREP(SSC_ENABLE, 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) max96776_edp_link_config(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) max96776_edp_pll_config(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) max96776_edp_timing_config(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (des->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) drm_panel_prepare(des->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) max96776_bridge_atomic_enable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) max96776_edp_full_training(des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (des->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) drm_panel_enable(des->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) max96776_bridge_atomic_disable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (des->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) drm_panel_disable(des->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) max96776_bridge_atomic_post_disable(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct drm_bridge_state *old_bridge_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (des->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) drm_panel_unprepare(des->panel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int max96776_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &des->panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &des->next_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0 && ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (des->next_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return drm_bridge_attach(bridge->encoder, des->next_bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bridge, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void max96776_bridge_mode_set(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const struct drm_display_mode *adj_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) drm_mode_copy(&des->mode, adj_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static enum drm_connector_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) max96776_bridge_detect(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct max96776_bridge *des = to_max96776_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 hpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (regmap_read(des->regmap, 0x6230, &hpd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return connector_status_disconnected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!FIELD_PREP(HPD_PRESENT, hpd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return connector_status_disconnected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return connector_status_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct drm_bridge_funcs max96776_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .attach = max96776_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .detect = max96776_bridge_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .get_modes = max96776_bridge_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .atomic_pre_enable = max96776_bridge_atomic_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .atomic_post_disable = max96776_bridge_atomic_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .atomic_enable = max96776_bridge_atomic_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .atomic_disable = max96776_bridge_atomic_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .atomic_reset = drm_atomic_helper_bridge_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .mode_set = max96776_bridge_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int max96776_bridge_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct max96776_bridge *des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) des = devm_kzalloc(dev, sizeof(*des), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) des->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) des->parent = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) platform_set_drvdata(pdev, des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) des->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!des->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) des->max_link_rate = DP_LINK_BW_5_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) des->max_lane_count = USE_FOUR_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) des->aux.name = "DP-AUX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) des->aux.transfer = max96776_dp_aux_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) des->aux.dev = des->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = drm_dp_aux_register(&des->aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(dev, "failed to register dp aux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) des->bridge.funcs = &max96776_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) des->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) des->bridge.ops = DRM_BRIDGE_OP_MODES | DRM_BRIDGE_OP_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) des->bridge.type = DRM_MODE_CONNECTOR_eDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) drm_bridge_add(&des->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int max96776_bridge_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct max96776_bridge *des = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) drm_bridge_remove(&des->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct of_device_id max96776_bridge_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { .compatible = "maxim,max96776-bridge" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_DEVICE_TABLE(of, max96776_bridge_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct platform_driver max96776_bridge_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "max96776-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .of_match_table = max96776_bridge_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .probe = max96776_bridge_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .remove = max96776_bridge_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) module_platform_driver(max96776_bridge_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MODULE_DESCRIPTION("Maxim max96776 GMSL2 Deserializer with eDP Output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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