^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifdef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //#include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/extcon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <crypto/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_crtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <drm/drm_crtc_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <drm/drm_edid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <sound/hdmi-codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IT6161_PRINT(fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) _DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int ite_debug = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define it6161_debug(fmt, ...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ite_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) _DRM_PRINTK(, INFO, fmt, ##__VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Vendor option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AUDIO_SELECT I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUDIO_TYPE LPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUDIO_CHANNEL_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 0: Standard I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 1: 32bit I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_INPUT_FORMAT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 0: Left-justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 1: Right-justified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2S_JUSTIFIED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 0: Data delay 1T correspond to WS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 1: No data delay correspond to WS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2S_DATA_DELAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 0: Left channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 1: Right channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2S_WS_CHANNEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 0: MSB shift first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 1: LSB shift first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2S_DATA_SEQUENCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AUX_WAIT_TIMEOUT_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PIXEL_CLK_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PIXEL_CLK_INVERSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADJUST_PHASE_THRESHOLD 80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAX_PIXEL_CLK 95000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DEFAULT_DRV_HOLD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DEFAULT_PWR_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum hdmi_tx_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HDMI_TX_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) HDMI_TX_BY_PASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) HDMI_TX_ENABLE_DE_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) HDMI_TX_ENABLE_PATTERN_GENERATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum it6161_audio_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) I2S = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum it6161_audio_sample_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SAMPLE_RATE_24K = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SAMPLE_RATE_32K = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SAMPLE_RATE_48K = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SAMPLE_RATE_96K = 0xA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SAMPLE_RATE_192K = 0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SAMPLE_RATE_44_1K = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SAMPLE_RATE_88_2K = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SAMPLE_RATE_176_4K = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum it6161_audio_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LPCM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) NLPCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum it6161_audio_u32_length {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32_LENGTH_16BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32_LENGTH_18BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32_LENGTH_20BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32_LENGTH_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Audio Sample u32 Length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * u32_LENGTH_16BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * u32_LENGTH_18BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * u32_LENGTH_20BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * u32_LENGTH_24BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AUDIO_u32_LENGTH u32_LENGTH_24BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum it6161_active_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum dsi_data_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) RGB_24b = 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RGB_30b = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RGB_36b = 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RGB_18b = 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) RGB_18b_L = 0x2E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) YCbCr_16b = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) YCbCr_20b = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) YCbCr_24b = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #include "ite_it6161_hdmi_tx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #include "ite_it6161_mipi_rx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // for sample clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AUDFS_22p05KHz 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AUDFS_44p1KHz 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AUDFS_88p2KHz 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AUDFS_176p4KHz 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AUDFS_24KHz 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AUDFS_48KHz 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AUDFS_96KHz 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AUDFS_192KHz 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AUDFS_768KHz 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AUDFS_32KHz 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AUDFS_OTHER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ////////////////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) // HDMI VTable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ////////////////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static HDMI_VTiming const s_VMTable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 1,0,640,480,800,525,25175000L,0x89,16,96,48,10,2,33,PROG,Vneg,Hneg},//640x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 2,0,720,480,858,525,27000000L,0x80,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 3,0,720,480,858,525,27000000L,0x80,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 4,0,1280,720,1650,750,74250000L,0x2E,110,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 5,0,1920,540,2200,562,74250000L,0x2E,88,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 6,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 7,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 8,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 9,1,720,240,858,262,13500000L,0x100,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {10,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {11,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {12,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {13,2,720,240,858,262,54000000L,0x40,19,62,57,4,3,15,PROG,Vneg,Hneg},//720x480(I)@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {14,1,1440,480,1716,525,54000000L,0x40,32,124,120,9,6,30,PROG,Vneg,Hneg},//1440x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {15,1,1440,480,1716,525,54000000L,0x40,32,124,120,9,6,30,PROG,Vneg,Hneg},//1440x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {16,0,1920,1080,2200,1125,148500000L,0x17,88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {17,0,720,576,864,625,27000000L,0x80,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {18,0,720,576,864,625,27000000L,0x80,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {19,0,1280,720,1980,750,74250000L,0x2E,440,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {20,0,1920,540,2640,562,74250000L,0x2E,528,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {21,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {22,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {23,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {24,1,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {25,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {26,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {27,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {28,2,720,288,864,312,13500000L,0x100,12,63,69,2,3,19,PROG,Vneg,Hneg},//1440x288@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {29,1,1440,576,1728,625,54000000L,0x40,24,128,136,5,5,39,PROG,Vpos,Hneg},//1440x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {30,1,1440,576,1728,625,54000000L,0x40,24,128,136,5,5,39,PROG,Vpos,Hneg},//1440x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {31,0,1920,1080,2640,1125,148500000L,0x17,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {32,0,1920,1080,2750,1125,74250000L,0x2E,638,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@24Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {33,0,1920,1080,2640,1125,74250000L,0x2E,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@25Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {34,0,1920,1080,2200,1125,74250000L,0x2E,88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@30Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {35,2,2880,480,1716*2,525,108000000L,0x20,32*2,124*2,120*2,9,6,30,PROG,Vneg,Hneg},//2880x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {36,2,2880,480,1716*2,525,108000000L,0x20,32*2,124*2,120*2,9,6,30,PROG,Vneg,Hneg},//2880x480@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {37,1,2880,576,3456,625,108000000L,0x20,24*2,128*2,136*2,5,5,39,PROG,Vneg,Hneg},//2880x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {38,2,2880,576,3456,625,108000000L,0x20,24*2,128*2,136*2,5,5,39,PROG,Vneg,Hneg},//2880x576@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {39,0,1920,540,2304,625,72000000L,0x17,32,168,184,23,5,57,INTERLACE,Vneg,Hpos},//1920x1080@50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) // 100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {40,0,1920,540,2640,562,148500000L,0x17,528,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {41,0,1280,720,1980,750,148500000L,0x17,440,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {42,0,720,576,864,625, 54000000L,0x40,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {43,0,720,576,864,625, 54000000L,0x40,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {44,1,720,288,864,312, 27000000L,0x80,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {45,1,720,288,864,312, 27000000L,0x80,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) // 120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {46,0,1920,540,2200,562,148500000L,0x17,88,44,148,2,5,15,INTERLACE,Vpos,Hpos},//1920x1080(I)@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {47,0,1280,720,1650,750,148500000L,0x17,110,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {48,0, 720,480, 858,525, 54000000L,0x40,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {49,0, 720,480, 858,525, 54000000L,0x40,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {50,1, 720,240, 858,262, 27000000L,0x80,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {51,1, 720,240, 858,262, 27000000L,0x80,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) // 200Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {52,0,720,576,864,625,108000000L,0x20,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@200Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {53,0,720,576,864,625,108000000L,0x20,12,64,68,5,5,39,PROG,Vneg,Hneg},//720x576@200Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {54,1,720,288,864,312, 54000000L,0x40,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@200Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {55,1,720,288,864,312, 54000000L,0x40,12,63,69,2,3,19,INTERLACE,Vneg,Hneg},//1440x576(I)@200Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) // 240Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {56,0,720,480,858,525,108000000L,0x20,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {57,0,720,480,858,525,108000000L,0x20,16,62,60,9,6,30,PROG,Vneg,Hneg},//720x480@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {58,1,720,240,858,262, 54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {59,1,720,240,858,262, 54000000L,0x40,19,62,57,4,3,15,INTERLACE,Vneg,Hneg},//720x480(I)@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) // 720p low resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {60,0,1280, 720,3300, 750, 59400000L,0x3A,1760,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@24Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {61,0,1280, 720,3960, 750, 74250000L,0x2E,2420,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@25Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {62,0,1280, 720,3300, 750, 74250000L,0x2E,1760,40,220,5,5,20,PROG,Vpos,Hpos},//1280x720@30Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) // 1080p high refresh rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {63,0,1920,1080,2200,1125,297000000L,0x0B, 88,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@120Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {64,0,1920,1080,2640,1125,297000000L,0x0B,528,44,148,4,5,36,PROG,Vpos,Hpos},//1920x1080@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) // VESA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0,0,640,350,832,445,31500000L,0x6D,32,64,96,32,3,60,PROG,Vneg,Hpos},// 640x350@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0,0,640,400,832,445,31500000L,0x6D,32,64,96,1,3,41,PROG,Vneg,Hneg},// 640x400@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0,0,832,624,1152,667,57283000L,0x3C,32,64,224,1,3,39,PROG,Vneg,Hneg},// 832x624@75Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0,0,720,350,900,449,28322000L,0x7A,18,108,54,59,2,38,PROG,Vneg,Hneg},// 720x350@70Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0,0,720,400,900,449,28322000L,0x7A,18,108,54,13,2,34,PROG,Vpos,Hneg},// 720x400@70Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0,0,720,400,936,446,35500000L,0x61,36,72,108,1,3,42,PROG,Vpos,Hneg},// 720x400@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0,0,640,480,800,525,25175000L,0x89,16,96,48,10,2,33,PROG,Vneg,Hneg},// 640x480@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0,0,640,480,832,520,31500000L,0x6D,24,40,128,9,3,28,PROG,Vneg,Hneg},// 640x480@72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0,0,640,480,840,500,31500000L,0x6D,16,64,120,1,3,16,PROG,Vneg,Hneg},// 640x480@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0,0,640,480,832,509,36000000L,0x60,56,56,80,1,3,25,PROG,Vneg,Hneg},// 640x480@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0,0,800,600,1024,625,36000000L,0x60,24,72,128,1,2,22,PROG,Vpos,Hpos},// 800x600@56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0,0,800,600,1056,628,40000000L,0x56,40,128,88,1,4,23,PROG,Vpos,Hpos},// 800x600@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0,0,800,600,1040,666,50000000L,0x45,56,120,64,37,6,23,PROG,Vpos,Hpos},// 800x600@72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0,0,800,600,1056,625,49500000L,0x45,16,80,160,1,3,21,PROG,Vpos,Hpos},// 800x600@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0,0,800,600,1048,631,56250000L,0x3D,32,64,152,1,3,27,PROG,Vpos,Hpos},// 800X600@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0,0,848,480,1088,517,33750000L,0x66,16,112,112,6,8,23,PROG,Vpos,Hpos},// 840X480@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0,0,1024,384,1264,408,44900000L,0x4C,8,176,56,0,4,20,INTERLACE,Vpos,Hpos},//1024x768(I)@87Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0,0,1024,768,1344,806,65000000L,0x35,24,136,160,3,6,29,PROG,Vneg,Hneg},// 1024x768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0,0,1024,768,1328,806,75000000L,0x2E,24,136,144,3,6,29,PROG,Vneg,Hneg},// 1024x768@70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0,0,1024,768,1312,800,78750000L,0x2B,16,96,176,1,3,28,PROG,Vpos,Hpos},// 1024x768@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0,0,1024,768,1376,808,94500000L,0x24,48,96,208,1,3,36,PROG,Vpos,Hpos},// 1024x768@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0,0,1152,864,1600,900,108000000L,0x20,64,128,256,1,3,32,PROG,Vpos,Hpos},// 1152x864@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0,0,1280,768,1440,790,68250000L,0x32,48,32,80,3,7,12,PROG,Vneg,Hpos},// 1280x768@60-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0,0,1280,768,1664,798,79500000L,0x2B,64,128,192,3,7,20,PROG,Vpos,Hneg},// 1280x768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0,0,1280,768,1696,805,102250000L,0x21,80,128,208,3,7,27,PROG,Vpos,Hneg},// 1280x768@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0,0,1280,768,1712,809,117500000L,0x1D,80,136,216,3,7,31,PROG,Vpos,Hneg},// 1280x768@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0,0,1280,800,1440, 823, 71000000L,0x31, 48, 32, 80,3,6,14,PROG,Vpos,Hneg},// 1280x800@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0,0,1280,800,1680, 831, 83500000L,0x29, 72,128,200,3,6,22,PROG,Vpos,Hneg},// 1280x800@60Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0,0,1280,800,1696, 838,106500000L,0x20, 80,128,208,3,6,29,PROG,Vpos,Hneg},// 1280x800@75Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0,0,1280,800,1712, 843,122500000L,0x1C, 80,136,216,3,6,34,PROG,Vpos,Hneg},// 1280x800@85Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0,0,1280,960,1800,1000,108000000L,0x20,96,112,312,1,3,36,PROG,Vpos,Hpos},// 1280x960@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0,0,1280,960,1728,1011,148500000L,0x17,64,160,224,1,3,47,PROG,Vpos,Hpos},// 1280x960@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0,0,1280,1024,1688,1066,108000000L,0x20,48,112,248,1,3,38,PROG,Vpos,Hpos},// 1280x1024@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0,0,1280,1024,1688,1066,135000000L,0x19,16,144,248,1,3,38,PROG,Vpos,Hpos},// 1280x1024@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0,0,1280,1024,1728,1072,157500000L,0x15,64,160,224,1,3,44,PROG,Vpos,Hpos},// 1280X1024@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0,0,1360,768,1792,795,85500000L,0x28,64,112,256,3,6,18,PROG,Vpos,Hpos},// 1360X768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0,0,1366,768,1792,798,85500000L,0x28, 70,143,213,3,3,24,PROG,Vpos,Hpos},// 1366X768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0,0,1366,768,1500,800,72000000L,0x30, 14, 56, 64,1,3,28,PROG,Vpos,Hpos},// 1360X768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0,0,1400,1050,1560,1080,101000000L,0x22,48,32,80,3,4,23,PROG,Vneg,Hpos},// 1400x768@60-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0,0,1400,1050,1864,1089,121750000L,0x1C,88,144,232,3,4,32,PROG,Vpos,Hneg},// 1400x768@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0,0,1400,1050,1896,1099,156000000L,0x16,104,144,248,3,4,42,PROG,Vpos,Hneg},// 1400x1050@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0,0,1400,1050,1912,1105,179500000L,0x13,104,152,256,3,4,48,PROG,Vpos,Hneg},// 1400x1050@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0,0,1440,900,1600,926,88750000L,0x26,48,32,80,3,6,17,PROG,Vneg,Hpos},// 1440x900@60-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0,0,1440,900,1904,934,106500000L,0x20,80,152,232,3,6,25,PROG,Vpos,Hneg},// 1440x900@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0,0,1440,900,1936,942,136750000L,0x19,96,152,248,3,6,33,PROG,Vpos,Hneg},// 1440x900@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0,0,1440,900,1952,948,157000000L,0x16,104,152,256,3,6,39,PROG,Vpos,Hneg},// 1440x900@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0,0,1600,1200,2160,1250,162000000L,0x15,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0,0,1600,1200,2160,1250,175500000L,0x13,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0,0,1600,1200,2160,1250,189000000L,0x12,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0,0,1600,1200,2160,1250,202500000L,0x11,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0,0,1600,1200,2160,1250,229500000L,0x0F,64,192,304,1,3,46,PROG,Vpos,Hpos},// 1600x1200@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0,0,1680,1050,1840,1080,119000000L,0x1D,48,32,80,3,6,21,PROG,Vneg,Hpos},// 1680x1050@60-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0,0,1680,1050,2240,1089,146250000L,0x17,104,176,280,3,6,30,PROG,Vpos,Hneg},// 1680x1050@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0,0,1680,1050,2272,1099,187000000L,0x12,120,176,296,3,6,40,PROG,Vpos,Hneg},// 1680x1050@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0,0,1680,1050,2288,1105,214750000L,0x10,128,176,304,3,6,46,PROG,Vpos,Hneg},// 1680x1050@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0,0,1792,1344,2448,1394,204750000L,0x10,128,200,328,1,3,46,PROG,Vpos,Hneg},// 1792x1344@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0,0,1792,1344,2456,1417,261000000L,0x0D,96,216,352,1,3,69,PROG,Vpos,Hneg},// 1792x1344@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0,0,1856,1392,2528,1439,218250000L,0x0F,96,224,352,1,3,43,PROG,Vpos,Hneg},// 1856x1392@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0,0,1856,1392,2560,1500,288000000L,0x0C,128,224,352,1,3,104,PROG,Vpos,Hneg},// 1856x1392@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0,0,1920,1200,2080,1235,154000000L,0x16,48,32,80,3,6,26,PROG,Vneg,Hpos},// 1920x1200@60-R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0,0,1920,1200,2592,1245,193250000L,0x11,136,200,336,3,6,36,PROG,Vpos,Hneg},// 1920x1200@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0,0,1920,1200,2608,1255,245250000L,0x0E,136,208,344,3,6,46,PROG,Vpos,Hneg},// 1920x1200@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0,0,1920,1200,2624,1262,281250000L,0x0C,144,208,352,3,6,53,PROG,Vpos,Hneg},// 1920x1200@85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0,0,1920,1440,2600,1500,234000000L,0x0E,128,208,344,1,3,56,PROG,Vpos,Hneg},// 1920x1440@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0,0,1920,1440,2640,1500,297000000L,0x0B,144,224,352,1,3,56,PROG,Vpos,Hneg},// 1920x1440@75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DIFF(a,b) (((a)>(b))?((a)-(b)):((b)-(a)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static bool bChangeMode = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static unsigned char CommunBuff[128] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const u8 CA[] = { 0,0,0, 02, 0x3, 0x7, 0xB, 0xF, 0x1F } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static u32 VideoPixelClock ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static u8 pixelrep ; // no pixelrepeating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) // static HDMI_Aspec aspec ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) // static HDMI_Colorimetry Colorimetry ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static u32 ulAudioSampleFS = INPUT_SAMPLE_FREQ_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) // u8 bAudioSampleFreq = INPUT_SAMPLE_FREQ ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static u8 bOutputAudioChannel = OUTPUT_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static u8 bOutputAudioType=CNOFIG_INPUT_AUDIO_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MSCOUNT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define LOADING_UPDATE_TIMEOUT (3000/32) // 3sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static HDMITXDEV hdmiTxDev[HDMITX_MAX_DEV_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) //#define ENABLE_HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ENABLE_MIPI_RX_EXTERNAL_CLOCK false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MPLaneSwap FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MPPNSwap FALSE /* TRUE: MTK , FALSE: Solomon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MIPI_RX_LANE_COUNT 4 /* 1~4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OUTPUT_COLOR_MODE F_MODE_RGB444 /* F_MODE_YUV444, F_MODE_YUV422, F_MODE_RGB444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HDMI_TX_MODE HDMI_TX_ENABLE_DE_ONLY /* HDMI_TX_NONE, HDMI_TX_BY_PASS, HDMI_TX_ENABLE_DE_ONLY, HDMI_TX_ENABLE_PATTERN_GENERATOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define HDMI_TX_PATTERN_GENERATOR_FORMAT 16 /* support format 2, 4, 16*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define HDMI_TX_PATTERN_COLLOR_R 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define HDMI_TX_PATTERN_COLLOR_G 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define HDMI_TX_PATTERN_COLLOR_B 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* vendor option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define EOTPSel 0 /* LM option 0~15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define EnDeSkew TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PPIDbgSel 12/* 0~15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define RegIgnrNull 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define RegIgnrBlk 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define RegEnDummyECC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define LMDbgSel 0 /* 0~7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define EnContCK TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define HSSetNum 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define EnMBPM FALSE /* enable MIPI Bypass Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #if (EnMBPM == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PREC_Update TRUE//int PREC_Update = FALSE; // enable P-timing update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MREC_Update TRUE//int MREC_Update = FALSE; // enable M-timing update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EnTBPM TRUE /* enable HDMITX Bypass Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PREC_Update FALSE//int PREC_Update = FALSE; // enable P-timing update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MREC_Update FALSE//int MREC_Update = FALSE; // enable M-timing update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define EnTBPM FALSE /* enable HDMITX Bypass Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define REGSELDEF FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MPForceStb FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define EnHReSync FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define EnVReSync FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define EnFReSync FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define EnVREnh FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define EnVREnhSel 1 /* 0:Div2, 1:Div4, 2:Div8, 3:Div16, 4:Div32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define EnMAvg TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SkipStg 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SkipStg 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PDREFCLK FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PDREFCLK TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PDREFCNT 0 /* when PDREFCLK=TRUE, 0:div2, 1:div4, 2:div8, 3:divg16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define EnIntWakeU3 FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define EnIOIDDQ FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define EnStb2Rst FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define EnExtStdby FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define EnStandby FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MShift 4//int MShift = 5; // default: 0 //fmt2 fmt4 :4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PPSFFRdStg 0x04//int PPSFFRdStg = 0x10; //PPSFFRdStg(2:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define RegAutoSync TRUE//int RegAutoSync = TRUE;//add sync falling //pet:D0 20200211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MShift 5//int MShift = 5; // default: 0 //fmt2 fmt4 :4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PPSFFRdStg 0x10//int PPSFFRdStg = 0x10; //PPSFFRdStg(2:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif //#if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PShift 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define EnFFAutoRst TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define RegEnSyncErr FALSE//int RegEnSyncErr = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define EnTxCRC TRUE//int EnTxCRC = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TxCRCnum (0x20) //D0 20200211//(0x00)//TxCRCnum(6:0)//int TxCRCnum = 0x00; //TxCRCnum(6:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define InvMCLK TRUE //FALSE for solomon, if NonUFO, MCLK max = 140MHz with InvMCLK=TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define InvMCLK FALSE //FALSE for solomon, if NonUFO, MCLK max = 140MHz with InvMCLK=TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define InvPCLK FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #ifndef INV_INPUT_PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PCLKINV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PCLKINV B_TX_VDO_LATCH_EDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #ifndef INV_INPUT_ACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define InvAudCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define InvAudCLK B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) // #define INIT_CLK_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TxChSwap 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TxPNSwap 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define NRTXRCLK 1//int NRTXRCLK = true;//it6161b0 option true:set TRCLK by self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define RCLKFreqSel 1// int RCLKFreqSel = true; // false: 10MHz(div1), true : 20 MHz(OSSDIV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) // #ifdef REDUCE_HDMITX_SRC_JITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) // #define ForceTxCLKStb true// int ForceTxCLKStb = false; //true:define _hdmitx_jitter_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) // #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define ForceTxCLKStb true //20200220 C code set true-> false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) // #endif //#ifdef REDUCE_HDMITX_SRC_JITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const RegSetEntry HDMITX_Init_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x0F, 0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) //PLL Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x62, 0x08, 0x00}, // XP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x64, 0x04, 0x00}, // IP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0F, 0x01, 0x00}, // bank 0 ;3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #ifdef INIT_CLK_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x62, 0x90, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x64, 0x89, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x68, 0x10, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) // {0xD1, 0x0E, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) // {0x65, 0x03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) // #ifdef NON_SEQUENTIAL_YCBCR422 // for ITE HDMIRX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) // {0x71, 0xFC, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) // #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) // {0x71, 0xFC, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) // #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x8D, 0xFF, CEC_I2C_SLAVE_ADDR},//EnCEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) //{0x0F, 0x08, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0xA9, 0x80, (EnTBPM<<7)},// hdmitxset(0xa9, 0xc0, (EnTBPM<<7) + (EnTxPatMux<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0xBF, 0x80, (NRTXRCLK<<7)},//from c code hdmitxset(0xbf, 0x80, (NRTXRCLK<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) // Initial Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0xF8,0xFF,0xC3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0xF8,0xFF,0xA5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) //{0x05,0x1E,0x0C},//hdmitxset(0x05, 0x1E, (ForceRxOn<<4)+(RCLKPDSel<<2)+(RCLKPDEn<<1));ForceRxOn:F,RCLKPDSel=3,RCLKPDSel=false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0xF4,0x0C,0x00},//hdmitxset(0xF4, 0x0C, DDCSpeed<<2);//DDC75K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0xF3,0x02,0x00},//hdmitxset(0xF3, 0x02, ForceVOut<<1);//ForceVOut:false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) // {0x20, 0x80, 0x80},//TODO: check need or not?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) // {0x37, 0x01, 0x00},//TODO: check need or not?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) // {0x20, 0x80, 0x00},//TODO: check need or not?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0xF8,0xFF,0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x5A,0x0C,0x0C},//hdmitxset(0x5A, 0x0C, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0xD1,0x0A,((ForceTxCLKStb)<<3)+0x02},//hdmitxset(0xD1, 0x0A, (ForceTxCLKStb<<3)+0x02); // High Sensitivity , modified by junjie force "CLK_stable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x5D,0x04,((RCLKFreqSel)<<2)},//hdmitxset(0x5D, 0x04, (RCLKFreqSel<<2));//int RCLKFreqSel = true; // false: 10MHz(div1), true : 20 MHz(OSSDIV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x65,0x03,0x00},//hdmitxset(0x65, 0x03, RINGOSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x71,0xF9,((0<<6)+(0<<5)+(1<<4)+(1<<3)+0)},//hdmitxset(0x71, 0xF9, (XPStableTime<<6)+(EnXPLockChk<<5)+(EnPLLBufRst<<4)+(EnFFAutoRst<<3)+ EnFFManualRst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0xCF,0xFF,(0<<7)+(0<<6)+(0<<4)+(0<<2)+0},//hdmitxset(0xCF, 0xFF, (EnPktLimitGB<<7)+(EnPktBlankGB<<6)+(KeepOutGBSel<<4)+(PktLimitGBSel<<2)+PktBlankGBSel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0xd1,0x02,0x00},//hdmitxset(0xd1, 0x02, 0x00);//VidStbSen = false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) // 2014/01/07 HW Request for ROSC stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) // {0x5D,0x03,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) //~2014/01/07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) // #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) // {0x5A, 0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) // {0xE2, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) // #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x59, 0xD0, (((2-1)<<6)+(0<<4))},//hdmitxset(0x59, 0xD0, ((ManuallPR-1)<<6)+(DisLockPR<<4));ManuallPR=2, DisLockPR = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) // {0x59, 0xD8, 0x40|PCLKINV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #if((TxChSwap == 1) || (TxPNSwap == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x6b,0xC0,((TxChSwap<<7)+ (TxPNSwap<<6))},// hdmitxset(0x6b, 0xC0,(TxChSwap<<7)+ (TxPNSwap<<6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x61,0x40,0x40},// hdmitxset(0x61, 0x40,0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif //#if((TxChSwap ==true) || (TxPNSwap ==true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0xE1, 0x20, InvAudCLK},// Inverse Audio Latch Edge of IACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0xF5, 0x40, 0x00},//hdmitxset(0xF5,0x40,ForceTMDSStable<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x05, 0xC0, 0x40},// Setup INT Pin: Active Low & Open-Drain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) // {REG_TX_INT_MASK1, 0xFF, ~(B_TX_RXSEN_MASK|B_TX_HPD_MASK)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) // {REG_TX_INT_MASK2, 0xFF, ~(B_TX_KSVLISTCHK_MASK|B_TX_AUTH_DONE_MASK|B_TX_AUTH_FAIL_MASK)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) // {REG_TX_INT_MASK3, 0xFF, ~(B_TX_VIDSTABLE_MASK)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x0C, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x0D, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x0E, 0x03, 0x03},// Clear all Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x0C, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x0D, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x0E, 0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) //{0x09, 0x03, 0x00}, // Enable HPD and RxSen Interrupt//remove for interrupt mode allen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x20,0x01,0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const RegSetEntry HDMITX_DefaultVideo_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) // Config default output format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x72, 0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x70, 0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #ifndef DEFAULT_INPUT_YCBCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) // GenCSC\RGB2YUV_ITU709_16_235.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x72, 0xFF, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x73, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x74, 0xFF, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x75, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x76, 0xFF, 0xB8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x77, 0xFF, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x78, 0xFF, 0xB4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x79, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x7A, 0xFF, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x7B, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x7C, 0xFF, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x7D, 0xFF, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x7E, 0xFF, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x7F, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x80, 0xFF, 0x9F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x81, 0xFF, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x82, 0xFF, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x83, 0xFF, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x84, 0xFF, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x85, 0xFF, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x86, 0xFF, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x87, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) // GenCSC\YUV2RGB_ITU709_16_235.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x72, 0xFF, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x73, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x74, 0xFF, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x75, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x76, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x77, 0xFF, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x78, 0xFF, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x79, 0xFF, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x7A, 0xFF, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x7B, 0xFF, 0x3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x7C, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x7D, 0xFF, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x7E, 0xFF, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x7F, 0xFF, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x80, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x81, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x82, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x83, 0xFF, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x84, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x85, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x86, 0xFF, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x87, 0xFF, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) // 2012/12/20 added by Keming's suggestion test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x88, 0xF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const RegSetEntry HDMITX_SetHDMI_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) // Config default HDMI Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0xC0, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0xC1, 0x03, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0xC6, 0x03, 0x03}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const RegSetEntry HDMITX_SetDVI_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) // Config default HDMI Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x0F, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x58, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0xC0, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0xC1, 0x03, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0xC6, 0x03, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const RegSetEntry HDMITX_DefaultAVIInfo_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) // Config default avi infoframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x0F, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x58, 0xFF, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x59, 0xFF, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x5A, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x5B, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x5C, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x5D, 0xFF, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x5E, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x5F, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x60, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x61, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x62, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x63, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x64, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x65, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0xCD, 0x03, 0x03}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const RegSetEntry HDMITX_DeaultAudioInfo_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) // Config default audio infoframe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x0F, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x68, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x69, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x6A, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x6B, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x6C, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x6D, 0xFF, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0xCE, 0x03, 0x03}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const RegSetEntry HDMITX_Aud_CHStatus_LPCM_20bit_48Khz[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x0F, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x33, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x34, 0xFF, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x35, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x91, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x92, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x93, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x94, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x98, 0xFF, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x99, 0xFF, 0xDA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x0F, 0x01, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const RegSetEntry HDMITX_AUD_SPDIF_2ch_24bit[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x0F, 0x11, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x04, 0x14, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0xE0, 0xFF, 0xD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0xE1, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0xE2, 0xFF, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0xE3, 0xFF, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0xE4, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0xE5, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x04, 0x14, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const RegSetEntry HDMITX_AUD_I2S_2ch_24bit[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0F, 0x11, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x04, 0x14, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0xE0, 0xFF, 0xC1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0xE1, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x5A, 0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0xE2, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0xE2, 0xFF, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0xE3, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0xE4, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0xE5, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x04, 0x14, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const RegSetEntry HDMITX_DefaultAudio_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) // Config default audio output format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x0F, 0x21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x04, 0x14, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0xE0, 0xFF, 0xC1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0xE1, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0xE2, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0xE2, 0xFF, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0xE3, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0xE4, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0xE5, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x0F, 0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x33, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x34, 0xFF, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x35, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x91, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x92, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x93, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x94, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x98, 0xFF, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x99, 0xFF, 0xDB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x04, 0x14, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const RegSetEntry HDMITX_PwrDown_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x05, 0x60, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0xf8, 0xc3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0xf8, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0xe8, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0xE0, 0x0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) // Enable GRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) // #if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) // {0x0F, 0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) // #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) // {0x0F, 0x70, 0x70},// PwrDown RCLK , IACLK ,TXCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) // #endif //#if (IC_VERSION == 0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) // PLL Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x61, 0x10, 0x10}, // DRV_RST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x62, 0x08, 0x00}, // XP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x64, 0x04, 0x00}, // IP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x01, 0x00, 0x00}, // idle(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x61, 0x60, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x70, 0xFF, 0x00},//hdmitxwr(0x70, 0x00); // Select TXCLK power-down path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) // PLL PwrDn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) // {0x61, 0x20, 0x20}, // PwrDn DRV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) // {0x62, 0x44, 0x44}, // PwrDn XPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) // {0x64, 0x40, 0x40}, // PwrDn IPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) // HDMITX PwrDn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) // {0x05, 0x01, 0x01}, // PwrDn PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) // {0xE0, 0x0F, 0x00},// hdmitxset(0xE0, 0x0F, 0x00); // PwrDn GIACLK, IACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) // {0x72, 0x03, 0x00},// hdmitxset(0x72, 0x03, 0x00); // PwrDn GTxCLK (QCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) // {0x0F, 0x78, 0x78}, // PwrDn GRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x0F, 0x70, 0x70}//Gate RCLK IACLK TXCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const RegSetEntry HDMITX_PwrOn_Table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x0F, 0x70, 0x00}, // // PwrOn RCLK , IACLK ,TXCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) // {0x0F, 0x78, 0x38}, // PwrOn GRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) // {0x05, 0x01, 0x00}, // PwrOn PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) // PLL PwrOn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x61, 0x20, 0x00}, // PwrOn DRV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x62, 0x44, 0x00}, // PwrOn XPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x64, 0x40, 0x00}, // PwrOn IPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) // PLL Reset OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x61, 0x10, 0x00}, // DRV_RST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x62, 0x08, 0x08}, // XP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x64, 0x04, 0x04} // IP_RESETB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) // {0x0F, 0x78, 0x08}, // PwrOn IACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const RegSetEntry hdmi_tx_pg_1080p60_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) // 1920x1080@60.00Hz VIC = 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x0F, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x90, 0xFF, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x91, 0xFF, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x92, 0xFF, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x93, 0xFF, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x94, 0xFF, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x95, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x96, 0xFF, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x97, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x98, 0xFF, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x99, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x9A, 0xFF, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x9B, 0xFF, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x9C, 0xFF, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x9D, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x9E, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x9F, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0xA0, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0xA1, 0xFF, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0xA2, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0xA3, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0xA4, 0xFF, 0x4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0xA5, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0xA6, 0xFF, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0xB1, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0xB2, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0xA9, 0xFF, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0xAA, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0xAB, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0xAC, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0xAF, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0xB0, 0xFF, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const RegSetEntry hdmi_tx_pg_720p60_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) // PatGen\fmt4_PatGen.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) // 1280x720@60.00Hz VIC = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x90, 0xFF, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x91, 0xFF, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x92, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x93, 0xFF, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x94, 0xFF, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x95, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x96, 0xFF, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x97, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x98, 0xFF, 0xED},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x99, 0xFF, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x9A, 0xFF, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x9B, 0xFF, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x9C, 0xFF, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x9D, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x9E, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x9F, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0xA0, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0xA1, 0xFF, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0xA2, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0xA3, 0xFF, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0xA4, 0xFF, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0xA5, 0xFF, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0xA6, 0xFF, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0xB1, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0xB2, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0xA9, 0xFF, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0xAA, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0xAB, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0xAC, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0xAF, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0xB0, 0xFF, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const RegSetEntry hdmi_tx_pg_480p60_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) // PatGen\fmt2_PatGen.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) // 720x480@59.94Hz VIC = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x0F, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x90, 0xFF, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x91, 0xFF, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x92, 0xFF, 0x7A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x93, 0xFF, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x94, 0xFF, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x95, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x96, 0xFF, 0x3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x97, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x98, 0xFF, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x99, 0xFF, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x9A, 0xFF, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x9B, 0xFF, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x9C, 0xFF, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x9D, 0xFF, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x9E, 0xFF, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x9F, 0xFF, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0xA0, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0xA1, 0xFF, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0xA2, 0xFF, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0xA3, 0xFF, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0xA4, 0xFF, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0xA5, 0xFF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0xA6, 0xFF, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0xB1, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0xB2, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) // {0xA9, 0xFF, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0xA9, 0xFF, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0xAA, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0xAB, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0xAC, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0xAF, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0xB0, 0xFF, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #ifdef DETECT_VSYNC_CHG_IN_SAV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static bool EnSavVSync = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* Period of hdcp checks (to ensure we're still authenticated) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define DRM_HDCP2_CHECK_PERIOD_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Shared lengths/masks between HDMI/DVI/DisplayPort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define DRM_HDCP_AN_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define DRM_HDCP_BSTATUS_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define DRM_HDCP_KSV_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define DRM_HDCP_RI_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define DRM_HDCP_V_PRIME_PART_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define DRM_HDCP_V_PRIME_NUM_PARTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Slave address for the HDCP registers in the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define DRM_HDCP_DDC_ADDR 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Value to use at the end of the SHA-1 bytestream used for repeaters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define DRM_HDCP_SHA1_TERMINATOR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* HDCP register offsets for HDMI/DVI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define DRM_HDCP_DDC_BKSV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define DRM_HDCP_DDC_RI_PRIME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define DRM_HDCP_DDC_AKSV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define DRM_HDCP_DDC_AN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define DRM_HDCP_DDC_BCAPS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DRM_HDCP_DDC_BSTATUS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define DRM_HDCP_DDC_KSV_FIFO 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define MAX_HDCP_DOWN_STREAM_COUNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define HDMI_TX_HDCP_RETRY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define HDMI_TX_PCLK_DIV2 false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #ifndef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) extern const struct drm_display_mode edid_cea_modes[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct it6161 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct i2c_client *i2c_mipi_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct i2c_client *i2c_hdmi_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct i2c_client *i2c_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct mutex mode_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct regmap *regmap_mipi_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct regmap *regmap_hdmi_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct regmap *regmap_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 it6161_addr_hdmi_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 it6161_addr_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct device_node *host_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct completion wait_hdcp_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct completion wait_edid_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct delayed_work hdcp_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct work_struct wait_hdcp_ksv_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 hdmi_tx_hdcp_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 hdmi_tx_rclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 hdmi_tx_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 mipi_rx_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u32 mipi_rx_rclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 mipi_rx_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct drm_display_mode mipi_rx_p_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct drm_display_mode hdmi_tx_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct drm_display_mode source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct hdmi_avi_infoframe source_avi_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 vic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u8 mipi_rx_lane_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) bool is_repeater;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u8 hdcp_downstream_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u8 bksv[DRM_HDCP_KSV_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u8 sha1_transform_input[HDCP_SHA1_FIFO_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u16 bstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) bool enable_drv_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u8 hdmi_tx_output_color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u8 hdmi_tx_input_color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u8 hdmi_tx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u8 support_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u8 bOutputAudioMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u8 bAudioChannelSwap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u8 bAudioChannelEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u8 bAudFs ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u32 TMDSClock ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 RCLK ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #ifdef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) HDMITX_HDCP_State TxHDCP_State ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u16 usHDCPTimeOut ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u16 Tx_BStatus ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u8 bAuthenticated:1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) bool hdmi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u8 bAudInterface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct gpio_desc *enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct gpio_desc *test_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct delayed_work restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static struct it6161 *it6161;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) //static struct it6161 *it6161_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct drm_bridge *it6161_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct regmap_range it6161_mipi_rx_bridge_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { .range_min = 0, .range_max = 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const struct regmap_access_table it6161_mipi_rx_bridge_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .yes_ranges = it6161_mipi_rx_bridge_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .n_yes_ranges = ARRAY_SIZE(it6161_mipi_rx_bridge_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const struct regmap_config it6161_mipi_rx_bridge_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .volatile_table = &it6161_mipi_rx_bridge_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const struct regmap_range it6161_hdmi_tx_bridge_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { .range_min = 0, .range_max = 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const struct regmap_access_table it6161_hdmi_tx_bridge_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .yes_ranges = it6161_hdmi_tx_bridge_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .n_yes_ranges = ARRAY_SIZE(it6161_hdmi_tx_bridge_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct regmap_config it6161_hdmi_tx_bridge_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .volatile_table = &it6161_hdmi_tx_bridge_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const struct regmap_range it6161_cec_bridge_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) { .range_min = 0, .range_max = 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct regmap_access_table it6161_cec_bridge_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .yes_ranges = it6161_cec_bridge_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .n_yes_ranges = ARRAY_SIZE(it6161_cec_bridge_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct regmap_config it6161_cec_bridge_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .volatile_table = &it6161_cec_bridge_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int it6161_mipi_rx_read(struct it6161 *it6161, unsigned int reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) err = regmap_read(it6161->regmap_mipi_rx, reg_addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) DRM_DEV_ERROR(dev, "mipi rx read failed reg[0x%x] err: %d", reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int mipi_rx_read_word(struct it6161 *it6161, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int val_0, val_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) val_0 = it6161_mipi_rx_read(it6161, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (val_0 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return val_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) val_1 = it6161_mipi_rx_read(it6161, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (val_1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return val_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return (val_1 << 8) | val_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int it6161_mipi_rx_write(struct it6161 *it6161, unsigned int reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned int reg_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) err = regmap_write(it6161->regmap_mipi_rx, reg_addr, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) DRM_DEV_ERROR(dev, "mipi rx write failed reg[0x%x] = 0x%x err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) reg_addr, reg_val, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int it6161_mipi_rx_set_bits(struct it6161 *it6161, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int mask, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) err = regmap_update_bits(it6161->regmap_mipi_rx, reg, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) DRM_DEV_ERROR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev, "mipi rx set reg[0x%x] = 0x%x mask = 0x%x failed err %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) reg, value, mask, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void it6161_mipi_rx_dump(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u8 regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) it6161_debug("mipi rx dump:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) for (i = 0; i <= 0xff; i += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) for (j = 0; j < 16; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) regs[j] = it6161_mipi_rx_read(it6161, i + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) it6161_debug("[0x%02x] = %16ph", i, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static int it6161_hdmi_tx_read(struct it6161 *it6161, unsigned int reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) err = regmap_read(it6161->regmap_hdmi_tx, reg_addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DRM_DEV_ERROR(dev, "hdmi tx read failed reg[0x%x] err: %d", reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int hdmi_tx_read_word(struct it6161 *it6161, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int val_0, val_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) val_0 = it6161_hdmi_tx_read(it6161, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (val_0 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return val_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) val_1 = it6161_hdmi_tx_read(it6161, reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (val_1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return val_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return (val_1 << 8) | val_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #ifdef HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int it6161_hdmi_tx_burst_read(struct it6161 *it6161, unsigned int reg_addr, void *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = regmap_bulk_read(it6161->regmap_hdmi_tx, reg_addr, buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) DRM_DEV_ERROR(dev, "hdmi tx burst read failed reg[0x%x] ret: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) reg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int it6161_hdmi_tx_write(struct it6161 *it6161, unsigned int reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) unsigned int reg_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) err = regmap_write(it6161->regmap_hdmi_tx, reg_addr, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) DRM_DEV_ERROR(dev, "hdmi tx write failed reg[0x%x] = 0x%x err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) reg_addr, reg_val, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int hdmi_tx_burst_write(struct it6161 *it6161, unsigned int reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) void *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct device *dev = &it6161->i2c_hdmi_tx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret = regmap_bulk_write(it6161->regmap_hdmi_tx, reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) (u8 *)buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DRM_DEV_ERROR(dev, "hdmi tx burst write failed reg[0x%x] ret = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) reg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int it6161_hdmi_tx_set_bits(struct it6161 *it6161, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) unsigned int mask, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) err = regmap_update_bits(it6161->regmap_hdmi_tx, reg, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) DRM_DEV_ERROR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev, "hdmi tx set reg[0x%x] = 0x%x mask = 0x%x failed err %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) reg, value, mask, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int inline it6161_hdmi_tx_change_bank(struct it6161 *it6161, int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, x & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void it6161_hdmi_tx_dump(struct it6161 *it6161, unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u8 regs[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) it6161_debug("hdmi tx dump bank: %d", bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) it6161_hdmi_tx_change_bank(it6161, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) for (i = 0; i <= 0xff; i += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (j = 0; j < 16; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) regs[j] = it6161_hdmi_tx_read(it6161, i + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) it6161_debug("[0x%02x] = %16ph", i, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int it6161_cec_read(struct it6161 *it6161, unsigned int reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) err = regmap_read(it6161->regmap_cec, reg_addr, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) DRM_DEV_ERROR(dev, "cec read failed reg[0x%x] err: %d", reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int it6161_cec_write(struct it6161 *it6161, unsigned int reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned int reg_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) err = regmap_write(it6161->regmap_cec, reg_addr, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) DRM_DEV_ERROR(dev, "cec write failed reg[0x%x] = 0x%x err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) reg_addr, reg_val, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int it6161_cec_set_bits(struct it6161 *it6161, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) unsigned int mask, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) err = regmap_update_bits(it6161->regmap_cec, reg, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) DRM_DEV_ERROR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev, "cec set reg[0x%x] = 0x%x mask = 0x%x failed err %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) reg, value, mask, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static inline struct it6161 *connector_to_it6161(struct drm_connector *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return container_of(c, struct it6161, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static inline struct it6161 *bridge_to_it6161(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return container_of(bridge, struct it6161, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static void mipi_rx_logic_reset(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static void mipi_rx_logic_reset_release(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static void hdmi_tx_logic_reset(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) it6161_hdmi_tx_set_bits(it6161, 0x04, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static void it6161_mipi_rx_int_mask_disable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) it6161_mipi_rx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) it6161_mipi_rx_write(it6161, 0x09, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) it6161_mipi_rx_write(it6161, 0x0A, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) it6161_mipi_rx_write(it6161, 0x0B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static void it6161_mipi_rx_int_mask_enable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) it6161_mipi_rx_write(it6161, 0x09, EnMBPM ? 0x11 : 0xBF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) it6161_mipi_rx_write(it6161, 0x0A, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) it6161_mipi_rx_write(it6161, 0x0B, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static void hdmi_tx_hdcp_int_mask_disable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_KSVLISTCHK_MASK, B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_KSVLISTCHK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #ifdef HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static void hdmi_tx_hdcp_int_mask_enable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_KSVLISTCHK_MASK, ~(B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_KSVLISTCHK_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static void it6161_hdmi_tx_int_mask_disable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) it6161_mipi_rx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK2, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void it6161_hdmi_tx_int_mask_enable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, ~(B_TX_AUDIO_OVFLW_MASK | B_TX_DDC_FIFO_ERR_MASK | B_TX_DDC_BUS_HANG_MASK | B_TX_HPD_MASK | B_TX_RXSEN_MASK));//0x7C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK2, ~(B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_KSVLISTCHK_MASK | B_TX_PKT_VID_UNSTABLE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, ~B_TX_VIDSTABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void it6161_hdmi_tx_write_table(struct it6161 *it6161, const RegSetEntry table[], int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (table[i].mask == 0 && table[i].value == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) msleep(table[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) } else if (table[i].mask == 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) it6161_hdmi_tx_write(it6161, table[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) table[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) it6161_hdmi_tx_set_bits(it6161, table[i].offset, table[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) table[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static inline void hdmi_tx_enable_pattern_generator(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) it6161_debug("enable pattern generator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static inline void hdmi_tx_disable_pattern_generator(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static inline void hdmi_tx_pattern_generator_setup_color(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x3F, (HDMI_TX_PATTERN_COLLOR_B << 4) | (HDMI_TX_PATTERN_COLLOR_G << 2) | HDMI_TX_PATTERN_COLLOR_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static void hdmi_tx_setup_pattern_generator(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) switch (HDMI_TX_PATTERN_GENERATOR_FORMAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_480p60_table, sizeof(hdmi_tx_pg_480p60_table) / sizeof(RegSetEntry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) DRM_INFO("use 480p60 pattern");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_720p60_table, sizeof(hdmi_tx_pg_720p60_table) / sizeof(RegSetEntry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) DRM_INFO("use 720p60 pattern");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_1080p60_table, sizeof(hdmi_tx_pg_1080p60_table) / sizeof(RegSetEntry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) DRM_INFO("use 1080p60 pattern");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_1080p60_table, sizeof(hdmi_tx_pg_1080p60_table) / sizeof(RegSetEntry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) DRM_INFO("other format, will use 1080p60 pattern");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) hdmi_tx_pattern_generator_setup_color(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) hdmi_tx_enable_pattern_generator(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void show_display_mode(struct it6161 *it6161, struct drm_display_mode *display_mode, u8 select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) char *name[3] = { "source output", "it6161 hdmi tx receive", "mipi rx p receive" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) DRM_INFO("%s timing:", name[select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) DRM_INFO("timing name:%s", display_mode->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) DRM_INFO("clock = %dkHz", display_mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) DRM_INFO("htotal = %d", display_mode->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) DRM_INFO("hactive = %d", display_mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) DRM_INFO("hfront_porch = %d", display_mode->hsync_start - display_mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) DRM_INFO("hsyncw = %d", display_mode->hsync_end - display_mode->hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) DRM_INFO("hback_porch = %d", display_mode->htotal - display_mode->hsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) DRM_INFO("vtotal = %d", display_mode->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) DRM_INFO("vactive = %d", display_mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) DRM_INFO("vfront_porch = %d", display_mode->vsync_start - display_mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) DRM_INFO("vsyncw = %d", display_mode->vsync_end - display_mode->vsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) DRM_INFO("vback_porch = %d", display_mode->vtotal - display_mode->vsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) DRM_INFO("drm_display_mode flags = 0x%04x", display_mode->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static void inline it6161_set_interrupts_active_level(enum it6161_active_level level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) it6161_mipi_rx_set_bits(it6161, 0x0D, 0x02, level == HIGH ? 0x02 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) it6161_hdmi_tx_set_bits(it6161, 0x05, 0xC0, level == HIGH ? 0x80 : 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static void hdmi_tx_init(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) it6161_debug("init hdmi tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) it6161_hdmi_tx_write_table(it6161, HDMITX_Init_Table, ARRAY_SIZE(HDMITX_Init_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) it6161_hdmi_tx_write_table(it6161, HDMITX_PwrOn_Table, ARRAY_SIZE(HDMITX_PwrOn_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultVideo_Table, ARRAY_SIZE(HDMITX_DefaultVideo_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) it6161_hdmi_tx_write_table(it6161, HDMITX_SetHDMI_Table, ARRAY_SIZE(HDMITX_SetHDMI_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultAVIInfo_Table, ARRAY_SIZE(HDMITX_DefaultAVIInfo_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) it6161_hdmi_tx_write_table(it6161, HDMITX_DeaultAudioInfo_Table, ARRAY_SIZE(HDMITX_DeaultAudioInfo_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) it6161_hdmi_tx_write_table(it6161, HDMITX_Aud_CHStatus_LPCM_20bit_48Khz, ARRAY_SIZE(HDMITX_Aud_CHStatus_LPCM_20bit_48Khz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) it6161_hdmi_tx_write_table(it6161, HDMITX_AUD_SPDIF_2ch_24bit, ARRAY_SIZE(HDMITX_AUD_SPDIF_2ch_24bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #ifdef SUPPORT_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) it6161_hdmi_tx_set_bits(it6161, 0x8D, 0x01, 0x01);//it6161_hdmi_tx_write(it6161, 0xf, 0 ); //pet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) Initial_Ext_Int1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) HDMITX_CEC_Init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #endif // SUPPORT_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static bool mipi_rx_get_m_video_stable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return !!(it6161_mipi_rx_read(it6161, 0x0D) & 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static bool mipi_rx_get_p_video_stable(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return !!(it6161_mipi_rx_read(it6161, 0x0D) & 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static void mipi_rx_setup_polarity(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct drm_display_mode *display_mode = &it6161->source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) u8 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) polarity = ((display_mode->flags & DRM_MODE_FLAG_PHSYNC) == DRM_MODE_FLAG_PHSYNC) ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) polarity |= ((display_mode->flags & DRM_MODE_FLAG_PVSYNC) == DRM_MODE_FLAG_PVSYNC) ? 0x02 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) it6161_mipi_rx_set_bits(it6161, 0x4E, 0x03, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static void mipi_rx_afe_configuration(struct it6161 *it6161, u8 data_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) u8 MPLaneNum = (it6161->mipi_rx_lane_count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) it6161_debug("afe configuration data_id:0x%02x", data_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (data_id == RGB_18b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if( MPLaneNum==3 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02); // MPPCLKSel = 1; // 4-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02); // MPPCLKSel = 1; // 4-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) DRM_INFO("Solomon is impossible TXPLL= 9/2 PCLK !!! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) DRM_INFO("MCLK=3/4PCLK Change to MCLK=PCLK ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) } else if( MPLaneNum==1 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); // MPPCLKSel = 6; // 2-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); // MPPCLKSel = 6; // 2-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) DRM_INFO("IT6121 is impossible RXPLL= 2/9 PCLK !!! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) DRM_INFO("MCLK=3/4PCLK Change to MCLK=PCLK ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) } else if( MPLaneNum==0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x0b);// MPPCLKSel = 7; // 1-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x08); // MPPCLKSel = 8; // 1-lane : MCLK = 3/4 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if( MPLaneNum==3 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x03);// MPPCLKSel = 0; // 4-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02);// MPPCLKSel = 1; // 4-lane : MCLK = 3/4 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) } else if( MPLaneNum==1 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x07); // MPPCLKSel = 2; // 2-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); // MPPCLKSel = 3; // 2-lane : MCLK = 3/4 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) } else if( MPLaneNum==0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) // if( EnMPx1PCLK )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) // it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x0f);// MPPCLKSel = 4; // 1-lane : MCLK = 1/1 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) // else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x0b); // MPPCLKSel = 5; // 1-lane : MCLK = 3/4 PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static void mipi_rx_configuration(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u8 mipi_lane_config = (it6161->mipi_rx_lane_count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) //20200211 D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) msleep(1);//idle(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) // MPRX Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) // it6161_mipi_rx_set_bits(it6161, 0x05, 0x07, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) // msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) // it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) mipi_rx_logic_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) mipi_rx_logic_reset_release(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) it6161_mipi_rx_int_mask_disable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* setup INT pin: active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) it6161_mipi_rx_set_bits(it6161, 0x0d, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) it6161_mipi_rx_set_bits(it6161, 0x0C, 0x0F, (MPLaneSwap<<3) + (MPPNSwap<<2) + mipi_lane_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) it6161_mipi_rx_set_bits(it6161, 0x11, 0x3F, (EnIOIDDQ<<5)+(EnStb2Rst<<4)+(EnExtStdby<<3)+(EnStandby<<2)+(InvPCLK<<1)+InvMCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) it6161_mipi_rx_set_bits(it6161, 0x12, 0x03, (PDREFCNT<<1)+PDREFCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) it6161_mipi_rx_set_bits(it6161, 0x18, 0xf7, (RegEnSyncErr<<7)+(SkipStg<<4)+HSSetNum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) it6161_mipi_rx_set_bits(it6161, 0x19, 0xf3, (PPIDbgSel<<4)+(EnContCK<<1)+EnDeSkew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) it6161_mipi_rx_set_bits(it6161, 0x20, 0xf7, (EOTPSel<<4)+(RegEnDummyECC<<2)+(RegIgnrBlk<<1)+RegIgnrNull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) it6161_mipi_rx_set_bits(it6161, 0x21, 0x07, LMDbgSel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) // it6161_mipi_rx_set_bits(it6161, 0x44, 0x38, (MREC_Update<<5)+(PREC_Update<<4)+(REGSELDEF<<3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) it6161_mipi_rx_set_bits(it6161, 0x44, 0x3a, (MREC_Update<<5)+(PREC_Update<<4)+(REGSELDEF<<3)+(RegAutoSync<<1));//D0 20200211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) it6161_mipi_rx_set_bits(it6161, 0x4B, 0x1f, (EnFReSync<<4)+(EnVREnh<<3)+EnVREnhSel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) it6161_mipi_rx_write(it6161, 0x4C, PPSFFRdStg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) it6161_mipi_rx_set_bits(it6161, 0x4D, 0x01, (PPSFFRdStg>>8)&0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) it6161_mipi_rx_set_bits(it6161, 0x4E, 0x0C, (EnVReSync<<3)+(EnHReSync<<2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) it6161_mipi_rx_set_bits(it6161, 0x4F, 0x03, EnFFAutoRst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) //it6161_mipi_rx_write(it6161, 0x27, MPVidType);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) it6161_mipi_rx_write(it6161, 0x72, MShift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) it6161_mipi_rx_write(it6161, 0x73, PShift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) it6161_mipi_rx_set_bits(it6161, 0x80, 0x20, ENABLE_MIPI_RX_EXTERNAL_CLOCK << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) it6161_mipi_rx_write(it6161, 0x21, 0x00); //debug sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) // it6161_mipi_rx_set_bits(it6161, 0x84, 0x70, 0x70); // max swing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) // it6161_mipi_rx_set_bits(it6161, 0x84, 0x70, 0x40); // def swing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) it6161_mipi_rx_set_bits(it6161, 0x84, 0x70, 0x00); // min swing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) it6161_mipi_rx_set_bits(it6161, 0xA0, 0x01, EnMBPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* enable auto detect format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) it6161_mipi_rx_set_bits(it6161, 0x21, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) // if( REGSELDEF == true )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) // DRM_INFO("REGSELDEF MODE !!! ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) // PHFP = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) // PHSW = 0x3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) // PHBP = 0x3c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) // it6161_mipi_rx_write(it6161, 0x30, PHFP); // HFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) // it6161_mipi_rx_write(it6161, 0x31, 0x80+((PHFP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) // it6161_mipi_rx_write(it6161, 0x32, PHSW); // HBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) // it6161_mipi_rx_write(it6161, 0x33, 0x80+((PHSW&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) // it6161_mipi_rx_write(it6161, 0x34, PHBP); // HBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) // it6161_mipi_rx_write(it6161, 0x35, 0x80+((PHFP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) it6161_mipi_rx_set_bits(it6161, 0x05, 0x02, 0x02); // Video Clock Domain Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if( EnMBPM ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) //HSW = pSetVTiming->HSyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) //VSW = pSetVTiming->VSyncWidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) it6161_mipi_rx_write(it6161, 0xA1, 0x00); // HRS offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) it6161_mipi_rx_write(it6161, 0xA2, 0x00); // VRS offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) // it6161_mipi_rx_write(it6161, 0xA3, 44);//HSW); // HSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) // it6161_mipi_rx_write(it6161, 0xA5, 5);//VSW); // VSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) it6161_mipi_rx_write(it6161, 0xA3, 0x08);//0x10); // HSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) it6161_mipi_rx_write(it6161, 0xA5, 0x04); // VSw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) // it6161_hdmi_tx_set_bits(it6161, 0xa9, 0xc0, (EnTBPM<<7)/* + (EnTxPatMux<<6)*/);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) // it6161_hdmi_tx_set_bits(it6161, 0xbf, 0x80, (NRTXRCLK<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if( MPForceStb == true ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) // mprxwr(0x30, HFP); // HSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) // mprxwr(0x31, 0x80+((HFP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) // mprxwr(0x32, HSW); // HSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) // mprxwr(0x33, 0x80+((HSW&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) // mprxwr(0x34, HBP&0xFF); // HBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) // mprxwr(0x35, 0x80+((HBP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) // mprxwr(0x36, HDEW&0xFF); // HDEW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) // mprxwr(0x37, 0x80+((HDEW&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) // mprxwr(0x38, HVR2nd&0xFF); // HVR2nd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) // mprxwr(0x39, 0x80+((HVR2nd&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) // mprxwr(0x3A, VFP); // VSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) // mprxwr(0x3B, 0x80+((VFP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) // mprxwr(0x3C, VSW); // VSW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) // mprxwr(0x3D, 0x80+((VSW&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) // mprxwr(0x3E, VBP&0xFF); // VBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) // mprxwr(0x3F, 0x80+((VBP&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) // mprxwr(0x40, VDEW&0xFF); // VDEW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) // mprxwr(0x41, 0x80+((VDEW&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) // mprxwr(0x42, VFP2nd&0xFF); // VFP2nd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) // mprxwr(0x43, 0x80+((VFP2nd&0x3F00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) // mprxset(0x4e, 0x03, 0xC0+(VPol<<1)+HPol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if( REGSELDEF == false ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) it6161_mipi_rx_set_bits(it6161, 0x31, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) it6161_mipi_rx_set_bits(it6161, 0x33, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) it6161_mipi_rx_set_bits(it6161, 0x35, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) it6161_mipi_rx_set_bits(it6161, 0x37, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) it6161_mipi_rx_set_bits(it6161, 0x39, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) it6161_mipi_rx_set_bits(it6161, 0x3A, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) it6161_mipi_rx_set_bits(it6161, 0x3C, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) it6161_mipi_rx_set_bits(it6161, 0x3E, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) it6161_mipi_rx_set_bits(it6161, 0x41, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) it6161_mipi_rx_set_bits(it6161, 0x43, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) // mprxset(0x4e, 0x03, 0x00+(VPol<<1)+HPol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void mipi_rx_init(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) it6161_debug("init mpip rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) mipi_rx_configuration(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) it6161_mipi_rx_set_bits(it6161, 0x05, 0x03, 0x00); // Enable MPRX clock domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static void hdmi_tx_video_reset(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) it6161_debug("%s reg04:0x%02x reg05:0x%02x reg6:0x%02x reg07:0x%02x reg08:0x%02x reg0e:0x%02x", __func__, it6161_hdmi_tx_read(it6161, 0x04), it6161_hdmi_tx_read(it6161, 0x05), it6161_hdmi_tx_read(it6161, 0x06), it6161_hdmi_tx_read(it6161, 0x07), it6161_hdmi_tx_read(it6161, 0x08), it6161_hdmi_tx_read(it6161, 0x0e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static void hdmi_tx_audio_fifo_reset(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST, B_HDMITX_AUD_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* DDC master will set to be host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static void it6161_hdmi_tx_clear_ddc_fifo(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_FIFO_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) it6161_hdmi_tx_set_bits(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHOST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #ifdef HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static void it6161_hdmi_tx_generate_ddc_sclk(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_GEN_SCLCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static void hdmi_tx_generate_blank_timing(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct drm_display_mode *display_mode = &it6161->source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) bool force_hdmi_tx_clock_stable = true, force_hdmi_tx_video_stable = true, hdmi_tx_by_pass_mode = false, de_generation = false, enable_de_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) u8 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) u16 hsync_start, hsync_end, vsync_start, vsync_end, htotal, hde_start, vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) u16 vsync_start_2nd = 0, vsync_end_2nd = 0, vsync_rising_at_h_2nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) it6161_debug("start %s", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) polarity = ((display_mode->flags & DRM_MODE_FLAG_PHSYNC) == DRM_MODE_FLAG_PHSYNC) ? 0x02 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) polarity |= ((display_mode->flags & DRM_MODE_FLAG_PVSYNC) == DRM_MODE_FLAG_PVSYNC) ? 0x04 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) hsync_start = display_mode->hsync_start - display_mode->hdisplay - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) hsync_end = hsync_start + display_mode->hsync_end - display_mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) vsync_rising_at_h_2nd = hsync_start + display_mode->htotal / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) hde_start = display_mode->htotal - display_mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) it6161_hdmi_tx_set_bits(it6161, 0xD1, 0x0C, force_hdmi_tx_clock_stable << 3 | force_hdmi_tx_video_stable << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, hdmi_tx_by_pass_mode << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) it6161_hdmi_tx_set_bits(it6161, 0x90, 0x01, de_generation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) it6161_hdmi_tx_write(it6161, 0x91, vsync_rising_at_h_2nd >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (vsync_rising_at_h_2nd & 0x00F) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) it6161_hdmi_tx_set_bits(it6161, 0x90, 0x06, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) it6161_hdmi_tx_write(it6161, 0x95, (u8)hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) it6161_hdmi_tx_write(it6161, 0x96, (u8)hsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) it6161_hdmi_tx_write(it6161, 0x97, (hsync_end & 0x0F00) >> 4 | hsync_start >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) vsync_start = display_mode->vsync_start - display_mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) vsync_end = display_mode->vsync_end - display_mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if ((display_mode->flags & DRM_MODE_FLAG_INTERLACE) != DRM_MODE_FLAG_INTERLACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) vsync_start_2nd = 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) vsync_end_2nd = 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) vtotal = display_mode->vtotal - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) vtotal = display_mode->vtotal * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) it6161_hdmi_tx_write(it6161, 0xA0, (u8)vsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) it6161_hdmi_tx_write(it6161, 0xA1, (vsync_end & 0x0F) << 4 | vsync_start >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) it6161_hdmi_tx_write(it6161, 0xA2, (u8)vsync_start_2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) it6161_hdmi_tx_write(it6161, 0xA6, (vsync_end_2nd & 0xF0) | vsync_end >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) it6161_hdmi_tx_write(it6161, 0xA3, (vsync_end_2nd & 0x0F) << 4 | vsync_start_2nd >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) it6161_hdmi_tx_write(it6161, 0xA4, vsync_rising_at_h_2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) it6161_hdmi_tx_set_bits(it6161, 0xB1, 0x51, (hsync_end & 0x1000) >> 6 | (hsync_start & 0x1000) >> 8 | hde_start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x2F, enable_de_only << 5 | vsync_rising_at_h_2nd >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x05, (vsync_rising_at_h_2nd & 0x1000) >> 10 | (vsync_rising_at_h_2nd & 0x1000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) htotal = display_mode->htotal - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (htotal & 0x0F) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) it6161_hdmi_tx_write(it6161, 0x91, (htotal & 0x0FF0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x01, (htotal & 0x1000) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) it6161_hdmi_tx_write(it6161, 0x98, vtotal & 0x0FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) it6161_hdmi_tx_write(it6161, 0x99, (vtotal & 0xF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* force abort DDC and reset DDC bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static void it6161_hdmi_tx_abort_ddc(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u8 cp_desire, sw_reset, ddc_master, retry = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) u8 uc, timeout, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) it6161_debug("%s", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* save the sw reset, ddc master and cp desire setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) sw_reset = it6161_hdmi_tx_read(it6161, REG_TX_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) cp_desire = it6161_hdmi_tx_read(it6161, REG_TX_HDCP_DESIRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ddc_master = it6161_hdmi_tx_read(it6161, REG_TX_DDC_MASTER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) // it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE,CPDesire&(~B_TX_CPDESIRE)); // @emily change order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, sw_reset | B_TX_HDCP_RST_HDMITX); // @emily change order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* do abort DDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_DDC_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_GEN_SCLCLK);//hdmitxwr(0x15, 0x0A); //it6161A0 // Generate SCL Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) for (timeout = 0; timeout < 200; timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) uc = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (uc&B_TX_DDC_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (uc & (B_TX_DDC_NOACK | B_TX_DDC_WAITBUS | B_TX_DDC_ARBILOSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) DRM_INFO("it6161_hdmi_tx_abort_ddc Fail by reg16=%02X\n",(int)uc);//pet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* delay 1 ms to stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static bool hdmi_tx_get_video_state(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return !!(B_TXVIDSTABLE & it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static bool inline hdmi_tx_get_sink_hpd(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return !!(it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS) & B_TX_HPDETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static bool it6161_ddc_op_finished(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) int reg16 = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (reg16 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) return (reg16 & B_TX_DDC_DONE) == B_TX_DDC_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static int it6161_ddc_wait(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) //struct device *dev = &it6161->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) while (!it6161_ddc_op_finished(it6161)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) DRM_INFO("Timed out waiting AUX to finish");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) DRM_INFO("Failed to read DDC channel: 0x%02x", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if(status & B_TX_DDC_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) DRM_INFO("DDC error: 0x%02x", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static void hdmi_tx_ddc_operation(struct it6161 *it6161, u8 addr, u8 offset, u8 size, u8 segment, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) size = min(size, (u8)DDC_FIFO_MAXREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) it6161_hdmi_tx_write(it6161, REG_TX_DDC_EDIDSEG, segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) // Function: it6161_ddc_get_edid_operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) // Parameter: buffer - the pointer of buffer to receive EDID ucdata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) // segment - the segment of EDID readback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) // offset - the offset of EDID ucdata in the segment. in byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) // size - the read back bytes count,cannot exceed 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) // Return: ER_SUCCESS if successfully getting EDID. ER_FAIL otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) // Remark: function for read EDID ucdata from reciever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) // Side-Effect: DDC master will set to be HOST. DDC FIFO will be used and dirty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static int it6161_ddc_get_edid_operation(struct it6161 *it6161, u8 *buffer, u8 segment, u8 offset, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) u8 status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if(!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if(it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1) & B_TX_INT_DDC_BUS_HANG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) DRM_INFO("Called it6161_hdmi_tx_abort_ddc()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) it6161_hdmi_tx_abort_ddc(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) status = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hdmi_tx_ddc_operation(it6161, DDC_EDID_ADDRESS, offset, size, segment, CMD_EDID_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) status = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) buffer[i] = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static int it6161_get_edid_block(void *data, u8 *buf, unsigned int block_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct it6161 *it6161 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) u8 offset, ret, step = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) step = min(step, (u8)DDC_FIFO_MAXREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) DRM_INFO("[%s] edid block number:%d read step:%d", __func__, block_num, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) for (offset = 0; offset < len; offset += step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ret = it6161_ddc_get_edid_operation(it6161, buf + offset, block_num / 2, (block_num % 2) * EDID_LENGTH + offset, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if(ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #ifdef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) DRM_INFO("[0x%02x]: %*ph", offset, step, buf + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) DRM_INFO("[0x%02x]:", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) for (ret = 0; ret < step; ret++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) printf(" 0x%02x", (buf + offset)[ret]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) printf("\n\r");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static void hdmi_tx_set_capability_from_edid_parse(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct drm_display_info *info = &it6161->connector.display_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) it6161->hdmi_mode = drm_detect_hdmi_monitor(it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) it6161->support_audio = drm_detect_monitor_audio(it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (it6161->hdmi_tx_output_color_space == F_MODE_YUV444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB444) != DRM_COLOR_FORMAT_YCRCB444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) it6161->hdmi_tx_output_color_space |= F_MODE_RGB444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (it6161->hdmi_tx_output_color_space == F_MODE_YUV422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB422) != DRM_COLOR_FORMAT_YCRCB422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) it6161->hdmi_tx_output_color_space |= F_MODE_RGB444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) DRM_INFO("%s mode, monitor %ssupport audio, outputcolormode:%d color_formats:0x%08x color_depth:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) it6161->hdmi_mode ? "HDMI" : "DVI", it6161->support_audio ? "" : "not ", it6161->hdmi_tx_output_color_space, info->color_formats, info->bpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if ((info->color_formats & DRM_COLOR_FORMAT_RGB444) == DRM_COLOR_FORMAT_RGB444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) DRM_INFO("support RGB444 output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB444) == DRM_COLOR_FORMAT_YCRCB444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) DRM_INFO("support YUV444 output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB422) == DRM_COLOR_FORMAT_YCRCB422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) DRM_INFO("support YUV422 output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static void it6161_variable_config(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) it6161->hdmi_tx_hdcp_retry = HDMI_TX_HDCP_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) it6161->hdmi_tx_mode = HDMI_TX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) it6161->mipi_rx_lane_count = MIPI_RX_LANE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #ifdef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static int it6161_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct it6161 *it6161 = connector_to_it6161(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) int err, num_modes = 0, i, retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) it6161_debug("%s start", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (it6161->edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return drm_add_edid_modes(connector, it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) mutex_lock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) reinit_completion(&it6161->wait_edid_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) it6161->edid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) drm_do_get_edid(&it6161->connector, it6161_get_edid_block, it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (it6161->edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (!it6161->edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) DRM_DEV_ERROR(dev, "Failed to read EDID");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) err = drm_connector_update_edid_property(connector, it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) DRM_DEV_ERROR(dev, "Failed to update EDID property: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) num_modes = drm_add_edid_modes(connector, it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) complete(&it6161->wait_edid_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) DRM_INFO("edid mode number:%d", num_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) mutex_unlock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return num_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static const struct drm_connector_helper_funcs it6161_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .get_modes = it6161_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static enum drm_connector_status it6161_detect(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct it6161 *it6161 = connector_to_it6161(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) enum drm_connector_status status = connector_status_disconnected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) bool hpd = hdmi_tx_get_sink_hpd(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) DRM_INFO("hpd:%s", hpd ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) //mutex_lock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (hpd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) it6161_variable_config(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) status = connector_status_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) it6161_set_interrupts_active_level(HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) it6161_mipi_rx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) it6161_hdmi_tx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) //mutex_lock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static const struct drm_connector_funcs it6161_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .detect = it6161_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static int it6161_attach_dsi(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) struct mipi_dsi_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) struct mipi_dsi_device *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) const struct mipi_dsi_device_info info = { .type = "it6161",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) host = of_find_mipi_dsi_host_by_node(it6161->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) DRM_INFO("it6161 failed to find dsi host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) dsi = mipi_dsi_device_register_full(host, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (IS_ERR(dsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) DRM_INFO("it6161 failed to create dsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ret = PTR_ERR(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) goto err_dsi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) it6161->dsi = dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) dsi->lanes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dsi->format = MIPI_DSI_FMT_RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ret = mipi_dsi_attach(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) DRM_INFO("it6161 failed to attach dsi to host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) goto err_dsi_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) err_dsi_attach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) mipi_dsi_device_unregister(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) err_dsi_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static int it6161_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!bridge->encoder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) DRM_DEV_ERROR(dev, "Parent encoder object not found");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) err = drm_connector_init(bridge->dev, &it6161->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) &it6161_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) DRM_MODE_CONNECTOR_HDMIA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) DRM_DEV_ERROR(dev, "Failed to initialize connector: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) drm_connector_helper_add(&it6161->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) &it6161_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) it6161->connector.polled = DRM_CONNECTOR_POLL_HPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) err = drm_connector_attach_encoder(&it6161->connector, bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) DRM_DEV_ERROR(dev, "Failed to link up connector to encoder: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) goto cleanup_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) DRM_INFO("%s, ret:%d", __func__, it6161_attach_dsi(it6161));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) err = drm_connector_register(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) DRM_DEV_ERROR(dev, "Failed to register connector: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) goto cleanup_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) it6161_debug("%s finish", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) // unregister_connector:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) // drm_connector_unregister(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) cleanup_connector:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) drm_connector_cleanup(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static void it6161_detach_dsi(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) mipi_dsi_detach(it6161->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) mipi_dsi_device_unregister(it6161->dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static void it6161_bridge_detach(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) drm_connector_unregister(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) drm_connector_cleanup(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) it6161_detach_dsi(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) it6161_bridge_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) //struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) // if (mode->flags & DRM_MODE_FLAG_INTERLACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) // return MODE_NO_INTERLACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) it6161_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) // /* Max 1200p at 5.4 Ghz, one lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) // if (mode->clock > MAX_PIXEL_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) // return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (mode->clock == 27027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (mode->clock > 165000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) //DRM_INFO("%s end", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) // static int it6161_send_video_infoframe(struct it6161 *it6161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) // struct hdmi_avi_infoframe *frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) // u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) // int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) // struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) // err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) // if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) // DRM_DEV_ERROR(dev, "Failed to pack AVI infoframe: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) // return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) // err = dptx_set_bits(it6161, 0xE8, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) // if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) // return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) // err = regmap_bulk_write(it6161->regmap_mipi_rx, 0xE9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) // buffer + HDMI_INFOFRAME_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) // frame->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) // if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) // return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) // err = dptx_set_bits(it6161, 0xE8, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) // if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) // return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) // return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static void it6161_bridge_mode_set(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) const struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct drm_display_mode *display_mode = &it6161->source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) mutex_lock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) err = drm_hdmi_avi_infoframe_from_display_mode(&it6161->source_avi_infoframe, &it6161->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) DRM_DEV_ERROR(dev, "Failed to setup AVI infoframe: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) //it6161->hdmi_tx_display_mode.base.id = adjusted_mode->base.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) strlcpy(it6161->hdmi_tx_display_mode.name, adjusted_mode->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) DRM_DISPLAY_MODE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) it6161->hdmi_tx_display_mode.type = adjusted_mode->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) it6161->hdmi_tx_display_mode.flags = adjusted_mode->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) //err = it6161_send_video_infoframe(it6161, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) strlcpy(display_mode->name, adjusted_mode->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) DRM_DISPLAY_MODE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) display_mode->clock = mode->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) display_mode->hdisplay = mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) display_mode->hsync_start = mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) display_mode->hsync_end = mode->hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) display_mode->htotal = mode->htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) display_mode->vdisplay = mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) display_mode->vsync_start = mode->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) display_mode->vsync_end = mode->vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) display_mode->vtotal = mode->vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) display_mode->flags = mode->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) it6161->vic = it6161->source_avi_infoframe.video_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) DRM_INFO("config display mode clk: %d\n", display_mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) DRM_INFO("config display mode hdisplay: %d\n", display_mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) DRM_INFO("config display mode hsync_start: %d\n", display_mode->hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) DRM_INFO("config display mode hsync_end: %d\n", display_mode->hsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) DRM_INFO("config display mode htotal: %d\n", display_mode->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) DRM_INFO("config display mode vdisplay: %d\n", display_mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) DRM_INFO("config display mode vsync_start: %d\n", display_mode->vsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) DRM_INFO("config display mode vsync_end: %d\n", display_mode->vsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) DRM_INFO("config display mode vtotal: %d\n", display_mode->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) DRM_DEV_ERROR(dev, "Failed to send AVI infoframe: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) mutex_unlock(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static void it6161_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) it6161_bridge = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) it6161_debug("%s start", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) mipi_rx_init(it6161);//allen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) hdmi_tx_init(it6161);//allen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) it6161_set_interrupts_active_level(HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) it6161_mipi_rx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) it6161_hdmi_tx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) it6161_debug("%s start restart delayed work\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) schedule_delayed_work(&it6161->restart, msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) //if (enable_de_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) // hdmi_tx_generate_blank_timing(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) //hdmi_tx_video_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) // if (!it6161->enable_drv_hold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) // it6161_int_mask_on(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) // dptx_sys_chg(it6161, SYS_HPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static void it6161_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct it6161 *it6161 = bridge_to_it6161(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) it6161_debug("%s start", __func__);//----TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) mipi_rx_logic_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) hdmi_tx_logic_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) it6161_set_interrupts_active_level(HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) it6161_mipi_rx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) it6161_hdmi_tx_int_mask_enable(it6161);//---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) //kfree(it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) //it6161->edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static const struct drm_bridge_funcs it6161_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .attach = it6161_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .detach = it6161_bridge_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .mode_valid = it6161_bridge_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .mode_set = it6161_bridge_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .enable = it6161_bridge_enable,// set NULL for old linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .disable = it6161_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define InitCEC() it6161_hdmi_tx_write(it6161, 0x8D, (CEC_I2C_SLAVE_ADDR|0x01))//HDMITX_SetI2C_Byte(0x8D, 0x01, 0x01)//HDMITX_SetI2C_Byte(0x0F, 0x08, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define DisableCEC() it6161_hdmi_tx_set_bits(it6161, 0x8D, 0x01, 0x00)//HDMITX_SetI2C_Byte(0x0F, 0x08, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) static bool it6161_check_device_ready(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) u8 Vendor_ID[2], Device_ID[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) Vendor_ID[0] = it6161_mipi_rx_read(it6161, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) Vendor_ID[1] = it6161_mipi_rx_read(it6161, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) Device_ID[0] = it6161_mipi_rx_read(it6161, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) Device_ID[1] = it6161_mipi_rx_read(it6161, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) // Version_ID = MIPIRX_ReadI2C_Byte(0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (Vendor_ID[0] == 0x54 && Vendor_ID[1] == 0x49 && Device_ID[0] == 0x61 && Device_ID[1] == 0x61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) DRM_INFO("Find 6161 revision: 0x%2x", (u32)it6161_mipi_rx_read(it6161, 0x04));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) DRM_INFO("find it6161 Fail");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static u32 hdmi_tx_calc_rclk(struct it6161 *it6161)//in c code: cal_txrclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) // u8 uc ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) long sum = 0, RCLKCNT, TimeLoMax, retry = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) InitCEC();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) // it6161_hdmi_tx_write(it6161, 0x8D, (CEC_I2C_SLAVE_ADDR|0x01));// Enable CRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) // uc = it6161_cec_read(it6161, 0x09) & 0xFE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) it6161_cec_write(it6161, 0x09, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) it6161_cec_write(it6161, 0x09, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) RCLKCNT = it6161_cec_read(it6161, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) RCLKCNT <<= 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) RCLKCNT |= it6161_cec_read(it6161, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) RCLKCNT <<= 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) RCLKCNT |= it6161_cec_read(it6161, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) // DRM_INFO1(("RCLK = %d\n",RCLKCNT) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) sum += RCLKCNT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) sum /= retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) RCLKCNT = sum/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) it6161_cec_write(it6161, 0x0C, (RCLKCNT & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) DisableCEC();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) // it6161->hdmi_tx_rclk = (sum << 4) / 108;//actually nxp platform msleep(100) is 108ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) it6161->hdmi_tx_rclk = (sum << 4) / 104;//actually nxp platform msleep(100) is 108ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) DRM_INFO("hdmi tx rclk = %d.%dMHz", it6161->hdmi_tx_rclk / 1000, it6161->hdmi_tx_rclk % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) TimeLoMax = (sum << 4)/10;//10*TxRCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) // add HDCP TimeLomax over-flow protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if(TimeLoMax>0x3FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) TimeLoMax = 0x3FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) DRM_INFO("TimeLoMax=%08lx\n", TimeLoMax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) it6161_hdmi_tx_write(it6161, 0x47, (TimeLoMax&0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) it6161_hdmi_tx_write(it6161, 0x48, ((TimeLoMax&0xFF00)>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) it6161_hdmi_tx_set_bits(it6161, 0x49, 0x03, ((TimeLoMax&0x30000)>>16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) return it6161->hdmi_tx_rclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static u32 hdmi_tx_calc_pclk(struct it6161 *it6161) //c code void cal_txclk( void )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) u8 uc, RCLKFreqSelRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) int div, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 sum , count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) // uc = it6161_hdmi_tx_read(it6161, 0x5F) & 0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) // if( ! uc )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) // return 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) RCLKFreqSelRead = (it6161_hdmi_tx_read(it6161, 0x5D) & 0x04)>>2;//hdmitxset(0x5D, 0x04, (RCLKFreqSel<<2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) /* PCLK Count Pre-Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) it6161_hdmi_tx_set_bits(it6161, 0xD7, 0xF0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) it6161_hdmi_tx_set_bits(it6161, 0xD7, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) count = it6161_hdmi_tx_read(it6161, 0xD7) & 0xF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) count <<= 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) count |= it6161_hdmi_tx_read(it6161, 0xD8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (RCLKFreqSelRead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) count <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) for ( div = 7 ; div > 0 ; div-- ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (count < (1<<(11-div)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) it6161_hdmi_tx_set_bits(it6161, 0xD7, 0x70, div<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) uc = it6161_hdmi_tx_read(it6161, 0xD7) & 0x7F ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) for( i = 0 , sum = 0 ; i < 100 ; i ++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) it6161_hdmi_tx_write(it6161, 0xD7, uc|0x80) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) it6161_hdmi_tx_write(it6161, 0xD7, uc) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) count = it6161_hdmi_tx_read(it6161, 0xD7) & 0xF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) count <<= 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) count |= it6161_hdmi_tx_read(it6161, 0xD8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (RCLKFreqSelRead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) count <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) sum += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) sum /= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) count = sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) it6161->hdmi_tx_pclk = it6161->hdmi_tx_rclk * 128 / count * 16 ;//128*16=2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) it6161->hdmi_tx_pclk *= (1<<div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) // if( it6161_hdmi_tx_read(it6161, 0x70) & 0x10 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) // it6161->hdmi_tx_pclk /= 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) DRM_INFO("hdmi tx pclk = %d.%dMHz", it6161->hdmi_tx_pclk / 1000, it6161->hdmi_tx_pclk % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) return it6161->hdmi_tx_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static void hdmi_tx_get_display_mode(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) struct drm_display_mode *display_mode = &it6161->hdmi_tx_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) u32 hsyncpol, vsyncpol, interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) u32 htotal, hdes, hdee, hsyncw, hactive, hfront_porch, H2ndVRRise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) u32 vtotal, vdes, vdee, vsyncw, vactive, vfront_porch, vdes2nd, vdee2nd, vsyncw2nd, VRS2nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) u32 vdew2nd, vfph2nd, vbph2nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) u8 rega9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) hdmi_tx_calc_rclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) hdmi_tx_calc_pclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) /* enable video timing read back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) rega9 = it6161_hdmi_tx_read(it6161, 0xa9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) hsyncpol = rega9 & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) vsyncpol = (rega9 & 0x02) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) interlaced = (rega9 & 0x04) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) htotal = hdmi_tx_read_word(it6161, 0x98) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) hdes = hdmi_tx_read_word(it6161, 0x90) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) hdee = hdmi_tx_read_word(it6161, 0x92) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) hsyncw = hdmi_tx_read_word(it6161, 0x94) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) hactive = hdee - hdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) hfront_porch = htotal - hdee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) vtotal = hdmi_tx_read_word(it6161, 0xA6) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) vdes = hdmi_tx_read_word(it6161, 0x9C) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) vdee = hdmi_tx_read_word(it6161, 0x9E) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) vsyncw = it6161_hdmi_tx_read(it6161, 0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) vactive = vdee - vdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) vfront_porch = (interlaced == 0x01) ? (vtotal / 2 - vdee) : (vtotal - vdee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) display_mode->clock = it6161->hdmi_tx_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) display_mode->hdisplay = hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) display_mode->hsync_start = hactive + hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) display_mode->hsync_end = hactive + hfront_porch + hsyncw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) display_mode->htotal = htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) display_mode->vdisplay = vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) display_mode->vsync_start = vactive + vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) display_mode->vsync_end = vactive + vfront_porch + vsyncw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) display_mode->vtotal = vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) display_mode->flags = ((hsyncpol == 0x01) ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) ((vsyncpol == 0x01) ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) ((interlaced == 0x01) ? DRM_MODE_FLAG_INTERLACE : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (interlaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) vdes2nd = hdmi_tx_read_word(it6161, 0xA2) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) vdee2nd = hdmi_tx_read_word(it6161, 0xA4) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) VRS2nd = hdmi_tx_read_word(it6161, 0xB1) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) vsyncw2nd = it6161_hdmi_tx_read(it6161, 0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) H2ndVRRise = hdmi_tx_read_word(it6161, 0x96) & 0x0FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) vdew2nd = vdee2nd-vdes2nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) vfph2nd = VRS2nd-vdee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) vbph2nd = vdes2nd-VRS2nd-vsyncw2nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) DRM_INFO("vdew2nd = %d\n", vdew2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) DRM_INFO("vfph2nd = %d\n", vfph2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) DRM_INFO("VSyncW2nd = %d\n", vsyncw2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) DRM_INFO("vbph2nd = %d\n", vbph2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) DRM_INFO("H2ndVRRise = %d\n", H2ndVRRise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /* disable video timing read back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) static void it6161_hdmi_tx_set_av_mute(struct it6161 *it6161, u8 bEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) it6161_hdmi_tx_set_bits(it6161, REG_TX_GCP,B_TX_SETAVMUTE, bEnable?B_TX_SETAVMUTE:0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) it6161_hdmi_tx_write(it6161, REG_TX_PKT_GENERAL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) #ifdef HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #ifdef SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static u8 SHABuff[64] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static u8 V[20] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static u8 KSVList[32] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static u8 Vr[20] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) static u8 M0[8] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static bool hdmi_tx_hdcp_auth_status(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) return !!(it6161_hdmi_tx_read(it6161, REG_TX_AUTH_STAT) & B_TX_AUTH_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static bool hdmi_tx_hdcp_get_auth_done(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static void hdmi_tx_hdcp_clear_auth_interrupt(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_KSVLISTCHK_MASK | B_TX_AUTH_DONE_MASK | B_TX_AUTH_FAIL_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0, B_TX_CLR_AUTH_FAIL | B_TX_CLR_AUTH_DONE | B_TX_CLR_KSVLISTCHK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS, B_TX_INTACTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) static void hdmi_tx_hdcp_reset_auth(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, B_TX_HDCP_RST_HDMITX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) it6161_hdmi_tx_abort_ddc(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) /* write anything to reg21 to enable HDCP authentication by HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) static void hdmi_tx_hdcp_auth_fire(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHDCP); // MASTERHDCP,no need command but fire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) it6161_hdmi_tx_write(it6161, REG_TX_AUTHFIRE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) * Start the Cipher to free run for random number. When stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) * An is ready in Reg30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) static void hdmi_tx_hdcp_start_an_cipher(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) it6161_hdmi_tx_write(it6161, REG_TX_AN_GENERATE, B_TX_START_CIPHER_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /* Stop the Cipher,and An is ready in Reg30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) static void hdmi_tx_hdcp_stop_an_cipher(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) it6161_hdmi_tx_write(it6161, REG_TX_AN_GENERATE, B_TX_STOP_CIPHER_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * start An ciper random run at first,then stop it. Software can get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * An in reg30~reg38,the write to reg28~2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static void hdmi_tx_hdcp_generate_an(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) u8 an[DRM_HDCP_AN_LEN], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) hdmi_tx_hdcp_start_an_cipher(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) hdmi_tx_hdcp_stop_an_cipher(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) /* new An is ready in reg30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) it6161_hdmi_tx_burst_read(it6161, REG_TX_AN_GEN, an, DRM_HDCP_AN_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) for (i = 0; i < DRM_HDCP_AN_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) it6161_hdmi_tx_write(it6161, REG_TX_AN + i, an[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) * Parameter: pBCaps - pointer of byte to get BCaps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) * pBStatus - pointer of two bytes to get BStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) * Return: ER_SUCCESS if successfully got BCaps and BStatus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) * Remark: get B status and capability from HDCP reciever via DDC bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) static SYS_STATUS hdmi_tx_get_hdcp_bcaps_bstatus(struct it6161 *it6161, u8 *pBCaps, u16 *pBStatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) int ucdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER,DDC_HDCP_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF,0x40); // BCaps offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT,3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) ucdata = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (ucdata < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) DRM_INFO("get bcaps/bstatus failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) return ER_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ucdata = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) *pBStatus = (u16)ucdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) *pBStatus <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) ucdata = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) *pBStatus |= ((u16)ucdata & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) *pBCaps = it6161_hdmi_tx_read(it6161, REG_TX_BCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) *pBCaps = it6161_hdmi_tx_read(it6161, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) *pBStatus = it6161_hdmi_tx_read(it6161, 0x17) & 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) *pBStatus |= (int)(it6161_hdmi_tx_read(it6161, 0x17)&0xFF)<<8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) DRM_INFO("hdmi_tx_get_hdcp_bcaps_bstatus(): ucdata = %02X\n",(int)it6161_hdmi_tx_read(it6161, 0x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) #ifdef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) TxBstatus = *pBStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) return ER_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* Get bksv from HDCP sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static int hdmi_tx_hdcp_get_bksv(struct it6161 *it6161, u8 *bksv, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) #ifdef _SUPPORT_HDMI_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BKSV, size, 0x00, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ret = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) DRM_INFO("ddc get bksv failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_BKSV, bksv, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) DRM_INFO("i2c get bksv failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #ifdef _SUPPORT_HDMI_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) for (timeout = 0; timeout < 5; timeout++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) KSVList[timeout] = *(bksv+timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static u8 countbit(u8 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) u8 i, count ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) for (i = 0, count = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (b & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static void hdmitx_hdcp_CancelRepeaterAuthenticate(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) it6161_debug("hdmitx_hdcp_CancelRepeaterAuthenticate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) it6161_hdmi_tx_abort_ddc(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, B_TX_LISTFAIL | B_TX_LISTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) hdmi_tx_hdcp_clear_auth_interrupt(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static void hdmitx_hdcp_ResumeRepeaterAuthenticate(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHDCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #define WCOUNT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) u32 VH[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) u32 w[WCOUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) #define rol(x,y)(((x)<< (y))| (((u32)x)>> (32-y)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static void SHATransform(u32 * h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) h[0]=0x67452301;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) h[1]=0xefcdab89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) h[2]=0x98badcfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) h[3]=0x10325476;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) h[4]=0xc3d2e1f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) for (t=0; t < 20; t++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) if(t>=16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) w[(t)% WCOUNT]=rol(tmp,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) DRM_INFO("w[%d]=%08X\n",t,w[(t)% WCOUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[3] & ~h[1]))+ h[4] + w[(t)% WCOUNT] + 0x5a827999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) h[4]=h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) h[3]=h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) h[2]=rol(h[1],30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) h[1]=h[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) h[0]=tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) for (t=20; t < 40; t++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) w[(t)% WCOUNT]=rol(tmp,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) DRM_INFO("w[%d]=%08X\n",t,w[(t)% WCOUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0x6ed9eba1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) h[4]=h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) h[3]=h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) h[2]=rol(h[1],30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) h[1]=h[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) h[0]=tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) for (t=40; t < 60; t++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) w[(t)% WCOUNT]=rol(tmp,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) DRM_INFO("w[%d]=%08X\n",t,w[(t)% WCOUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) tmp=rol(h[0],5)+ ((h[1] & h[2])| (h[1] & h[3])| (h[2] & h[3]))+ h[4] + w[(t)% WCOUNT] + 0x8f1bbcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) h[4]=h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) h[3]=h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) h[2]=rol(h[1],30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) h[1]=h[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) h[0]=tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) for (t=60; t < 80; t++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) tmp=w[(t - 3)% WCOUNT] ^ w[(t - 8)% WCOUNT] ^ w[(t - 14)% WCOUNT] ^ w[(t - 16)% WCOUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) w[(t)% WCOUNT]=rol(tmp,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) DRM_INFO("w[%d]=%08X\n",t,w[(t)% WCOUNT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) tmp=rol(h[0],5)+ (h[1] ^ h[2] ^ h[3])+ h[4] + w[(t)% WCOUNT] + 0xca62c1d6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) h[4]=h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) h[3]=h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) h[2]=rol(h[1],30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) h[1]=h[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) h[0]=tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) h[0] +=0x67452301;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) h[1] +=0xefcdab89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) h[2] +=0x98badcfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) h[3] +=0x10325476;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) h[4] +=0xc3d2e1f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) DRM_INFO("%08X %08X %08X %08X %08X\n",h[0],h[1],h[2],h[3],h[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static void SHA_Simple(void *p,u32 len,u8 *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) // SHA_State s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) u32 i,t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) u32 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) u8 *pBuff=p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) for(i=0;i < len;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) t=i/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if(i%4==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) w[t]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) c=pBuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) c <<=(3-(i%4))*8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) w[t] |=c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) DRM_INFO("pBuff[%d]=%02X,c=%08X,w[%d]=%08X\n",(int)i,(int)pBuff[i],c,(int)t,w[t]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) t=i/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) if(i%4==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) w[t]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) //c=0x80 << ((3-i%4)*24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) c=0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) c <<=((3-i%4)*8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) w[t]|=c;t++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) for(; t < 15;t++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) w[t]=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) w[15]=len*8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) for(i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) DRM_INFO("w[%d] = %08X\n",i,w[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) SHATransform(VH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) for(i=0;i < 5;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) output[i*4+3]=(u8)((VH[i]>>24)&0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) output[i*4+2]=(u8)((VH[i]>>16)&0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) output[i*4+1]=(u8)((VH[i]>>8)&0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) output[i*4+0]=(u8)(VH[i]&0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #ifdef SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) static SYS_STATUS hdmitx_hdcp_CheckSHA(u8 pM0[],u16 BStatus,u8 pKSVList[],int cDownStream,u8 Vr[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) int i,n ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) for(i = 0 ; i < cDownStream*5 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) SHABuff[i] = pKSVList[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) SHABuff[i++] = BStatus & 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) SHABuff[i++] = (BStatus>>8) & 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) for(n = 0 ; n < 8 ; n++,i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) SHABuff[i] = pM0[n] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) n = i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) // SHABuff[i++] = 0x80 ; // end mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) for(; i < 64 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) SHABuff[i] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) // n = cDownStream * 5 + 2 /* for BStatus */ + 8 /* for M0 */ ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) // n *= 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) // SHABuff[62] = (n>>8) & 0xff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) // SHABuff[63] = (n>>8) & 0xff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) for(i = 0 ; i < 64 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) if(i % 16 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) DRM_INFO("SHA[]: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) DRM_INFO(" %02X",SHABuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if((i%16)==15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) DRM_INFO("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) SHA_Simple(SHABuff,n,V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) for(i = 0 ; i < 20 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) if(V[i] != Vr[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) DRM_INFO("V[] =");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) for(i = 0 ; i < 20 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) DRM_INFO(" %02X",(int)V[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) DRM_INFO("\nVr[] =");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) for(i = 0 ; i < 20 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) DRM_INFO(" %02X",(int)Vr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #endif // SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static SYS_STATUS hdmi_tx_hdcp_get_ksv_list(struct it6161 *it6161, u8 *pKSVList,u8 cDownStream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) u8 timeout = 100, ucdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) if( cDownStream == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if( /* cDownStream == 0 || */ pKSVList == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT, cDownStream * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) ucdata = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) if (ucdata < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) DRM_INFO("hdmi_tx_hdcp_get_ksv_list(): KSV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) for(timeout = 0 ; timeout < cDownStream * 5 ; timeout++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) pKSVList[timeout] = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) #ifdef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) KSVList[timeout] = pKSVList[timeout];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) DRM_INFO(" %x",(int)pKSVList[timeout]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) DRM_INFO(" %02X",(int)pKSVList[timeout]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static SYS_STATUS hdmitx_hdcp_GetVr(struct it6161 *it6161, u8 *pVr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) u8 timeout, ucdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) if(pVr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER,0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF,0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT,20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) ucdata = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (ucdata < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) DRM_INFO("hdmitx_hdcp_GetVr(): DDC fail by timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) for(timeout = 0 ; timeout < 5 ; timeout++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL ,timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) pVr[timeout*4] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) pVr[timeout*4+1] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) pVr[timeout*4+2] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) pVr[timeout*4+3] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) // DRM_INFO("V' = %02X %02X %02X %02X\n",(int)pVr[timeout*4],(int)pVr[timeout*4+1],(int)pVr[timeout*4+2],(int)pVr[timeout*4+3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) static SYS_STATUS hdmitx_hdcp_GetM0(struct it6161 *it6161, u8 *pM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if(!pM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,5); // read m0[31:0] from reg51~reg54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) pM0[0] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) pM0[1] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) pM0[2] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) pM0[3] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,0); // read m0[39:32] from reg55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) pM0[4] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,1); // read m0[47:40] from reg55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) pM0[5] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,2); // read m0[55:48] from reg55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) pM0[6] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,3); // read m0[63:56] from reg55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) pM0[7] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) DRM_INFO("M[] =");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) for(i = 0 ; i < 8 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) DRM_INFO("0x%02x,",(int)pM0[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) DRM_INFO("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #ifdef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) static void TxHDCP_chg(HDMITX_HDCP_State state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) if( state == hdmiTxDev[0].TxHDCP_State )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) DRM_INFO("TxHDCP %d -> %d\n",hdmiTxDev[0].TxHDCP_State,state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) hdmiTxDev[0].TxHDCP_State = state ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) switch(state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) case TxHDCP_Off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) hdmiTxDev[0].bAuthenticated=false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) hdmiTxDev[0].usHDCPTimeOut = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) case TxHDCP_AuthRestart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) hdmiTxDev[0].usHDCPTimeOut = 5 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) case TxHDCP_AuthStart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) hdmiTxDev[0].usHDCPTimeOut = 80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) case TxHDCP_Receiver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) hdmiTxDev[0].usHDCPTimeOut = 250 ; // set the count as the 5000ms/interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) case TxHDCP_Repeater:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) hdmiTxDev[0].usHDCPTimeOut = 250 ; // set the count as the 5000ms/interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) case TxHDCP_CheckFIFORDY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) hdmiTxDev[0].usHDCPTimeOut = 300 ; // set the count as the 6000ms/interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) case TxHDCP_VerifyRevocationList:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) case TxHDCP_AuthFail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) case TxHDCP_RepeaterFail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) hdmitx_hdcp_CancelRepeaterAuthenticate(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) case TxHDCP_RepeaterSuccess:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) hdmitx_hdcp_ResumeRepeaterAuthenticate(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) case TxHDCP_Authenticated:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) it6161_hdmi_tx_set_av_mute(it6161, false) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) hdmiTxDev[0].bAuthenticated = true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static void TxHDCP_fsm()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) u8 ucdata ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) static u8 BCaps ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) static u16 BStatus ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) static u8 cDownStream ;// this value will be use in the function....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) static u8 bksv[5] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) switch(hdmiTxDev[0].TxHDCP_State)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) case TxHDCP_Off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) case TxHDCP_AuthRestart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) if(hdmiTxDev[0].usHDCPTimeOut>0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) hdmiTxDev[0].usHDCPTimeOut -- ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) if( hdmiTxDev[0].usHDCPTimeOut == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) TxHDCP_chg(TxHDCP_AuthStart) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) case TxHDCP_AuthStart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) cDownStream = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) if(hdmiTxDev[0].usHDCPTimeOut>0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) hdmiTxDev[0].usHDCPTimeOut -- ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) ucdata = it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)& (B_TX_HPDETECT|B_TX_RXSENDETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) if(ucdata != (B_TX_HPDETECT|B_TX_RXSENDETECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) // if no Rx sense, do not start authentication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) // Eventhough start it, cannot work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) != ER_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) DRM_INFO("hdmi_tx_get_hdcp_bcaps_bstatus fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) // wait for HDMI State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) if(B_TX_HDMI_MODE == (it6161_hdmi_tx_read(it6161, REG_TX_HDMI_MODE) & B_TX_HDMI_MODE ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if((BStatus & B_TX_CAP_HDMI_MODE)!=B_TX_CAP_HDMI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) if((BStatus & B_TX_CAP_HDMI_MODE)==B_TX_CAP_HDMI_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) TxHDCP_chg(TxHDCP_AuthRestart) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) DRM_INFO("BCAPS = %x BSTATUS = %X\n", (int)BCaps, BStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) hdmi_tx_hdcp_get_bksv(it6161, bksv, ARRAY_SIZE(bksv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) DRM_INFO("bksv %X %X %X %X %X\n",(int)bksv[0],(int)bksv[1],(int)bksv[2],(int)bksv[3],(int)bksv[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) for(i = 0, ucdata = 0 ; i < 5 ; i ++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) ucdata += countbit(bksv[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) if( ucdata != 20 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) DRM_INFO("countbit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) TxHDCP_chg(TxHDCP_AuthFail) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) it6161_hdmi_tx_change_bank(it6161, 0); // switch bank action should start on direct register writting of each function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE,8|B_TX_CPDESIRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) hdmi_tx_hdcp_clear_auth_interrupt(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) hdmi_tx_hdcp_generate_an(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) hdmi_tx_hdcp_auth_fire(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) hdmiTxDev[0].Tx_BStatus = BStatus ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) if(BCaps & B_TX_CAP_HDMI_REPEATER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) TxHDCP_chg(TxHDCP_Repeater) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) for(i = 0; i < 5 ; i ++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) KSVList[i] = bksv[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) TxHDCP_chg(TxHDCP_Receiver) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) case TxHDCP_Receiver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) if(hdmiTxDev[0].usHDCPTimeOut >0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) hdmiTxDev[0].usHDCPTimeOut -- ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) if(hdmiTxDev[0].usHDCPTimeOut==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) TxHDCP_chg(TxHDCP_AuthFail) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) DRM_INFO("[Fsm] Receiver: usHDCPTimeOut = %d\n",hdmiTxDev[0].usHDCPTimeOut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) ucdata = it6161_hdmi_tx_read(it6161, REG_TX_AUTH_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) DRM_INFO("[Fsm] Receiver: ucdata = %X, BStatus = %X\n",ucdata,BStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) if(ucdata & B_TX_AUTH_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) //BStatus += 0x101 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) IT680X_DownStream_AuthDoneCallback(bksv, BStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) TxHDCP_chg(TxHDCP_Authenticated) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) case TxHDCP_Repeater:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if(hdmiTxDev[0].usHDCPTimeOut >0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) hdmiTxDev[0].usHDCPTimeOut -- ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if(hdmiTxDev[0].usHDCPTimeOut==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) TxHDCP_chg(TxHDCP_AuthFail) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) case TxHDCP_CheckFIFORDY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if(hdmiTxDev[0].usHDCPTimeOut >0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) hdmiTxDev[0].usHDCPTimeOut -- ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if(hdmiTxDev[0].usHDCPTimeOut==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) TxHDCP_chg(TxHDCP_RepeaterFail) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) DRM_INFO("Get BCaps fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) break ; // get fail, again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) if(BCaps & B_TX_CAP_KSV_FIFO_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) DRM_INFO("FIFO Ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) it6161_hdmi_tx_generate_ddc_sclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) hdmiTxDev[0].Tx_BStatus = BStatus ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) cDownStream=(BStatus & M_TX_DOWNSTREAM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) //+++++++++++++++++++++++++++++++++++++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) DRM_INFO("Downstream=%X \n",cDownStream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) if( cDownStream > (MAX_REPEATER_DOWNSTREAM_COUNT-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) hdmiTxDev[0].Tx_BStatus |= B_TX_DOWNSTREAM_OVER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if( cDownStream > (MAX_REPEATER_DOWNSTREAM_COUNT-1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) BStatus & (B_TX_MAX_CASCADE_EXCEEDED|B_TX_DOWNSTREAM_OVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) DRM_INFO("Invalid Down stream count,fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) // RxAuthSetBStatus(B_DOWNSTREAM_OVER|B_MAX_CASCADE_EXCEEDED); //for ALLION HDCP 3C-2-06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) // ForceKSVFIFOReady(B_DOWNSTREAM_OVER|B_MAX_CASCADE_EXCEEDED) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) IT680X_DownStream_AuthDoneCallback(KSVList, 0xFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) TxHDCP_chg(TxHDCP_RepeaterFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) TxHDCP_chg(TxHDCP_VerifyRevocationList) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) case TxHDCP_VerifyRevocationList:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) #ifdef SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) DRM_INFO("TxHDCP_VerifyRevocationList: cDownStream = %d",cDownStream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) if(hdmi_tx_hdcp_get_ksv_list(it6161, KSVList,cDownStream) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) DRM_INFO("hdmitx_hdcp_Repeater_Fail 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) TxHDCP_chg(TxHDCP_RepeaterFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if(hdmitx_hdcp_GetVr(it6161, Vr) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) DRM_INFO("hdmitx_hdcp_Repeater_Fail 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) TxHDCP_chg(TxHDCP_RepeaterFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if(hdmitx_hdcp_GetM0(it6161, M0) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) DRM_INFO("hdmitx_hdcp_Repeater_Fail 4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) TxHDCP_chg(TxHDCP_RepeaterFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) // do check SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if(hdmitx_hdcp_CheckSHA(M0,BStatus,KSVList,cDownStream,Vr) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) DRM_INFO("hdmitx_hdcp_Repeater_Fail 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) TxHDCP_chg(TxHDCP_RepeaterFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) #endif // SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) // checkSHA success, append the bksv to KSV List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) for(i = 0; i < 5 ; i ++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) KSVList[cDownStream*5+i] = bksv[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) for( i = 0 ; i < ((cDownStream+1)*5) ; i ++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) DRM_INFO("KSVLIST[%d] = %X\n",i,KSVList[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) //BStatus += 0x101 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) IT680X_DownStream_AuthDoneCallback(KSVList, BStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) TxHDCP_chg(TxHDCP_RepeaterSuccess) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) case TxHDCP_Authenticated:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) case TxHDCP_AuthFail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) // force revoke the KSVList
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) // IT680X_DownStream_AuthDoneCallback(KSVList, 0xFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) TxHDCP_chg(TxHDCP_AuthRestart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) case TxHDCP_RepeaterFail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) TxHDCP_chg(TxHDCP_AuthFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) case TxHDCP_RepeaterSuccess:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) TxHDCP_chg(TxHDCP_Authenticated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) // Function: hdmi_tx_hdcp_auth_process_Repeater
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) // Parameter: BCaps and BStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) // Return: ER_SUCCESS if success,if AUTH_FAIL interrupt status,return fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) // Remark:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) // Side-Effect: as Authentication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) #ifdef HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) static SYS_STATUS hdmi_tx_hdcp_auth_process_Repeater(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) u8 uc ,ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) // u8 revoked ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) // int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) u8 cDownStream ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) u8 BCaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) u16 BStatus ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) u16 timeout ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) DRM_INFO("Authentication for repeater\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) // emily add for test,abort HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) // 2007/10/01 marked by jj_tseng@chipadvanced.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) // it6161_hdmi_tx_write(it6161, 0x20,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) // it6161_hdmi_tx_write(it6161, 0x04,0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) // it6161_hdmi_tx_write(it6161, 0x10,0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) // it6161_hdmi_tx_write(it6161, 0x15,0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) // msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) // it6161_hdmi_tx_write(it6161, 0x04,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) // it6161_hdmi_tx_write(it6161, 0x10,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) // it6161_hdmi_tx_write(it6161, 0x20,0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) // msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) // test07 = it6161_hdmi_tx_read(it6161, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) // test06 = it6161_hdmi_tx_read(it6161, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) // test08 = it6161_hdmi_tx_read(it6161, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) //~jj_tseng@chipadvanced.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) // end emily add for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) //////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) // Authenticate Fired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) //////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) DRM_INFO("HPD Before Fire Auth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) hdmi_tx_hdcp_auth_fire(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) //msleep(550); // emily add for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) for(ii=0;ii<55;ii++) //msleep(550); // emily add for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) for(timeout = /*250*6*/10 ; timeout > 0 ; timeout --)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) DRM_INFO("timeout = %d wait part 1\n",timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) DRM_INFO("HPD at wait part 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) uc = it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) if(uc & B_TX_INT_DDC_BUS_HANG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) DRM_INFO("DDC Bus hang\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) uc = it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) if(uc & B_TX_INT_AUTH_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0,B_TX_CLR_AUTH_FAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,B_TX_INTACTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) DRM_INFO("hdmi_tx_hdcp_auth_process_Repeater(): B_TX_INT_AUTH_FAIL.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) // emily add for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) // test =(it6161_hdmi_tx_read(it6161, 0x7)&0x4)>>2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) if(uc & B_TX_INT_KSVLIST_CHK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0,B_TX_CLR_KSVLISTCHK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,B_TX_INTACTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) DRM_INFO("B_TX_INT_KSVLIST_CHK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) if(timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) DRM_INFO("Time out for wait KSV List checking interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) ///////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) // clear KSVList check interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ///////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) for(timeout = 500 ; timeout > 0 ; timeout --)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) DRM_INFO("timeout=%d at wait FIFO ready\n",timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) DRM_INFO("HPD at wait FIFO ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) DRM_INFO("Get BCaps fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) if(BCaps & B_TX_CAP_KSV_FIFO_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) DRM_INFO("FIFO Ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) if(timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) DRM_INFO("Get KSV FIFO ready timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) DRM_INFO("Wait timeout = %d\n",timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) it6161_hdmi_tx_generate_ddc_sclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) cDownStream = (BStatus & M_TX_DOWNSTREAM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) if(/*cDownStream == 0 ||*/ cDownStream > 6 || BStatus & (B_TX_MAX_CASCADE_EXCEEDED|B_TX_DOWNSTREAM_OVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) DRM_INFO("Invalid Down stream count,fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) #ifdef SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) if(hdmi_tx_hdcp_get_ksv_list(it6161, KSVList,cDownStream) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) for(i = 0 ; i < cDownStream ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) revoked=false ; uc = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) for( timeout = 0 ; timeout < 5 ; timeout++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) // check bit count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) uc += countbit(KSVList[i*5+timeout]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) if( uc != 20 ) revoked = true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) if(revoked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) DRM_INFO("KSVFIFO[%d] = %02X %02X %02X %02X %02X is revoked\n",i,(int)KSVList[i*5],(int)KSVList[i*5+1],(int)KSVList[i*5+2],(int)KSVList[i*5+3],(int)KSVList[i*5+4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) if(hdmitx_hdcp_GetVr(it6161, Vr) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) if(hdmitx_hdcp_GetM0(it6161, M0) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) // do check SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) if(hdmitx_hdcp_CheckSHA(M0,BStatus,KSVList,cDownStream,Vr) == ER_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) DRM_INFO("HPD at Final\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) goto hdmitx_hdcp_Repeater_Fail ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) #endif // SUPPORT_SHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) hdmitx_hdcp_ResumeRepeaterAuthenticate(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) hdmiTxDev[0].bAuthenticated = true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) hdmitx_hdcp_Repeater_Fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) hdmitx_hdcp_CancelRepeaterAuthenticate(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) static int hdmi_tx_hdcp_get_m0(struct it6161 *it6161, u8 *m0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) if(!m0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) /* read m0[31:0] from reg51~reg54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_SHA_RD_BYTE1, m0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) DRM_INFO("i2c read m0 failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /* read m0[39 + i * 8 : 32 + i * 8] from reg55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) m0[4 + i] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) static int hdmi_tx_hdcp_get_bcaps(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BCAPS, 0x01, 0x00, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) ret = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) DRM_INFO("ddc get bcaps failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) ret = it6161_hdmi_tx_read(it6161, REG_TX_BCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) DRM_INFO("i2c get bcaps failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) static int hdmi_tx_hdcp_get_bstatus(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) int ret, bstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BSTATUS, 0x02, 0x00, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) ret = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) DRM_INFO("ddc get bstatus failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) ret = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) DRM_INFO("i2c get bstatus failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) bstatus = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) ret = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) DRM_INFO("i2c get bstatus failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) bstatus |= ret << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) return bstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) static void hdmi_tx_hdcp_show_ksv_list(struct it6161 *it6161, u8 *ksvlist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) for (i = 0; i < it6161->hdcp_downstream_count; i++, ksvlist += DRM_HDCP_KSV_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) DRM_INFO("device%d ksv:0x %*ph", i, DRM_HDCP_KSV_LEN, ksvlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) static int hdmi_tx_hdcp_get_ksv_list1(struct it6161 *it6161, u8 *ksvlist, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_KSV_FIFO, size, 0x00, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) ret = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) DRM_INFO("ddc get ksv list failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) ret = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) DRM_INFO("i2c get ksv list failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) ksvlist[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) static int hdmi_tx_hdcp_get_v_prime(struct it6161 *it6161, u8 *v_prime, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_V_PRIME(0), size, 0x00, CMD_DDC_SEQ_BURSTREAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) ret = it6161_ddc_wait(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) DRM_INFO("ddc get v prime failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) for(i = 0 ; i < DRM_HDCP_V_PRIME_NUM_PARTS ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL ,i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_SHA_RD_BYTE1, v_prime, DRM_HDCP_V_PRIME_PART_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) DRM_INFO("i2c get v prime failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) v_prime += DRM_HDCP_V_PRIME_PART_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) static int hdmi_tx_setup_sha1_input(struct it6161 *it6161, u8 *ksvlist, u8 *sha1_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) u8 i, m0[8], msg_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) hdmi_tx_hdcp_get_m0(it6161, m0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) for (i = 0; i < it6161->hdcp_downstream_count * DRM_HDCP_KSV_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) sha1_input[i] = ksvlist[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) msg_count += i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) sha1_input[msg_count++] = (u8)it6161->bstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) sha1_input[msg_count++] = (u8)(it6161->bstatus >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) while (i < ARRAY_SIZE(m0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) sha1_input[msg_count++] = m0[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) return msg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) static int it6161_sha1_digest(struct it6161 *it6161, u8 *sha1_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) unsigned int size, u8 *output_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) struct shash_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) struct crypto_shash *tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) tfm = crypto_alloc_shash("sha1", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) if (IS_ERR(tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) DRM_DEV_ERROR(dev, "crypto_alloc_shash sha1 failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) return PTR_ERR(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) crypto_free_shash(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) desc->tfm = tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) err = crypto_shash_digest(desc, sha1_input, size, output_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) DRM_DEV_ERROR(dev, "crypto_shash_digest sha1 failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) crypto_free_shash(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) static bool hdmi_tX_hdcp_compare_sha1_v_prime_v(struct it6161 *it6161, u8 *v_array, u8 *v_prime_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) u8 (*v)[DRM_HDCP_V_PRIME_PART_LEN] = (u8 (*)[DRM_HDCP_V_PRIME_PART_LEN])v_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) u8 (*v_prime)[DRM_HDCP_V_PRIME_PART_LEN] = (u8 (*)[DRM_HDCP_V_PRIME_PART_LEN])v_prime_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) for (j = 0; j < DRM_HDCP_V_PRIME_PART_LEN; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) if (v[i][j] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) v_prime[i][DRM_HDCP_V_PRIME_PART_LEN - 1- j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) static void hdmi_tx_hdcp_auth_part2_process(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) struct it6161 *it6161 = container_of(work, struct it6161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) wait_hdcp_ksv_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) int timeout = 5000, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) //u8 bcaps, ksvlist[DRM_HDCP_KSV_LEN * it6161->hdcp_downstream_count], *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) u8 bcaps, ksvlist[DRM_HDCP_KSV_LEN], *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) u8 v[DRM_HDCP_V_PRIME_NUM_PARTS][DRM_HDCP_V_PRIME_PART_LEN], v_prime[DRM_HDCP_V_PRIME_NUM_PARTS][DRM_HDCP_V_PRIME_PART_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) while (timeout > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) if (!hdmi_tx_get_sink_hpd(it6161))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) ret = hdmi_tx_hdcp_get_bcaps(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) bcaps = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) if (!!(bcaps & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) DRM_INFO("ksv list fifo ready");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) if (timeout <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) DRM_INFO("wait ksv list ready timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) ret = hdmi_tx_hdcp_get_ksv_list1(it6161, ksvlist, ARRAY_SIZE(ksvlist));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) hdmi_tx_hdcp_show_ksv_list(it6161, ksvlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) ret = hdmi_tx_setup_sha1_input(it6161, ksvlist, it6161->sha1_transform_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) DRM_INFO("sha1 msg_count :%d \nsha1_input:0x %*ph", ret, ret, it6161->sha1_transform_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) ret = it6161_sha1_digest(it6161, it6161->sha1_transform_input, ret, (u8 *)v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) tmp = (u8 *)v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++, tmp += DRM_HDCP_V_PRIME_PART_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) DRM_INFO("v:0x %*ph", DRM_HDCP_V_PRIME_PART_LEN, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) ret = hdmi_tx_hdcp_get_v_prime(it6161, (u8 *)v_prime, sizeof(v_prime));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) tmp = (u8 *)v_prime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++, tmp += DRM_HDCP_V_PRIME_PART_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) DRM_INFO("v_prime:0x %*ph", DRM_HDCP_V_PRIME_PART_LEN, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) ret = hdmi_tX_hdcp_compare_sha1_v_prime_v(it6161, (u8 *)v, (u8 *)v_prime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) DRM_INFO("sha1 check result: %s", ret ? "pass" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE , B_TX_LISTDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE | B_TX_LISTFAIL, B_TX_LISTDONE | B_TX_LISTFAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE | B_TX_LISTFAIL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) static bool hdmi_tx_hdcp_enable_auth_part1(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) u8 i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) ret = hdmi_tx_hdcp_get_bksv(it6161, it6161->bksv, (int)ARRAY_SIZE(it6161->bksv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) DRM_INFO("bksv: 0x %*ph", (int)ARRAY_SIZE(it6161->bksv), it6161->bksv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) for (i = 0; i < ARRAY_SIZE(it6161->bksv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) count += countbit(it6161->bksv[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) if (count != 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) DRM_INFO("not a valid bksv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) if ((it6161->bksv[4] == 0x93) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) (it6161->bksv[3] == 0x43) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) (it6161->bksv[2] == 0x5C) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) (it6161->bksv[1] == 0xDE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) (it6161->bksv[0] == 0x23)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) DRM_INFO("Revoked bksv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) return hdmiTxDev[0].bAuthenticated ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE, 0x08 | B_TX_CPDESIRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) hdmi_tx_hdcp_generate_an(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) hdmi_tx_hdcp_auth_fire(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) static bool hdmi_tx_hdcp_auth_process(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) u8 bcaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) u16 i, retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) /* Authenticate should be called after AFE setup up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) DRM_INFO("start");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) hdmiTxDev[0].bAuthenticated = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) it6161->hdmi_tx_hdcp_retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) hdmi_tx_hdcp_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) ret = hdmi_tx_hdcp_get_bstatus(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) if(ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) it6161->bstatus = (u16)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) ret = hdmi_tx_hdcp_get_bcaps(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) bcaps = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) if (i == retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) DRM_INFO("bcaps: 0x%02x, bstatus: 0x%04x, hdmi_mode: %d", bcaps, it6161->bstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) it6161->bstatus & B_TX_CAP_HDMI_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) it6161->is_repeater = !!(bcaps & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) DRM_INFO("downstream is hdcp %s", it6161->is_repeater ? "repeater" : "receiver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) if (it6161->is_repeater) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) it6161->hdcp_downstream_count = (u8)DRM_HDCP_NUM_DOWNSTREAM(it6161->bstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) DRM_INFO("down stream Count %d", it6161->hdcp_downstream_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) if (it6161->hdcp_downstream_count > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) DRM_INFO("over maximum supported number 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) ret = hdmi_tx_hdcp_enable_auth_part1(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) if (!it6161->is_repeater) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) ret = wait_for_completion_timeout(&it6161->wait_hdcp_event, msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) DRM_INFO("completion:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) DRM_INFO("hdcp-receiver: timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) return hdmiTxDev[0].bAuthenticated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) static void hdmitx_hdcp_ResumeAuthentication(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) it6161_hdmi_tx_set_av_mute(it6161, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) if(hdmi_tx_hdcp_auth_process(it6161) == ER_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) it6161_hdmi_tx_set_av_mute(it6161, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) static void hdmi_tx_hdcp_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) struct it6161 *it6161 = container_of(work, struct it6161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) hdcp_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) //struct device *dev = &it6161->i2c_hdmi_tx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) bool ret, sink_hpd = hdmi_tx_get_sink_hpd(it6161), video_state = hdmi_tx_get_video_state(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) if (it6161->hdmi_tx_hdcp_retry <= 0 || !sink_hpd || !video_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) DRM_INFO("hdcp_retry:%d sink_hpd:%d video_stable_state:%d", it6161->hdmi_tx_hdcp_retry, sink_hpd, video_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) ret = hdmi_tx_hdcp_auth_process(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (it6161->is_repeater) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) DRM_INFO("is repeater and wait for ksv list interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) DRM_INFO("hdcp_auth_process %s", ret ? "pass" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) static void hdmi_tx_enable_hdcp(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) struct device *dev = &it6161->i2c_hdmi_tx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) DRM_DEV_DEBUG_DRIVER(dev, "start");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) queue_delayed_work(system_wq, &it6161->hdcp_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) static bool getHDMITX_LinkStatus()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) it6161_debug("%s reg0E:0x%02x reg0x61:0x%02x", __func__, it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS), it6161_hdmi_tx_read(it6161, REG_TX_AFE_DRV_CTRL));//allen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) if(B_TX_RXSENDETECT & it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) if(0==it6161_hdmi_tx_read(it6161, REG_TX_AFE_DRV_CTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) //DRM_INFO("getHDMITX_LinkStatus()!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) DRM_INFO("GetTMDS not Ready()!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) // static void HDMITX_PowerDown()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) // it6161_hdmi_tx_write_table(it6161, HDMITX_PwrDown_Table, ARRAY_SIZE(HDMITX_PwrDown_Table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) static void hdmi_tx_setup_pclk_div2(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) if (HDMI_TX_PCLK_DIV2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) DRM_INFO("PCLK Divided by 2 mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) it6161_hdmi_tx_set_bits(it6161, REG_TX_INPUT_MODE, B_TX_PCLKDIV2, B_TX_PCLKDIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) // Function: hdmi_tx_setup_csc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) // Parameter: input_mode -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) // D[1:0] - Color Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) // D[4] - Colorimetry 0: ITU_BT601 1: ITU_BT709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) // D[5] - Quantization 0: 0_255 1: 16_235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) // D[6] - Up/Dn Filter 'Required'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) // 0: no up/down filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) // 1: enable up/down filter when csc need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) // D[7] - Dither Filter 'Required'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) // 0: no dither enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) // 1: enable dither and dither free go "when required".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) // output_mode -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) // D[1:0] - Color mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) // Return: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) // Remark: reg72~reg8D will be programmed depended the input with table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) // Side-Effect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) static void hdmi_tx_setup_csc(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) u8 ucData, csc = 0, i, filter = 0; // filter is for Video CTRL DN_FREE_GO,EN_DITHER,and ENUDFILT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) u8 input_mode = it6161->hdmi_tx_input_color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) u8 output_mode = it6161->hdmi_tx_output_color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) // (1) YUV422 in,RGB/YUV444 output (Output is 8-bit,input is 12-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) // (2) YUV444/422 in,RGB output (CSC enable,and output is not YUV422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) // (3) RGB in,YUV444 output (CSC enable,and output is not YUV422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) // YUV444/RGB24 <-> YUV422 need set up/down filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) DRM_INFO("hdmi_tx_setup_csc(u8 input_mode = %x,u8 output_mode = %x)\n", (int)input_mode, (int)output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) switch(input_mode&F_MODE_CLRMOD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) #ifdef SUPPORT_INPUTYUV444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) case F_MODE_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) DRM_INFO("Input mode is YUV444 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) switch(output_mode&F_MODE_CLRMOD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) case F_MODE_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) DRM_INFO("Output mode is YUV444\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) case F_MODE_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) DRM_INFO("Output mode is YUV422\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) if(input_mode & F_VIDMODE_EN_UDFILT) // YUV444 to YUV422 need up/down filter for processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) filter |= B_TX_EN_UDFILTER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) case F_MODE_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) DRM_INFO("Output mode is RGB24\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) csc = B_HDMITX_CSC_YUV2RGB ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) if(input_mode & F_VIDMODE_EN_DITHER) // YUV444 to RGB24 need dither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) #ifdef SUPPORT_INPUTYUV422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) case F_MODE_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) DRM_INFO("Input mode is YUV422\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) switch(output_mode&F_MODE_CLRMOD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) case F_MODE_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) DRM_INFO("Output mode is YUV444\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) if(input_mode & F_VIDMODE_EN_UDFILT) // YUV422 to YUV444 need up filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) filter |= B_TX_EN_UDFILTER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) if(input_mode & F_VIDMODE_EN_DITHER) // YUV422 to YUV444 need dither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) case F_MODE_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) DRM_INFO("Output mode is YUV422\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) case F_MODE_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) DRM_INFO("Output mode is RGB24\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) csc = B_HDMITX_CSC_YUV2RGB ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) if(input_mode & F_VIDMODE_EN_UDFILT) // YUV422 to RGB24 need up/dn filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) filter |= B_TX_EN_UDFILTER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) if(input_mode & F_VIDMODE_EN_DITHER) // YUV422 to RGB24 need dither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) #ifdef SUPPORT_INPUTRGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) case F_MODE_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) DRM_INFO("Input mode is RGB24\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) switch(output_mode&F_MODE_CLRMOD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) case F_MODE_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) DRM_INFO("Output mode is YUV444\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) csc = B_HDMITX_CSC_RGB2YUV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) if(input_mode & F_VIDMODE_EN_DITHER) // RGB24 to YUV444 need dither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) case F_MODE_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) DRM_INFO("Output mode is YUV422\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) if(input_mode & F_VIDMODE_EN_UDFILT) // RGB24 to YUV422 need down filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) filter |= B_TX_EN_UDFILTER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) if(input_mode & F_VIDMODE_EN_DITHER) // RGB24 to YUV422 need dither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) filter |= B_TX_EN_DITHER | B_TX_DNFREE_GO ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) csc = B_HDMITX_CSC_RGB2YUV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) case F_MODE_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) DRM_INFO("Output mode is RGB24\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) #ifndef DISABLE_HDMITX_CSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) #ifdef SUPPORT_INPUTRGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) // set the CSC metrix registers by colorimetry and quantization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) if(csc == B_HDMITX_CSC_RGB2YUV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) DRM_INFO("CSC = RGB2YUV %x ",csc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) switch(input_mode&(F_VIDMODE_ITU709|F_VIDMODE_16_235))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) case F_VIDMODE_ITU709|F_VIDMODE_16_235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) DRM_INFO("ITU709 16-235 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU709_16_235[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU709_16_235[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) case F_VIDMODE_ITU709|F_VIDMODE_0_255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) DRM_INFO("ITU709 0-255 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU709_0_255[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU709_0_255[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) case F_VIDMODE_ITU601|F_VIDMODE_16_235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) DRM_INFO("ITU601 16-235 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU601_16_235[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU601_16_235[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) case F_VIDMODE_ITU601|F_VIDMODE_0_255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) DRM_INFO("ITU601 0-255 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB2YUV_ITU601_0_255[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_RGB2YUV_ITU601_0_255[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) #ifdef SUPPORT_INPUTYUV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) if (csc == B_HDMITX_CSC_YUV2RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) DRM_INFO("CSC = YUV2RGB %x ",csc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) switch(input_mode&(F_VIDMODE_ITU709|F_VIDMODE_16_235))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) case F_VIDMODE_ITU709|F_VIDMODE_16_235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) DRM_INFO("ITU709 16-235 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU709_16_235[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU709_16_235[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) case F_VIDMODE_ITU709|F_VIDMODE_0_255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) DRM_INFO("ITU709 0-255 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU709_0_255[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU709_0_255[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) case F_VIDMODE_ITU601|F_VIDMODE_16_235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) DRM_INFO("ITU601 16-235 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU601_16_235[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU601_16_235[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) case F_VIDMODE_ITU601|F_VIDMODE_0_255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) DRM_INFO("ITU601 0-255 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV2RGB_ITU601_0_255[i]) ; DRM_INFO("reg%02X <- %02X\n",(int)(i+REG_TX_CSC_YOFF),(int)bCSCMtx_YUV2RGB_ITU601_0_255[i]);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) #else// DISABLE_HDMITX_CSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) csc = B_HDMITX_CSC_BYPASS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) #endif// DISABLE_HDMITX_CSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) if( csc == B_HDMITX_CSC_BYPASS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) ucData = it6161_hdmi_tx_read(it6161, REG_TX_CSC_CTRL) & ~(M_TX_CSC_SEL|B_TX_DNFREE_GO|B_TX_EN_DITHER|B_TX_EN_UDFILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) ucData |= filter|csc ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) it6161_hdmi_tx_write(it6161, REG_TX_CSC_CTRL,ucData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) // Parameter: VIDEOPCLKLEVEL level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) // PCLK_LOW - for 13.5MHz (for mode less than 1080p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) // PCLK MEDIUM - for 25MHz~74MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) // PCLK HIGH - PCLK > 80Hz (for 1080p mode or above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) // Remark: set reg62~reg65 depended on HighFreqMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) // reg61 have to be programmed at last and after video stable input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) static void hdmi_tx_setup_afe(struct it6161 *it6161, VIDEOPCLKLEVEL level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, B_TX_AFE_DRV_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) switch(level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) case PCLK_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) it6161_hdmi_tx_set_bits(it6161, 0x66, 0x80, 0x80);//hdmitxset(0x66, 0x80, 0x80);// mark fix 6017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) DRM_INFO("setup afe: %s", level ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) #ifdef REDUCE_HDMITX_SRC_JITTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) //it6161_hdmi_tx_set_bits(it6161, 0x64, 0x01, 0x00); //pet: TODO need check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) // it6161_hdmi_tx_set_bits(it6161, 0x6A, 0xFF, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) // 2019/02/15 modified by jjtseng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) // Dr. Liu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) // it6161 �b�� Solomon mipi TX (�Ψ�Ljitter �ܤj��source��), �Х[�H�U�]�w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) // reg[6A]=0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) // Note: Register 6A is REG_XP_TEST[7:0], its eye and jitter CTS report please see attached file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) // it6161 �b�� ite mipi TX (��Ljitter OK��source��), keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) // [6A]=0x00 (default setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) it6161_hdmi_tx_set_bits(it6161, 0x6A, 0xFF, 0x5D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) // Remark: write reg61 with 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) // When program reg61 with 0x04,then audio and video circuit work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) static void hdmi_tx_fire_afe(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) it6161_hdmi_tx_change_bank(it6161, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) // utility function for main..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) // #ifndef DISABLE_HDMITX_CSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) // #if (defined (SUPPORT_OUTPUTYUV)) && (defined (SUPPORT_INPUTRGB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) // extern const u8 bCSCMtx_RGB2YUV_ITU601_16_235[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) // extern const u8 bCSCMtx_RGB2YUV_ITU601_0_255[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) // extern const u8 bCSCMtx_RGB2YUV_ITU709_16_235[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) // extern const u8 bCSCMtx_RGB2YUV_ITU709_0_255[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) // #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) // #if (defined (SUPPORT_OUTPUTRGB)) && (defined (SUPPORT_INPUTYUV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) // extern const u8 bCSCMtx_YUV2RGB_ITU601_16_235[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) // extern const u8 bCSCMtx_YUV2RGB_ITU601_0_255[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) // extern const u8 bCSCMtx_YUV2RGB_ITU709_16_235[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) // extern const u8 bCSCMtx_YUV2RGB_ITU709_0_255[] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) // #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) // #endif// DISABLE_HDMITX_CSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) static void hdmi_tx_disable_video_output(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST|B_TX_AFE_DRV_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static void hdmi_tx_enable_video_output(struct it6161 *it6161, VIDEOPCLKLEVEL level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST | B_TX_AREF_RST | B_TX_HDCP_RST_HDMITX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) if(it6161->hdmi_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) it6161_hdmi_tx_set_av_mute(it6161, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) hdmi_tx_setup_pclk_div2(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) hdmi_tx_setup_csc(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) it6161_hdmi_tx_write(it6161, REG_TX_HDMI_MODE, it6161->hdmi_mode ? B_TX_HDMI_MODE : B_TX_DVI_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) hdmi_tx_setup_afe(it6161, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) hdmi_tx_fire_afe(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) static u8 AudioDelayCnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) static u8 LastRefaudfreqnum=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) static bool bForceCTS = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) static void setHDMITX_ChStat(struct it6161 *it6161, u8 ucIEC60958ChStat[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) u8 uc ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) uc = (ucIEC60958ChStat[0] <<1)& 0x7C ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_MODE,uc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CAT,ucIEC60958ChStat[1]); // 192, audio CATEGORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_SRCNUM,ucIEC60958ChStat[2]&0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) it6161_hdmi_tx_write(it6161, REG_TX_AUD0CHST_CHTNUM,(ucIEC60958ChStat[2]>>4)&0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS,ucIEC60958ChStat[3]); // choose clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL,ucIEC60958ChStat[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) void setHDMITX_UpdateChStatFs(u32 Fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) u8 uc ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) /////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) // Fs should be the following value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) // #define AUDFS_22p05KHz 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) // #define AUDFS_44p1KHz 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) // #define AUDFS_88p2KHz 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) // #define AUDFS_176p4KHz 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) // #define AUDFS_24KHz 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) // #define AUDFS_48KHz 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) // #define AUDFS_96KHz 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) // #define AUDFS_192KHz 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) // #define AUDFS_768KHz 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) // #define AUDFS_32KHz 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) // #define AUDFS_OTHER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) /////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) uc = it6161_hdmi_tx_read(it6161, REG_TX_AUDCHST_CA_FS); // choose clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS,uc); // choose clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) uc &= 0xF0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) uc |= (Fs&0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) uc = it6161_hdmi_tx_read(it6161, REG_TX_AUDCHST_OFS_WL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) uc &= 0xF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) uc |= ((~Fs) << 4)&0xF0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL,uc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) static void setHDMITX_LPCMAudio(u8 AudioSrcNum, u8 AudSWL, u8 bAudInterface /*I2S/SPDIF/TDM*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) u8 AudioEnable, AudioFormat ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) u8 bTDMSetting ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) AudioEnable = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) AudioFormat = hdmiTxDev[0].bOutputAudioMode ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) switch(AudSWL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) AudioEnable |= M_TX_AUD_16BIT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) case 18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) AudioEnable |= M_TX_AUD_18BIT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) AudioEnable |= M_TX_AUD_20BIT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) AudioEnable |= M_TX_AUD_24BIT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) AudioFormat &= ~0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) AudioEnable |= B_TX_AUD_SPDIF|B_TX_AUD_EN_I2S0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) AudioFormat |= 0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) switch(AudioSrcNum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) AudioEnable |= B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) AudioEnable |= B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) AudioEnable |= B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) AudioFormat &= ~0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) AudioEnable |= B_TX_AUD_EN_I2S0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) AudioFormat|=0x01;//mingchih add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) hdmiTxDev[0].bAudioChannelEnable=AudioEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0,AudioEnable&0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,AudioFormat); // regE1 bOutputAudioMode should be loaded from ROM image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) it6161_hdmi_tx_set_bits(it6161, 0x5A,0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) #ifdef USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) #else // not USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) #endif // USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) u8 i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) it6161_hdmi_tx_set_bits(it6161, 0x5c,(1<<6), (1<<6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) for( i = 0 ; i < 100 ; i++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) break ; // stable clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) bTDMSetting = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) if( bAudInterface == TDM )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) bTDMSetting |= B_TX_TDM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) bTDMSetting &= 0x9F ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) bTDMSetting |= (AudioSrcNum-1)<< 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) bTDMSetting &= ~B_TX_TDM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, bTDMSetting) ; // 2 channel NLPCM, no TDM mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) static void setHDMITX_NLPCMAudio(u8 bAudInterface /*I2S/SPDIF/TDM*/) // no Source Num, no I2S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) u8 AudioEnable, AudioFormat ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) u8 i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) AudioFormat = 0x01 ; // NLPCM must use standard I2S mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) AudioEnable = M_TX_AUD_24BIT|B_TX_AUD_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) AudioEnable = M_TX_AUD_24BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) // it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) //it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST|B_TX_AREF_RST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x01); // regE1 bOutputAudioMode should be loaded from ROM image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) #ifdef USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) #else // not USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) #endif // USE_SPDIF_CHSTAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) for( i = 0 ; i < 100 ; i++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) break ; // stable clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) i = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) i &= ~B_TX_TDM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, i) ; // 2 channel NLPCM, no TDM mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable|B_TX_AUD_EN_I2S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) static void setHDMITX_HBRAudio(u8 bAudInterface /*I2S/SPDIF/TDM*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) // u8 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) // rst = it6161_hdmi_tx_read(it6161, REG_TX_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) // rst &= ~(B_HDMITX_AUD_RST|B_TX_AREF_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) // it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, rst | B_HDMITX_AUD_RST );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x47); // regE1 bOutputAudioMode should be loaded from ROM image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) #ifdef USE_IT66120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,B_TX_HBR); // regE5 = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) //uc = it6161_hdmi_tx_read(it6161, REG_TX_CLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) //uc &= ~M_TX_AUD_DIV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) //it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL1, uc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) if( bAudInterface == SPDIF )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) u8 i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) for( i = 0 ; i < 100 ; i++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) break ; // stable clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF|B_TX_AUD_EN_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) it6161_hdmi_tx_set_bits(it6161, 0x5c, BIT(6), 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) hdmiTxDev[0].bAudioChannelEnable=it6161_hdmi_tx_read(it6161, REG_TX_AUDIO_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) // it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, rst );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) static void setHDMITX_DSDAudio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) // to be continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) // u8 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) // rst = it6161_hdmi_tx_read(it6161, REG_TX_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) //it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, rst | (B_HDMITX_AUD_RST|B_TX_AREF_RST) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x41); // regE1 bOutputAudioMode should be loaded from ROM image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,B_TX_DSD); // regE5 = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) //it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, rst & ~(B_HDMITX_AUD_RST|B_TX_AREF_RST) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) //uc = it6161_hdmi_tx_read(it6161, REG_TX_CLK_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) //uc &= ~M_TX_AUD_DIV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) //it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL1, uc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|B_TX_AUD_EN_I2S1|B_TX_AUD_EN_I2S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) static void HDMITX_DisableAudioOutput(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) //u8 uc = (it6161_hdmi_tx_read(it6161, REG_TX_SW_RST) | (B_HDMITX_AUD_RST | B_TX_AREF_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) //it6161_hdmi_tx_write(it6161, REG_TX_SW_RST,uc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) AudioDelayCnt=AudioOutDelayCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) LastRefaudfreqnum=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, (B_HDMITX_AUD_RST | B_TX_AREF_RST), (B_HDMITX_AUD_RST | B_TX_AREF_RST) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x10 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) static void HDMITX_EnableAudioOutput(struct it6161 *it6161, u8 AudioType, u8 bAudInterface /*I2S/SPDIF/TDM*/, u32 SampleFreq, u8 ChNum, u8 *pIEC60958ChStat, u32 TMDSClock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) static u8 ucIEC60958ChStat[5] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) u8 Fs ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) AudioDelayCnt=36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) LastRefaudfreqnum=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) hdmiTxDev[0].TMDSClock=TMDSClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) hdmiTxDev[0].bAudioChannelEnable=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) hdmiTxDev[0].bAudInterface=bAudInterface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) //DRM_INFO1(("HDMITX_EnableAudioOutput(%02X, %s, %d, %d, %p, %d);\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) // AudioType, bSPDIF?"SPDIF":"I2S",SampleFreq, ChNum, pIEC60958ChStat, TMDSClock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) // ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST | B_TX_AREF_RST), (B_HDMITX_AUD_RST | B_TX_AREF_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0,B_TX_AUTO_OVER_SAMPLING_CLOCK|B_TX_EXT_256FS|0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x00 ); // power on the ACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) if(bAudInterface == SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) if(AudioType==T_AUDIO_HBR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0,0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0,B_TX_AUD_SPDIF, B_TX_AUD_SPDIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, B_TX_AUD_SPDIF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) if( AudioType != T_AUDIO_DSD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) // one bit audio have no channel status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) switch(SampleFreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) case 44100L: Fs = AUDFS_44p1KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) case 88200L: Fs = AUDFS_88p2KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) case 176400L: Fs = AUDFS_176p4KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) case 32000L: Fs = AUDFS_32KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) case 48000L: Fs = AUDFS_48KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) case 96000L: Fs = AUDFS_96KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) case 192000L: Fs = AUDFS_192KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) case 768000L: Fs = AUDFS_768KHz ; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) SampleFreq = 48000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) Fs = AUDFS_48KHz ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) break ; // default, set Fs = 48KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) #ifdef SUPPORT_AUDIO_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) hdmiTxDev[0].bAudFs=Fs;// AUDFS_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) hdmiTxDev[0].bAudFs=Fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) setHDMITX_NCTS(hdmiTxDev[0].bAudFs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) if( pIEC60958ChStat == NULL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) ucIEC60958ChStat[0] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) ucIEC60958ChStat[1] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) ucIEC60958ChStat[2] = (ChNum+1)/2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) if(ucIEC60958ChStat[2]<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) ucIEC60958ChStat[2] = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) else if( ucIEC60958ChStat[2] >4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) ucIEC60958ChStat[2] = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) ucIEC60958ChStat[3] = Fs ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) ucIEC60958ChStat[4] = (((~Fs)<<4) & 0xF0) | CHTSTS_SWCODE ; // Fs | 24bit u32 length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) pIEC60958ChStat = ucIEC60958ChStat ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),B_TX_AREF_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) switch(AudioType)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) case T_AUDIO_HBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) DRM_INFO("T_AUDIO_HBR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) pIEC60958ChStat[0] |= 1<<1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) pIEC60958ChStat[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) pIEC60958ChStat[3] &= 0xF0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) pIEC60958ChStat[3] |= AUDFS_768KHz ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) pIEC60958ChStat[4] |= (((~AUDFS_768KHz)<<4) & 0xF0)| 0xB ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) setHDMITX_ChStat(it6161, pIEC60958ChStat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) setHDMITX_HBRAudio(bAudInterface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) case T_AUDIO_DSD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) DRM_INFO("T_AUDIO_DSD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) setHDMITX_DSDAudio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) case T_AUDIO_NLPCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) DRM_INFO("T_AUDIO_NLPCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) pIEC60958ChStat[0] |= 1<<1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) setHDMITX_ChStat(it6161, pIEC60958ChStat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) setHDMITX_NLPCMAudio(bAudInterface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) case T_AUDIO_LPCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) DRM_INFO("T_AUDIO_LPCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) pIEC60958ChStat[0] &= ~(1<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) setHDMITX_ChStat(it6161, pIEC60958ChStat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) setHDMITX_LPCMAudio((ChNum+1)/2, SUPPORT_AUDI_AudSWL, bAudInterface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) // can add auto adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK1, B_TX_AUDIO_OVFLW_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, hdmiTxDev[0].bAudioChannelEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) #ifdef SUPPORT_AUDIO_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) void hdmitx_AutoAdjustAudio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) u32 SampleFreq,cTMDSClock ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) u32 N ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) u32 aCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) u8 fs, uc,LoopCnt=10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) if(bForceCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) it6161_hdmi_tx_write(it6161, 0xF8, 0xC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) it6161_hdmi_tx_write(it6161, 0xF8, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, B_TX_SW_CTS, 0x00); // D[1] = 0, HW auto count CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) it6161_hdmi_tx_write(it6161, 0xF8, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) //msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) N = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN2)&0xF) << 16 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) N |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN1)) <<8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) N |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) while(LoopCnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) { u32 TempCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) aCTS = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt2)) << 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) aCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt1)) <<4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) aCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt0)&0xf0)>>4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) if(aCTS==TempCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) {break;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) TempCTS=aCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) if( aCTS == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) DRM_INFO("aCTS== 0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) uc = it6161_hdmi_tx_read(it6161, REG_TX_GCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) cTMDSClock = hdmiTxDev[0].TMDSClock ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) //TMDSClock=GetInputPclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) DRM_INFO("PCLK = %u0,000\n",(u32)(cTMDSClock/10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) switch(uc & 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) case 0x50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) cTMDSClock *= 5 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) cTMDSClock /= 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) cTMDSClock *= 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) cTMDSClock /= 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) SampleFreq = cTMDSClock/aCTS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) SampleFreq *= N ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) SampleFreq /= 128 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) //SampleFreq=48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) DRM_INFO("SampleFreq = %u0\n",(u32)(SampleFreq/10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) if( SampleFreq>31000L && SampleFreq<=38050L ){fs = AUDFS_32KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) else if (SampleFreq < 46550L ) {fs = AUDFS_44p1KHz ;}//46050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) else if (SampleFreq < 68100L ) {fs = AUDFS_48KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) else if (SampleFreq < 92100L ) {fs = AUDFS_88p2KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) else if (SampleFreq < 136200L ) {fs = AUDFS_96KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) else if (SampleFreq < 184200L ) {fs = AUDFS_176p4KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) else if (SampleFreq < 240200L ) {fs = AUDFS_192KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) else if (SampleFreq < 800000L ) {fs = AUDFS_768KHz ;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) fs = AUDFS_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) DRM_INFO("fs = AUDFS_OTHER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) if(hdmiTxDev[0].bAudFs != fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) hdmiTxDev[0].bAudFs=fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) setHDMITX_NCTS(hdmiTxDev[0].bAudFs); // set N, CTS by new generated clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) //CurrCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) bool hdmitx_IsAudioChang()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) //u32 pCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) u8 FreDiff=0,Refaudfreqnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) //it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) //pCTS = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt2)) << 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) //pCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt1)) <<4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) //pCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt0)&0xf0)>>4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) //it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) Refaudfreqnum=it6161_hdmi_tx_read(it6161, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) //"Refaudfreqnum=%X pCTS= %u",(u32)Refaudfreqnum,(u32)(pCTS/10000)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) //if((pCTS%10000)<1000)DRM_INFO("0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) //if((pCTS%10000)<100)DRM_INFO("0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) //if((pCTS%10000)<10)DRM_INFO("0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) //DRM_INFO("%u\n",(u32)(pCTS%10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) if((1<<4)&it6161_hdmi_tx_read(it6161, 0x5f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) //printf("=======XXXXXXXXXXX=========\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) if(LastRefaudfreqnum>Refaudfreqnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) {FreDiff=LastRefaudfreqnum-Refaudfreqnum;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) {FreDiff=Refaudfreqnum-LastRefaudfreqnum;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) LastRefaudfreqnum=Refaudfreqnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) if(3<FreDiff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) DRM_INFO("Aduio FreDiff=%d\n",(int)FreDiff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL,(1<<5), (1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, 0x0F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) void setHDMITX_AudioChannelEnable(bool EnableAudio_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) static bool AudioOutStatus=false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) if(EnableAudio_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) if(AudioDelayCnt==0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) //if(hdmiTxDev[0].bAuthenticated==false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) //{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) #ifdef SUPPORT_AUDIO_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) if(hdmitx_IsAudioChang())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) hdmitx_AutoAdjustAudio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) if(AudioOutStatus==false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) setHDMITX_NCTS(hdmiTxDev[0].bAudFs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL,(1<<5), (1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, hdmiTxDev[0].bAudioChannelEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) //it6161_hdmi_tx_set_bits(it6161, 0x59,(1<<2), (1<<2)); //for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, 0x3C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, 1<<5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) printf("Audio Out Enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) #ifndef SUPPORT_AUDIO_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) AudioOutStatus=true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) AudioOutStatus=false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) if(0==(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2)&0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) AudioDelayCnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) AudioDelayCnt=AudioOutDelayCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) // CurrCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) }*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) #endif //#ifdef SUPPORT_AUDIO_MONITOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) // Function: setHDMITX_NCTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) // Parameter: PCLK - video clock in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) // Fs - Encoded audio sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) // AUDFS_22p05KHz 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) // AUDFS_44p1KHz 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) // AUDFS_88p2KHz 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) // AUDFS_176p4KHz 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) // AUDFS_24KHz 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) // AUDFS_48KHz 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) // AUDFS_96KHz 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) // AUDFS_192KHz 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) // AUDFS_768KHz 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) // AUDFS_32KHz 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) // AUDFS_OTHER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) // Return: ER_SUCCESS if success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) // Remark: set N value,the CTS will be auto generated by HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) // Side-Effect: register bank will reset to bank 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) static void setHDMITX_NCTS(u8 Fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) u8 LoopCnt=255,CTSStableCnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) u32 diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) u32 CTS=0,LastCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) bool HBR_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) // u8 aVIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) if(B_TX_HBR & it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) HBR_mode=true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) HBR_mode=false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) switch(Fs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) case AUDFS_32KHz: n = 4096; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) case AUDFS_44p1KHz: n = 6272; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) case AUDFS_48KHz: n = 6144; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) case AUDFS_88p2KHz: n = 12544; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) case AUDFS_96KHz: n = 12288; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) case AUDFS_176p4KHz: n = 25088; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) case AUDFS_192KHz: n = 24576; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) case AUDFS_768KHz: n = 24576; break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) default: n = 6144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) // tr_printf((" n = %d\n",n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) it6161_hdmi_tx_write(it6161, REGPktAudN0,(u8)((n)&0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) it6161_hdmi_tx_write(it6161, REGPktAudN1,(u8)((n>>8)&0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) it6161_hdmi_tx_write(it6161, REGPktAudN2,(u8)((n>>16)&0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) if(bForceCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) u32 SumCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) while(LoopCnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) CTS = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt2)) << 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) CTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt1)) <<4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) CTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt0)&0xf0)>>4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) if( CTS == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) if(LastCTS>CTS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) {diff=LastCTS-CTS;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) {diff=CTS-LastCTS;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) //DRM_INFO("LastCTS= %u%u",(u32)(LastCTS/10000),(u32)(LastCTS%10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) //DRM_INFO(" CTS= %u%u\n",(u32)(CTS/10000),(u32)(CTS%10000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) LastCTS=CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) if(5>diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) CTSStableCnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) SumCTS+=CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) CTSStableCnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) SumCTS=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) if(CTSStableCnt>=32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) LastCTS=(SumCTS>>5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) it6161_hdmi_tx_write(it6161, REGPktAudCTS0,(u8)((LastCTS)&0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) it6161_hdmi_tx_write(it6161, REGPktAudCTS1,(u8)((LastCTS>>8)&0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) it6161_hdmi_tx_write(it6161, REGPktAudCTS2,(u8)((LastCTS>>16)&0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) #ifdef Force_CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) bForceCTS = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) it6161_hdmi_tx_write(it6161, 0xF8, 0xC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) it6161_hdmi_tx_write(it6161, 0xF8, 0xA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) if(bForceCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL,B_TX_SW_CTS, B_TX_SW_CTS); // D[1] = 0, HW auto count CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, B_TX_SW_CTS, 0x00); // D[1] = 0, HW auto count CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) it6161_hdmi_tx_write(it6161, 0xF8, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) if(false==HBR_mode) //LPCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) u8 uData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) Fs = AUDFS_768KHz ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS,0x00|Fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) Fs = ~Fs ; // OFS is the one's complement of FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) uData = (0x0f&it6161_hdmi_tx_read(it6161, REG_TX_AUDCHST_OFS_WL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL,(Fs<<4)|uData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) // Function: hdmitx_SetAudioInfoFrame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) // Parameter: pAudioInfoFrame - the pointer to HDMI Audio Infoframe ucData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) // Return: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) // Remark: Fill the Audio InfoFrame ucData,and count checksum,then fill into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) // Audio InfoFrame registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) // Side-Effect: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) static SYS_STATUS hdmitx_SetAudioInfoFrame(struct it6161 *it6161, Audio_InfoFrame *pAudioInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) u8 checksum ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) if(!pAudioInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) checksum = 0x100-(AUDIO_INFOFRAME_VER+AUDIO_INFOFRAME_TYPE+AUDIO_INFOFRAME_LEN );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CC,pAudioInfoFrame->pktbyte.AUD_DB[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_CC); checksum &= 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SF,pAudioInfoFrame->pktbyte.AUD_DB[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_SF); checksum &= 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CA,pAudioInfoFrame->pktbyte.AUD_DB[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_CA); checksum &= 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_DM_LSV,pAudioInfoFrame->pktbyte.AUD_DB[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_DM_LSV); checksum &= 0xFF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SUM,checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) hdmitx_ENABLE_AUD_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) // Function: hdmitx_SetAVIInfoFrame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) // Parameter: pAVIInfoFrame - the pointer to HDMI AVI Infoframe ucData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) // Return: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) // Remark: Fill the AVI InfoFrame ucData,and count checksum,then fill into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) // AVI InfoFrame registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) // Side-Effect: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) static SYS_STATUS hdmitx_SetAVIInfoFrame(struct it6161 *it6161, AVI_InfoFrame *pAVIInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) u8 checksum ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) if(!pAVIInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1,pAVIInfoFrame->pktbyte.AVI_DB[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB2,pAVIInfoFrame->pktbyte.AVI_DB[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB3,pAVIInfoFrame->pktbyte.AVI_DB[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB4,pAVIInfoFrame->pktbyte.AVI_DB[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB5,pAVIInfoFrame->pktbyte.AVI_DB[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB6,pAVIInfoFrame->pktbyte.AVI_DB[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB7,pAVIInfoFrame->pktbyte.AVI_DB[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB8,pAVIInfoFrame->pktbyte.AVI_DB[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB9,pAVIInfoFrame->pktbyte.AVI_DB[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB10,pAVIInfoFrame->pktbyte.AVI_DB[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB11,pAVIInfoFrame->pktbyte.AVI_DB[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB12,pAVIInfoFrame->pktbyte.AVI_DB[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB13,pAVIInfoFrame->pktbyte.AVI_DB[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) for(i = 0,checksum = 0; i < 13 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) checksum -= pAVIInfoFrame->pktbyte.AVI_DB[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) DRM_INFO("SetAVIInfo(): ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) DRM_INFO("%02X ",(int)it6161_hdmi_tx_read(it6161, REG_TX_AVIINFO_DB13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) DRM_INFO("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) checksum -= AVI_INFOFRAME_VER+AVI_INFOFRAME_TYPE+AVI_INFOFRAME_LEN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_SUM,checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) hdmitx_ENABLE_AVI_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) static SYS_STATUS hdmitx_SetVSIInfoFrame(struct it6161 *it6161, VendorSpecific_InfoFrame *pVSIInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) u8 ucData=0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) if(!pVSIInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) it6161_hdmi_tx_write(it6161, 0x80,pVSIInfoFrame->pktbyte.VS_DB[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) it6161_hdmi_tx_write(it6161, 0x81,pVSIInfoFrame->pktbyte.VS_DB[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) ucData -= pVSIInfoFrame->pktbyte.VS_DB[3] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) ucData -= pVSIInfoFrame->pktbyte.VS_DB[4] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) if( pVSIInfoFrame->pktbyte.VS_DB[4] & (1<<7 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) ucData -= pVSIInfoFrame->pktbyte.VS_DB[5] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) it6161_hdmi_tx_write(it6161, 0x82,pVSIInfoFrame->pktbyte.VS_DB[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) ucData -= VENDORSPEC_INFOFRAME_TYPE + VENDORSPEC_INFOFRAME_VER + 6 + 0x0C + 0x03 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) ucData -= VENDORSPEC_INFOFRAME_TYPE + VENDORSPEC_INFOFRAME_VER + 5 + 0x0C + 0x03 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) pVSIInfoFrame->pktbyte.CheckSum=ucData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) it6161_hdmi_tx_write(it6161, 0x83,pVSIInfoFrame->pktbyte.CheckSum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) it6161_hdmi_tx_write(it6161, REG_TX_3D_INFO_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) static bool HDMITX_EnableVSInfoFrame(struct it6161 *it6161, u8 bEnable,u8 *pVSInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) if(!bEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) hdmitx_DISABLE_VSDB_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) if(hdmitx_SetVSIInfoFrame(it6161, (VendorSpecific_InfoFrame *)pVSInfoFrame) == ER_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) return false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) static bool HDMITX_EnableAVIInfoFrame(struct it6161 *it6161, u8 bEnable,u8 *pAVIInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) if(!bEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) hdmitx_DISABLE_AVI_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) if(hdmitx_SetAVIInfoFrame(it6161, (AVI_InfoFrame *)pAVIInfoFrame) == ER_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) return false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) static bool HDMITX_EnableAudioInfoFrame(struct it6161 *it6161, u8 bEnable,u8 *pAudioInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) if(!bEnable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) hdmitx_DISABLE_AVI_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) if(hdmitx_SetAudioInfoFrame(it6161, (Audio_InfoFrame *)pAudioInfoFrame) == ER_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) return true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) return false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) // Function: hdmitx_SetSPDInfoFrame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) // Parameter: pSPDInfoFrame - the pointer to HDMI SPD Infoframe ucData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) // Return: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) // Remark: Fill the SPD InfoFrame ucData,and count checksum,then fill into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) // SPD InfoFrame registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) // Side-Effect: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) SYS_STATUS hdmitx_SetSPDInfoFrame(SPD_InfoFrame *pSPDInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) u8 ucData ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) if(!pSPDInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) for(i = 0,ucData = 0 ; i < 25 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) ucData -= pSPDInfoFrame->pktbyte.SPD_DB[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) it6161_hdmi_tx_write(it6161, REG_TX_PKT_SPDINFO_PB1+i,pSPDInfoFrame->pktbyte.SPD_DB[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) ucData -= SPD_INFOFRAME_VER+SPD_INFOFRAME_TYPE+SPD_INFOFRAME_LEN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) it6161_hdmi_tx_write(it6161, REG_TX_PKT_SPDINFO_SUM,ucData); // checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) hdmitx_ENABLE_SPD_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) // Function: hdmitx_SetMPEGInfoFrame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) // Parameter: pMPEGInfoFrame - the pointer to HDMI MPEG Infoframe ucData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) // Return: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) // Remark: Fill the MPEG InfoFrame ucData,and count checksum,then fill into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) // MPEG InfoFrame registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) // Side-Effect: N/A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) //////////////////////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) SYS_STATUS hdmitx_SetMPEGInfoFrame(MPEG_InfoFrame *pMPGInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) u8 ucData ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) if(!pMPGInfoFrame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) it6161_hdmi_tx_write(it6161, REG_TX_PKT_MPGINFO_FMT,pMPGInfoFrame->info.FieldRepeat|(pMPGInfoFrame->info.MpegFrame<<1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) it6161_hdmi_tx_write(it6161, REG_TX_PKG_MPGINFO_DB0,pMPGInfoFrame->pktbyte.MPG_DB[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) it6161_hdmi_tx_write(it6161, REG_TX_PKG_MPGINFO_DB1,pMPGInfoFrame->pktbyte.MPG_DB[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) it6161_hdmi_tx_write(it6161, REG_TX_PKG_MPGINFO_DB2,pMPGInfoFrame->pktbyte.MPG_DB[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) it6161_hdmi_tx_write(it6161, REG_TX_PKG_MPGINFO_DB3,pMPGInfoFrame->pktbyte.MPG_DB[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) for(ucData = 0,i = 0 ; i < 5 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) ucData -= pMPGInfoFrame->pktbyte.MPG_DB[i] ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) ucData -= MPEG_INFOFRAME_VER+MPEG_INFOFRAME_TYPE+MPEG_INFOFRAME_LEN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) it6161_hdmi_tx_write(it6161, REG_TX_PKG_MPGINFO_SUM,ucData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) hdmitx_ENABLE_SPD_INFOFRM_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) // 2009/12/04 added by Ming-chih.lung@ite.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) SYS_STATUS hdmitx_Set_GeneralPurpose_PKT(u8 *pData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) if( pData == NULL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) return ER_FAIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) for( i = 0x38 ; i <= 0x56 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) it6161_hdmi_tx_write(it6161, i, pData[i-0x38] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) hdmitx_ENABLE_GeneralPurpose_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) //hdmitx_ENABLE_NULL_PKT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) return ER_SUCCESS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) static void ConfigAVIInfoFrame(u8 VIC, u8 pixelrep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) AVI_InfoFrame *AviInfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) AviInfo = (AVI_InfoFrame *)CommunBuff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) AviInfo->pktbyte.AVI_HB[0] = AVI_INFOFRAME_TYPE|0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) AviInfo->pktbyte.AVI_HB[1] = AVI_INFOFRAME_VER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) AviInfo->pktbyte.AVI_HB[2] = AVI_INFOFRAME_LEN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) switch(it6161->hdmi_tx_output_color_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) case F_MODE_YUV444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) // AviInfo->info.ColorMode = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) AviInfo->pktbyte.AVI_DB[0] = (2<<5)|(1<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) case F_MODE_YUV422:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) // AviInfo->info.ColorMode = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) AviInfo->pktbyte.AVI_DB[0] = (1<<5)|(1<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) case F_MODE_RGB444:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) // AviInfo->info.ColorMode = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) AviInfo->pktbyte.AVI_DB[0] = (0<<5)|(1<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) AviInfo->pktbyte.AVI_DB[1] = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) AviInfo->pktbyte.AVI_DB[1] |= (aspec != HDMI_16x9)?(1<<4):(2<<4); // 4:3 or 16:9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) AviInfo->pktbyte.AVI_DB[1] |= (Colorimetry != HDMI_ITU709)?(1<<6):(2<<6); // 4:3 or 16:9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) AviInfo->pktbyte.AVI_DB[2] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) AviInfo->pktbyte.AVI_DB[3] = VIC ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) AviInfo->pktbyte.AVI_DB[4] = pixelrep & 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) AviInfo->pktbyte.AVI_DB[5] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) AviInfo->pktbyte.AVI_DB[6] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) AviInfo->pktbyte.AVI_DB[7] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) AviInfo->pktbyte.AVI_DB[8] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) AviInfo->pktbyte.AVI_DB[9] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) AviInfo->pktbyte.AVI_DB[10] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) AviInfo->pktbyte.AVI_DB[11] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) AviInfo->pktbyte.AVI_DB[12] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) HDMITX_EnableAVIInfoFrame(it6161, true, (unsigned char *)AviInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) static void ConfigAudioInfoFrm(struct it6161 *it6161, u8 channel_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) Audio_InfoFrame *AudioInfo ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) AudioInfo = (Audio_InfoFrame *)CommunBuff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) DRM_INFO("ConfigAudioInfoFrm channel count: %d", channel_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) AudioInfo->pktbyte.AUD_HB[0] = AUDIO_INFOFRAME_TYPE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) AudioInfo->pktbyte.AUD_HB[1] = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) AudioInfo->pktbyte.AUD_HB[2] = AUDIO_INFOFRAME_LEN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) AudioInfo->pktbyte.AUD_DB[0] = channel_count - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) for (i = 1 ;i < AUDIO_INFOFRAME_LEN ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) AudioInfo->pktbyte.AUD_DB[i] = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) /* audio_infoframe_ca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) switch (channel_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) case 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) AudioInfo->pktbyte.AUD_DB[3] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) break; // no audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) case 2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) AudioInfo->pktbyte.AUD_DB[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) case 3 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) AudioInfo->pktbyte.AUD_DB[3] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) break; // 0x01,0x02,0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) case 4 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) AudioInfo->pktbyte.AUD_DB[3] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) break; // 0x03,0x05,0x06,0x08,0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) case 5 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) AudioInfo->pktbyte.AUD_DB[3] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) break; // 0x07,0x09,0x0A,0x0C,0x15,0x16,0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) case 6 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) AudioInfo->pktbyte.AUD_DB[3] = 0x0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) break; // 0x0B,0x0D,0x0E,0x10,0x17,0x19,0x1A,0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) case 7 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) AudioInfo->pktbyte.AUD_DB[3] = 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) break; // 0x0F,0x11,0x12,0x1B,0x1D,0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) case 8 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) AudioInfo->pktbyte.AUD_DB[3] = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) break; // 0x13,0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) default :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) DRM_INFO("Error: Audio Channel Number Error!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) HDMITX_EnableAudioInfoFrame(it6161, TRUE, (unsigned char *)AudioInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) #ifdef OUTPUT_3D_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) void ConfigfHdmiVendorSpecificInfoFrame(struct it6161 *it6161, u8 _3D_Stru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) VendorSpecific_InfoFrame *VS_Info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) VS_Info=(VendorSpecific_InfoFrame *)CommunBuff ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) VS_Info->pktbyte.VS_HB[0] = VENDORSPEC_INFOFRAME_TYPE|0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) VS_Info->pktbyte.VS_HB[1] = VENDORSPEC_INFOFRAME_VER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) VS_Info->pktbyte.VS_HB[2] = (_3D_Stru == Side_by_Side)?6:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) VS_Info->pktbyte.VS_DB[0] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) VS_Info->pktbyte.VS_DB[1] = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) VS_Info->pktbyte.VS_DB[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) VS_Info->pktbyte.VS_DB[3] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) switch(_3D_Stru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) case Side_by_Side:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) case Frame_Pcaking:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) case Top_and_Botton:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) VS_Info->pktbyte.VS_DB[4] = (_3D_Stru<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) VS_Info->pktbyte.VS_DB[4] = (Frame_Pcaking<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) VS_Info->pktbyte.VS_DB[5] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) HDMITX_EnableVSInfoFrame(it6161, true,(u8 *)VS_Info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) #endif //#ifdef OUTPUT_3D_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) static void hdmi_tx_audio_process(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) if (it6161->support_audio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) ConfigAudioInfoFrm(it6161, bOutputAudioChannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) // HDMITX_EnableAudioOutput(T_AUDIO_LPCM, false, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,TMDSClock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) HDMITX_EnableAudioOutput(it6161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) //CNOFIG_INPUT_AUDIO_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) bOutputAudioType,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) CONFIG_INPUT_AUDIO_INTERFACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) ulAudioSampleFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) bOutputAudioChannel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) NULL, // pointer to cahnnel status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) VideoPixelClock*(pixelrep+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) // if you have channel status , set here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) // setHDMITX_ChStat(it6161, u8 ucIEC60958ChStat[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) u8 csum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) /* compute checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) csum += ptr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) return 256 - csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) static void hdmi_infoframe_set_checksum(void *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) u8 *ptr = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) ptr[3] = hdmi_infoframe_checksum(buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) static int hdmi_tx_get_avi_infoframe_from_source(struct it6161 *it6161, u8 *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) err = hdmi_avi_infoframe_pack(&it6161->source_avi_infoframe, buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) DRM_DEV_ERROR(dev, "Failed to pack AVI infoframe: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) static int hdmi_tx_get_avi_infoframe_from_user_define(struct it6161 *it6161, u8 *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) struct device *dev = &it6161->i2c_hdmi_tx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) struct hdmi_avi_infoframe *frame = &it6161->source_avi_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) struct drm_display_mode *display_mode = &it6161->source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) DRM_INFO( "user define to setup AVI infoframe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &it6161->connector, display_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) DRM_DEV_ERROR(dev, "Failed to setup AVI infoframe: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_RGB444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) frame->colorspace = HDMI_COLORSPACE_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) frame->colorspace = HDMI_COLORSPACE_YUV444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) frame->colorspace = HDMI_COLORSPACE_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) ret = hdmi_tx_get_avi_infoframe_from_source(it6161, buffer, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) DRM_DEV_ERROR(dev, "Failed to pack AVI infoframe: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) static int (*hdmi_tx_get_avi_infoframe)(struct it6161*, u8*, size_t) = hdmi_tx_get_avi_infoframe_from_user_define;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) static void hdmi_tx_setup_avi_infoframe(struct it6161 *it6161, u8 *buffer, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) u8 i, *ptr = buffer + HDMI_INFOFRAME_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) it6161_hdmi_tx_change_bank(it6161, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) for (i = 0; i < it6161->source_avi_infoframe.length; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1 + i, ptr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_SUM, buffer[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) static inline void hdmi_tx_disable_avi_infoframe(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) static inline void hdmi_tx_enable_avi_infoframe(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, B_TX_ENABLE_PKT | B_TX_REPEAT_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) static int hdmi_tx_avi_infoframe_process(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) hdmi_tx_disable_avi_infoframe(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) err = hdmi_tx_get_avi_infoframe(it6161, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) hdmi_tx_setup_avi_infoframe(it6161, buffer, sizeof(buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) hdmi_tx_enable_avi_infoframe(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) DRM_INFO("avi_infoframe:0x%*ph", (int)ARRAY_SIZE(buffer), buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) static void hdmi_tx_set_output_process(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) VIDEOPCLKLEVEL level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) u32 TMDSClock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) TMDSClock = it6161->hdmi_tx_pclk * 1000 * (it6161->source_avi_infoframe.pixel_repeat + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) HDMITX_DisableAudioOutput(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) //hdmi_tx_hdcp_reset_auth(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) hdmi_tx_disable_avi_infoframe(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) HDMITX_EnableVSInfoFrame(it6161, false,NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) if (TMDSClock > 80000000L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) level = PCLK_HIGH ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) } else if(TMDSClock > 20000000L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) level = PCLK_MEDIUM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) level = PCLK_LOW ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) hdmi_tx_enable_video_output(it6161, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) if (it6161->hdmi_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) #ifdef OUTPUT_3D_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) ConfigfHdmiVendorSpecificInfoFrame(it6161, OUTPUT_3D_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) hdmi_tx_avi_infoframe_process(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) hdmi_tx_audio_process(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) // if( it6161->support_audio )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) // {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) // ConfigAudioInfoFrm(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) // #ifdef SUPPORT_HBR_AUDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) // HDMITX_EnableAudioOutput(it6161, T_AUDIO_HBR, CONFIG_INPUT_AUDIO_INTERFACE, 768000L,8,NULL,TMDSClock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) // #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) // // HDMITX_EnableAudioOutput(it6161, T_AUDIO_LPCM, false, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,TMDSClock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) // HDMITX_EnableAudioOutput(it6161, CNOFIG_INPUT_AUDIO_TYPE, CONFIG_INPUT_AUDIO_INTERFACE, ulAudioSampleFS,bOutputAudioChannel,NULL,TMDSClock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) // #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) #ifdef SUPPORT_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) it6161_hdmi_tx_change_bank(it6161, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) it6161_hdmi_tx_write(it6161, 0xf, 0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) Initial_Ext_Int1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) HDMITX_CEC_Init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) #endif // SUPPORT_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) it6161_hdmi_tx_set_av_mute(it6161, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) bChangeMode = false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) /*void HDMITX_ChangeAudioOption(u8 Option, u8 channelNum, u8 AudioFs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) switch(Option )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) case T_AUDIO_HBR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) bOutputAudioType = T_AUDIO_HBR ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) ulAudioSampleFS = 768000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) bOutputAudioChannel = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) case T_AUDIO_NLPCM :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) bOutputAudioType = T_AUDIO_NLPCM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) bOutputAudioChannel = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) bOutputAudioType = T_AUDIO_LPCM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) if( channelNum < 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) bOutputAudioChannel = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) else if( channelNum > 8 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) bOutputAudioChannel = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) bOutputAudioChannel = channelNum ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) switch(AudioFs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) case AUDFS_44p1KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) ulAudioSampleFS = 44100L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) case AUDFS_88p2KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) ulAudioSampleFS = 88200L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) case AUDFS_176p4KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) ulAudioSampleFS = 176400L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) case AUDFS_48KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) ulAudioSampleFS = 48000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) case AUDFS_96KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) ulAudioSampleFS = 96000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) case AUDFS_192KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) ulAudioSampleFS = 192000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) case AUDFS_768KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) ulAudioSampleFS = 768000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) case AUDFS_32KHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) ulAudioSampleFS = 32000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) ulAudioSampleFS = 48000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) DRM_INFO("HDMITX_ChangeAudioOption():bOutputAudioType = %02X, ulAudioSampleFS = %8ld, bOutputAudioChannel = %d\n",(int)bOutputAudioType,ulAudioSampleFS,(int)bOutputAudioChannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) #ifdef HDMITX_AUTO_MONITOR_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) void HDMITX_MonitorInputAudioChange()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) static u32 prevAudioSampleFS = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) u32 AudioFS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) if( !it6161->support_audio )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) prevAudioSampleFS = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) AudioFS = CalcAudFS() ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) DRM_INFO1(("Audio Chagne, Audio clock = %dHz\n",AudioFS)) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) if( AudioFS > 188000L ) // 192KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) ulAudioSampleFS = 192000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) else if( AudioFS > 144000L ) // 176.4KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) ulAudioSampleFS = 176400L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) else if( AudioFS > 93000L ) // 96KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) ulAudioSampleFS = 96000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) else if( AudioFS > 80000L ) // 88.2KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) ulAudioSampleFS = 88200L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) else if( AudioFS > 45000L ) // 48 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) ulAudioSampleFS = 48000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) else if( AudioFS > 36000L ) // 44.1KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) ulAudioSampleFS = 44100L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) else // 32KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) ulAudioSampleFS = 32000L ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) if(!bChangeMode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) if( ulAudioSampleFS != prevAudioSampleFS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) DRM_INFO("ulAudioSampleFS = %dHz -> %dHz\n",ulAudioSampleFS,ulAudioSampleFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) ConfigAudioInfoFrm(it6161, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) HDMITX_EnableAudioOutput(it6161, CNOFIG_INPUT_AUDIO_TYPE, CONFIG_INPUT_AUDIO_INTERFACE, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) // HDMITX_EnableAudioOutput(it6161, T_AUDIO_LPCM, false, ulAudioSampleFS,OUTPUT_CHANNEL,NULL,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) prevAudioSampleFS = ulAudioSampleFS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) #endif // HDMITX_AUTO_MONITOR_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) static void mipi_rx_calc_rclk(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) u32 sum = 0, i, retry = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) int t10usint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) //it6161_hdmi_tx_write(it6161, 0x8D, (CEC_I2C_SLAVE_ADDR|0x01));// Enable CRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x80); // Enable RCLK 100ms count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x00); // Disable RCLK 100ms count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) it6161->mipi_rx_rclk = it6161_mipi_rx_read(it6161, 0x97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) it6161->mipi_rx_rclk <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) it6161->mipi_rx_rclk <<=8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) sum += it6161->mipi_rx_rclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) sum /= retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) DRM_INFO("rclk: %d\n", sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) //it6161->mipi_rx_rclk = sum / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) it6161->mipi_rx_rclk = sum / 104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) t10usint = it6161->mipi_rx_rclk / 108;//actually nxp platform msleep(100) is 108ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) DRM_INFO("it6161->mipi_rx_rclk = %d,%03d,%03d\n",(sum*10)/1000000,((sum*10)%1000000)/1000,((sum*10)%100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) DRM_INFO("T10usInt=0x%03X\n", (int)t10usint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) it6161_mipi_rx_write(it6161, 0x91, t10usint&0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) static void mipi_rx_calc_mclk(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) u32 i, rddata, sum = 0, calc_time = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) for (i = 0; i < calc_time; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) it6161_mipi_rx_set_bits(it6161, 0x9B, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) it6161_mipi_rx_set_bits(it6161, 0x9B, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) rddata = it6161_mipi_rx_read(it6161, 0x9B) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) rddata <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) rddata += it6161_mipi_rx_read(it6161, 0x9A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) sum += rddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) sum /= calc_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) it6161->mipi_rx_mclk = it6161->mipi_rx_rclk * 2048 / sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) DRM_INFO("MCLK = %d.%03dMHz", it6161->mipi_rx_mclk / 1000, it6161->mipi_rx_mclk % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) static void mipi_rx_calc_pclk(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) u32 rddata, sum = 0, retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) for (i = 0; i < retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) rddata = it6161_mipi_rx_read(it6161, 0x99) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) rddata <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) rddata += it6161_mipi_rx_read(it6161, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) sum += rddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) sum /= retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) DRM_INFO("pclk: %d\n", sum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) it6161->mipi_rx_pclk = it6161->mipi_rx_rclk * 2048 / sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) //it6161->mipi_rx_pclk = it6161->mipi_rx_rclk * 1960 / sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) DRM_INFO("it6161->mipi_rx_pclk = %d.%03dMHz", it6161->mipi_rx_pclk / 1000, it6161->mipi_rx_pclk % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) static void mipi_rx_show_mrec(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) int m_hfront_porch, m_hsyncw, m_hback_porch, m_hactive, MHVR2nd, MHBlank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) int m_vfront_porch, m_vsyncw, m_vback_porch, m_vactive, MVFP2nd, MVTotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) m_hfront_porch = mipi_rx_read_word(it6161, 0x50) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) m_hsyncw = mipi_rx_read_word(it6161, 0x52) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) m_hback_porch = mipi_rx_read_word(it6161, 0x54) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) m_hactive = mipi_rx_read_word(it6161, 0x56) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) MHVR2nd = mipi_rx_read_word(it6161, 0x58) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) MHBlank = m_hfront_porch + m_hsyncw + m_hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) m_vfront_porch = mipi_rx_read_word(it6161, 0x5A) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) m_vsyncw = mipi_rx_read_word(it6161, 0x5C) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) m_vback_porch = mipi_rx_read_word(it6161, 0x5E) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) m_vactive = mipi_rx_read_word(it6161, 0x60) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) MVFP2nd = mipi_rx_read_word(it6161, 0x62) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) MVTotal = m_vfront_porch + m_vsyncw + m_vback_porch + m_vactive ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) DRM_INFO("m_hfront_porch = %d\n", m_hfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) DRM_INFO("m_hsyncw = %d\n", m_hsyncw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) DRM_INFO("m_hback_porch = %d\n", m_hback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) DRM_INFO("m_hactive = %d\n", m_hactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) DRM_INFO("MHVR2nd = %d\n", MHVR2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) DRM_INFO("MHBlank = %d\n", MHBlank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) DRM_INFO("m_vfront_porch = %d\n", m_vfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) DRM_INFO("m_vsyncw = %d\n", m_vsyncw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) DRM_INFO("m_vback_porch = %d\n", m_vback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) DRM_INFO("m_vactive = %d\n", m_vactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) DRM_INFO("MVFP2nd = %d\n", MVFP2nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) DRM_INFO("MVTotal = %d\n", MVTotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) static void mipi_rx_prec_get_display_mode(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) struct drm_display_mode *display_mode = &it6161->mipi_rx_p_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) struct device *dev = &it6161->i2c_hdmi_tx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) int p_hfront_porch, p_hsyncw, p_hback_porch, p_hactive, p_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) int p_vfront_porch, p_vsyncw, p_vback_porch, p_vactive, p_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) p_hfront_porch = mipi_rx_read_word(it6161, 0x30) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) p_hsyncw = mipi_rx_read_word(it6161, 0x32) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) p_hback_porch = mipi_rx_read_word(it6161, 0x34) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) p_hactive = mipi_rx_read_word(it6161, 0x36) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) p_htotal = mipi_rx_read_word(it6161, 0x38) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) //p_htotal = p_hfront_porch + p_hsyncw + p_hback_porch + p_hactive ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) p_vfront_porch = mipi_rx_read_word(it6161, 0x3A) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) p_vsyncw = mipi_rx_read_word(it6161, 0x3C) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) p_vback_porch = mipi_rx_read_word(it6161, 0x3E) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) p_vactive = mipi_rx_read_word(it6161, 0x40) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) p_vtotal = mipi_rx_read_word(it6161, 0x42) & 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) //p_vtotal = p_vfront_porch + p_vsyncw + p_vback_porch + p_vactive ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) display_mode->clock = it6161->mipi_rx_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) display_mode->hdisplay = p_hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) display_mode->hsync_start = p_hactive + p_hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) display_mode->hsync_end = p_hactive + p_hfront_porch + p_hsyncw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) display_mode->htotal = p_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) display_mode->vdisplay = p_vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) display_mode->vsync_start = p_vactive + p_vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) display_mode->vsync_end = p_vactive + p_vfront_porch + p_vsyncw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) display_mode->vtotal = p_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) DRM_DEV_DEBUG_DRIVER(dev, "mipi pixel clock: %d KHz", display_mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) DRM_INFO("p_hfront_porch = %d\r\n", p_hfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) DRM_INFO("p_hsyncw = %d\r\n", p_hsyncw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) DRM_INFO("p_hback_porch = %d\r\n", p_hback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) DRM_INFO("p_hactive = %d\r\n", p_hactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) DRM_INFO("p_htotal = %d\r\n", p_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) DRM_INFO("p_vfront_porch = %d\r\n", p_vfront_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) DRM_INFO("p_vsyncw = %d\r\n", p_vsyncw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) DRM_INFO("p_vback_porch = %d\r\n", p_vback_porch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) DRM_INFO("p_vactive = %d\r\n", p_vactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) DRM_INFO("p_vtotal = %d\r\n", p_vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) static void mipi_rx_reset_p_domain(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x04); // Video Clock Domain Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x00); // Release Video Clock Domain Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) static void it6161_mipi_rx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg07, u8 reg08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) it6161_mipi_rx_write(it6161, 0x06, reg06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) it6161_mipi_rx_write(it6161, 0x07, reg07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) it6161_mipi_rx_write(it6161, 0x08, reg08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) it6161_debug("mipi rx i2c read reg06:0x%02x reg07:0x%02x reg08:0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) it6161_mipi_rx_read(it6161, 0x06), it6161_mipi_rx_read(it6161, 0x07), it6161_mipi_rx_read(it6161, 0x08));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) static void it6161_mipi_rx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) bool m_video_stable, p_video_stable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) #ifndef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) struct drm_display_mode *dmt_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) u8 data_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) if (reg06 == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) if (reg06 & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) m_video_stable = mipi_rx_get_m_video_stable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) DRM_INFO("PPS M video stable Change Interrupt, %sstable", m_video_stable ? "" : "un");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) if (m_video_stable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) data_id = it6161_mipi_rx_read(it6161, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) DRM_INFO("mipi receive video format: 0x%02x", data_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) mipi_rx_calc_rclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) mipi_rx_calc_mclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) mipi_rx_show_mrec(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) mipi_rx_afe_configuration(it6161, data_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) mipi_rx_reset_p_domain(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) if(reg06 & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) DRM_INFO("PPS MHSync error interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) if(reg06 & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) DRM_INFO("PPS MHDE Error Interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) if(reg06 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) DRM_INFO("PPS MVSync Error Interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) if (reg06 & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) p_video_stable = mipi_rx_get_p_video_stable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) DRM_INFO("PPS P video stable Change Interrupt, %sstable", p_video_stable ? "" : "un");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) it6161_debug("cancel restart work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) cancel_delayed_work(&it6161->restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) if (p_video_stable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) DRM_INFO("PVidStb Change to HIGH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) mipi_rx_calc_rclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) mipi_rx_calc_pclk(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) mipi_rx_prec_get_display_mode(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) it6161->vic = drm_match_cea_mode(&it6161->mipi_rx_p_display_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) #ifndef __linux__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) if (it6161->vic == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) dmt_display_mode = drm_match_dmt_mode(&it6161->mipi_rx_p_display_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) if (dmt_display_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) it6161->source_display_mode = *dmt_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) DRM_INFO("%sfind dmt timing", dmt_display_mode ? "" : "not ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) it6161->source_display_mode = edid_cea_modes[it6161->vic];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) DRM_INFO("source output vic: %d, %s cea timing", it6161->vic, it6161->vic ? " standard" : " not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) show_display_mode(it6161, &it6161->source_display_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) show_display_mode(it6161, &it6161->mipi_rx_p_display_mode, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) mipi_rx_setup_polarity(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) it6161_mipi_rx_write(it6161, 0xC0,(EnTxCRC<<7) +TxCRCnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) // setup 1 sec timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) it6161_mipi_rx_set_bits(it6161, 0x0b,0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) switch (it6161->hdmi_tx_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) case HDMI_TX_BY_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) case HDMI_TX_ENABLE_DE_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) hdmi_tx_generate_blank_timing(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) case HDMI_TX_ENABLE_PATTERN_GENERATOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) hdmi_tx_setup_pattern_generator(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) DRM_INFO("use hdmi tx normal mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) hdmi_tx_video_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) if(reg06 & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) if(DisPHSyncErr == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) DRM_INFO("PPS PHSync Error Interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) if(reg06 & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) DRM_INFO("PPS PHDE Error Interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) if(reg06 & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) DRM_INFO("PPS MVDE Error Interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) static void it6161_mipi_rx_interrupt_reg07_process(struct it6161 *it6161, u8 reg07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) if (reg07 == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) if(reg07 & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) DRM_INFO("PatGen PPGVidStb change interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) if(reg07 & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) DRM_INFO("PPS Data Byte Error Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) if(reg07 & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) DRM_INFO("PPS CMOff Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) if(reg07 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) DRM_INFO("PPS CMOn Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) if(reg07 & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) DRM_INFO("PPS ShutDone cmd Interrupt !!! \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) if(reg07 & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) DRM_INFO("PPS TurnOn Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) if((reg07 & 0x40) || (reg07 & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) if( reg07&0x40 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) DRM_INFO("PPS FIFO over read Interrupt !!! tx video stable:%d", hdmi_tx_get_video_state(it6161));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) it6161_mipi_rx_set_bits(it6161, 0x07, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) if( reg07&0x80 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) DRM_INFO("PPS FIFO over write Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) it6161_mipi_rx_set_bits(it6161, 0x07, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) static void it6161_mipi_rx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) int crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) if (reg08 == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) if(reg08 & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) if(DisECCErr == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) DRM_INFO("ECC 1-bit Error Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) if(reg08 & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) if(DisECCErr == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) DRM_INFO("ECC 2-bit Error Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) if(reg08 & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) DRM_INFO("LM FIFO Error Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) if(reg08 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) DRM_INFO("CRC Error Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) if(reg08 & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) DRM_INFO("MCLK Off Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) //DRM_INFO("setP1_6 High Mipi not Stable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) //P1_6=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) if(reg08 & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) DRM_INFO("PPI FIFO OverWrite Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) if(reg08 & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) DRM_INFO("FW Timer Interrupt !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) it6161_mipi_rx_set_bits(it6161, 0x0b, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) if((it6161_mipi_rx_read(it6161, 0xC1)&0x03) == 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) DRM_INFO("CRC Fail !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) if((it6161_mipi_rx_read(it6161, 0xC1)&0x05) == 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) DRM_INFO("CRC Pass !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) crc = it6161_mipi_rx_read(it6161, 0xC2) + (it6161_mipi_rx_read(it6161, 0xC3) <<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) DRM_INFO("CRCR = 0x%x !!!\n" , crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) crc = it6161_mipi_rx_read(it6161, 0xC4) + (it6161_mipi_rx_read(it6161, 0xC5) <<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) DRM_INFO("CRCG = 0x%x !!!\n" , crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) crc = it6161_mipi_rx_read(it6161, 0xC6) + (it6161_mipi_rx_read(it6161, 0xC7) <<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) DRM_INFO("CRCB = 0x%x !!!\n" , crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) static void it6161_hdmi_tx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg07, u8 reg08, u8 regee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) u8 int_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) if(reg06 & B_TX_INT_AUD_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) DRM_INFO("B_TX_INT_AUD_OVERFLOW");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST), (B_HDMITX_AUD_RST|B_TX_AREF_RST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST|B_TX_AREF_RST, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) //AudioDelayCnt=AudioOutDelayCnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) //LastRefaudfreqnum=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) if(reg06 & B_TX_INT_DDCFIFO_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) DRM_INFO("DDC FIFO Error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) it6161_hdmi_tx_clear_ddc_fifo(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) hdmiTxDev[0].bAuthenticated= false ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) if(reg06 & B_TX_INT_DDC_BUS_HANG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) DRM_INFO("DDC BUS HANG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) it6161_hdmi_tx_abort_ddc(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) if (hdmiTxDev[0].bAuthenticated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) DRM_INFO("when DDC hang,and aborted DDC,the HDCP authentication need to restart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) #ifndef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) #ifdef ENABLE_HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) hdmitx_hdcp_ResumeAuthentication(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) TxHDCP_chg(TxHDCP_AuthFail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) /* clear ext interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) it6161_hdmi_tx_write(it6161, 0xEE, regee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) /* write B_TX_INTACTDONE '1' to trigger clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) int_clear = (it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)) | B_TX_CLR_AUD_CTS | B_TX_INTACTDONE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS, int_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) it6161_debug("hdmi tx i2c read reg06:0x%02x reg07:0x%02x reg08:0x%02x regee:0x%02x", it6161_hdmi_tx_read(it6161, 0x06), it6161_hdmi_tx_read(it6161, 0x07), it6161_hdmi_tx_read(it6161, 0x08), it6161_hdmi_tx_read(it6161, 0xEE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) static void it6161_hdmi_tx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) u8 ret;//, reg0e = it6161_hdmi_tx_read(it6161, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) if(reg06 & B_TX_INT_HPD_PLUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) drm_helper_hpd_irq_event(it6161->connector.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) if(hdmi_tx_get_sink_hpd(it6161)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) DRM_INFO("hpd on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) ret = wait_for_completion_timeout(&it6161->wait_edid_complete, msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) DRM_INFO("wait edid timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) it6161->hdmi_tx_output_color_space = OUTPUT_COLOR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) it6161->hdmi_tx_input_color_space = INPUT_COLOR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) hdmi_tx_set_capability_from_edid_parse(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) reinit_completion(&it6161->wait_hdcp_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) hdmi_tx_video_reset(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) bChangeMode=true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) // 1. not only HDMI but DVI need the set the upstream HPD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) // 2. Before set upstream HPD , the EDID must be ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) DRM_INFO("hpd off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) hdmi_tx_disable_video_output(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) kfree(it6161->edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) it6161->edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) if (it6161->hdmi_tx_mode == HDMI_TX_ENABLE_PATTERN_GENERATOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) hdmi_tx_disable_pattern_generator(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) if (reg06 & B_TX_INT_RX_SENSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) DRM_INFO("rx sense interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) hdmiTxDev[0].bAuthenticated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) static void it6161_hdmi_tx_interrupt_reg07_process(struct it6161 *it6161, u8 reg07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) bool video_state = hdmi_tx_get_video_state(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) if(reg07 & B_TX_INT_AUTH_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) DRM_INFO("hdmi tx authenticate done interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) hdmi_tx_hdcp_int_mask_disable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) hdmiTxDev[0].bAuthenticated = true ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) it6161_hdmi_tx_set_av_mute(it6161, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) complete(&it6161->wait_hdcp_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) if(reg07 & B_TX_INT_AUTH_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) hdmiTxDev[0].bAuthenticated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) DRM_INFO("hdmi tx interrupt authenticate fail reg46:0x%02x, start HDCP again", it6161_hdmi_tx_read(it6161, 0x46));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) complete(&it6161->wait_hdcp_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) #ifdef ENABLE_HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) hdmi_tx_enable_hdcp(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) #ifdef _SUPPORT_HDCP_REPEATER_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) TxHDCP_chg(TxHDCP_AuthFail) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) if(reg07 & B_TX_INT_KSVLIST_CHK ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) DRM_INFO("ksv list event interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) schedule_work(&it6161->wait_hdcp_ksv_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) if (reg07 & B_TX_INT_VID_UNSTABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) if (!video_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) DRM_INFO("hdmi tx interrupt video unstable!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) static void it6161_hdmi_tx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) if (reg08 & B_TX_INT_VIDSTABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) it6161_hdmi_tx_write(it6161, REG_TX_INT_STAT3, reg08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) if (hdmi_tx_get_video_state(it6161)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) DRM_INFO("hdmi tx interrupt video stable link status:%d, rx reg0d:0x%02x start HDCP", getHDMITX_LinkStatus(), it6161_mipi_rx_read(it6161, 0x0D));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) hdmi_tx_get_display_mode(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) show_display_mode(it6161, &it6161->source_display_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) show_display_mode(it6161, &it6161->hdmi_tx_display_mode, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) hdmi_tx_set_output_process(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) #ifdef ENABLE_HDCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) hdmi_tx_enable_hdcp(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) static void it6161_hdmi_tx_interrupt_regee_process(struct it6161 *it6161, u8 regee)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) if (regee != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) DRM_INFO("%s%s%s%s%s%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) (regee & 0x40) ? "video parameter change ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) (regee & 0x20) ? "HDCP Pj check done ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) (regee & 0x10) ? "HDCP Ri check done ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) (regee & 0x8) ? "DDC bus hang ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) (regee & 0x4) ? "Video input FIFO auto reset ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) (regee & 0x2) ? "No audio input interrupt ":"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) (regee & 0x1) ? "Audio decode error interrupt ":"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) static irqreturn_t it6161_intp_threaded_handler(int unused, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) struct it6161 *it6161 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) //struct device *dev = &it6161->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) u8 mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08, mipi_rx_reg0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) u8 hdmi_tx_reg06, hdmi_tx_reg07, hdmi_tx_reg08, hdmi_tx_regee, hdmi_tx_reg0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) //it6161_dump = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) if (it6161->enable_drv_hold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) mipi_rx_reg06 = it6161_mipi_rx_read(it6161, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) mipi_rx_reg07 = it6161_mipi_rx_read(it6161, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) mipi_rx_reg08 = it6161_mipi_rx_read(it6161, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) mipi_rx_reg0d = it6161_mipi_rx_read(it6161, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) hdmi_tx_reg06 = it6161_hdmi_tx_read(it6161, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) hdmi_tx_reg07 = it6161_hdmi_tx_read(it6161, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) hdmi_tx_reg08 = it6161_hdmi_tx_read(it6161, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) hdmi_tx_reg0e = it6161_hdmi_tx_read(it6161, 0x0E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) hdmi_tx_regee = it6161_hdmi_tx_read(it6161, 0xEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) if ((mipi_rx_reg06 != 0) || (mipi_rx_reg07 != 0) || (mipi_rx_reg08 != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) it6161_debug("rx reg06: 0x%02x reg07:0x%02x reg08:0x%02x reg0d:0x%02x", mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08, mipi_rx_reg0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) it6161_mipi_rx_interrupt_clear(it6161, mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) if ((hdmi_tx_reg06 != 0) || (hdmi_tx_reg07 != 0) || (hdmi_tx_reg08 != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) it6161_debug("tx reg06: 0x%02x reg07: 0x%02x reg08: 0x%02x reg0e: 0x%02x regee: 0x%02x", hdmi_tx_reg06, hdmi_tx_reg07, hdmi_tx_reg08, hdmi_tx_reg0e, hdmi_tx_regee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) it6161_hdmi_tx_interrupt_clear(it6161, hdmi_tx_reg06, hdmi_tx_reg07, hdmi_tx_reg08, hdmi_tx_regee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) it6161_mipi_rx_interrupt_reg08_process(it6161, mipi_rx_reg08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) it6161_mipi_rx_interrupt_reg06_process(it6161, mipi_rx_reg06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) it6161_mipi_rx_interrupt_reg07_process(it6161, mipi_rx_reg07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) it6161_hdmi_tx_interrupt_reg06_process(it6161, hdmi_tx_reg06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) it6161_hdmi_tx_interrupt_reg07_process(it6161, hdmi_tx_reg07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) it6161_hdmi_tx_interrupt_reg08_process(it6161, hdmi_tx_reg08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) it6161_hdmi_tx_interrupt_regee_process(it6161, hdmi_tx_regee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) it6161_debug("end %s", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) static void mipirx_restart(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) it6161_debug("****it6161: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) it6161_bridge_enable(it6161_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) static ssize_t enable_drv_hold_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) return scnprintf(buf, PAGE_SIZE, "drv_hold: %d\n", it6161->enable_drv_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) static ssize_t enable_drv_hold_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) unsigned int drv_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) if (kstrtoint(buf, 10, &drv_hold) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) it6161->enable_drv_hold = !!drv_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) if (it6161->enable_drv_hold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) it6161_mipi_rx_int_mask_disable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) it6161_hdmi_tx_int_mask_disable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) it6161_mipi_rx_interrupt_clear(it6161, 0xFF, 0xFF, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) it6161_hdmi_tx_interrupt_clear(it6161, 0xFF, 0xFF, 0xFF, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) it6161_mipi_rx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) it6161_hdmi_tx_int_mask_enable(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) static ssize_t hdmi_output_color_space_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) DRM_INFO("config color space: %s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) if (strncmp(buf, "ycbcr444", strlen(buf) - 1) == 0 || strncmp(buf, "yuv444", strlen(buf) - 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) it6161->hdmi_tx_output_color_space |= F_MODE_YUV444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) if (strncmp(buf, "ycbcr422", strlen(buf) - 1) == 0 || strncmp(buf, "yuv422", strlen(buf) - 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) it6161->hdmi_tx_output_color_space |= F_MODE_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) if (strncmp(buf, "rgb444", strlen(buf) - 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) it6161->hdmi_tx_output_color_space |= F_MODE_RGB444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) DRM_INFO("not support this color space, only support ycbcr444/yuv444, ycbcr422/yuv422, rgb444");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) DRM_INFO("config color space: %s value:0x%02x", buf, it6161->hdmi_tx_output_color_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) static ssize_t hdmi_output_color_space_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) char *str = buf, *end = buf + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) str += scnprintf(str, end - str, "it6161->hdmi_tx_output_color_space:%d\n", it6161->hdmi_tx_output_color_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) return str - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) static ssize_t print_timing_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) struct drm_display_mode *vid = &it6161->source_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) char *str = buf, *end = buf + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) str += scnprintf(str, end - str, "---video timing---\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n", vid->clock / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) vid->clock % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) str += scnprintf(str, end - str, "HFrontPorch:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) vid->hsync_start - vid->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) str += scnprintf(str, end - str, "HSyncWidth:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) vid->hsync_end - vid->hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) str += scnprintf(str, end - str, "HBackPorch:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) vid->htotal - vid->hsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) str += scnprintf(str, end - str, "VFrontPorch:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) vid->vsync_start - vid->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) str += scnprintf(str, end - str, "VSyncWidth:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) vid->vsync_end - vid->vsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) str += scnprintf(str, end - str, "VBackPorch:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) vid->vtotal - vid->vsync_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) return str - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) static ssize_t sha_debug_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) char *str = buf, *end = buf + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) str += scnprintf(str, end - str, "sha input:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) for (i = 0; i < ARRAY_SIZE(it6161->sha1_input); i += 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) str += scnprintf(str, end - str, "%16ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) it6161->sha1_input + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) str += scnprintf(str, end - str, "av:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) for (i = 0; i < ARRAY_SIZE(it6161->av); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) str += scnprintf(str, end - str, "%4ph\n", it6161->av[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) str += scnprintf(str, end - str, "bv:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) for (i = 0; i < ARRAY_SIZE(it6161->bv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) str += scnprintf(str, end - str, "%4ph\n", it6161->bv[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) return end - str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) static ssize_t enable_hdcp_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) return scnprintf(buf, PAGE_SIZE, "%d\n", it6161->enable_hdcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) static ssize_t enable_hdcp_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) unsigned int reg3f, hdcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) if (kstrtoint(buf, 10, &hdcp) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) if (!it6161->powered || it6161->state == SYS_UNPLUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) DRM_DEV_DEBUG_DRIVER(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) "power down or unplug, can not fire HDCP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) it6161->enable_hdcp = hdcp ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) if (it6161->enable_hdcp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) if (it6161->cp_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) dptx_sys_chg(it6161, SYS_HDCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) dptx_sys_fsm(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) DRM_DEV_ERROR(dev, "sink not support HDCP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) dptx_set_bits(it6161, 0x05, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) dptx_set_bits(it6161, 0x05, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) reg3f = dptx_read(it6161, 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) hdcp = (reg3f & BIT(7)) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) DRM_DEV_DEBUG_DRIVER(dev, "%s to disable hdcp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) hdcp ? "failed" : "succeeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) static ssize_t force_pwronoff_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) int pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) if (kstrtoint(buf, 10, &pwr) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) if (pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) it6161_poweron(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) it6161_poweroff(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) static ssize_t pwr_state_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) struct it6161 *it6161 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) return scnprintf(buf, PAGE_SIZE, "%d\n", it6161->powered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) static DEVICE_ATTR_RO(print_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) static DEVICE_ATTR_RO(pwr_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) static DEVICE_ATTR_RO(sha_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) static DEVICE_ATTR_WO(force_pwronoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) static DEVICE_ATTR_RW(enable_hdcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) static const struct attribute *it6161_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) &dev_attr_enable_drv_hold.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) &dev_attr_print_timing.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) &dev_attr_sha_debug.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) &dev_attr_enable_hdcp.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) &dev_attr_force_pwronoff.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) &dev_attr_pwr_state.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) static void it6161_shutdown(struct i2c_client *i2c_mipi_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) struct it6161 *it6161 = dev_get_drvdata(&i2c_mipi_rx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) dptx_sys_chg(it6161, SYS_UNPLUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) static DEVICE_ATTR_RW(enable_drv_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) static DEVICE_ATTR_RW(hdmi_output_color_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) static const struct attribute *it6161_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) &dev_attr_enable_drv_hold.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) &dev_attr_hdmi_output_color_space.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) static int it6161_parse_dt(struct it6161 *it6161, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) //struct device *dev = &adv->i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) it6161->host_node = of_graph_get_remote_node(np, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) if (!it6161->host_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) DRM_INFO("no host node");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) DRM_INFO("%s", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) of_node_put(it6161->host_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) static int it6161_gpio_init(struct it6161 *it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) struct device *dev = it6161->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) it6161->enable_gpio = devm_gpiod_get_optional(dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) if (IS_ERR(it6161->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) dev_err(dev, "failed to acquire enable gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) return PTR_ERR(it6161->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) it6161->test_gpio = devm_gpiod_get_optional(dev, "test",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) if (IS_ERR(it6161->test_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) dev_info(dev, "failed to acquire test gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) gpiod_set_value_cansleep(it6161->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) static int it6161_i2c_probe(struct i2c_client *i2c_mipi_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) //struct it6161 *it6161;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) struct device *dev = &i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) int err, intp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) it6161 = devm_kzalloc(dev, sizeof(*it6161), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) if (!it6161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) it6161_bridge = devm_kzalloc(dev, sizeof(*it6161), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) if (!it6161_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) it6161->i2c_mipi_rx = i2c_mipi_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) it6161->dev = &i2c_mipi_rx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) // mutex_init(&it6161->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) mutex_init(&it6161->mode_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) //init_completion(&it6161->wait_hdcp_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) init_completion(&it6161->wait_edid_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) //INIT_DELAYED_WORK(&it6161->hdcp_work, hdmi_tx_hdcp_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) //INIT_WORK(&it6161->wait_hdcp_ksv_list, hdmi_tx_hdcp_auth_part2_process);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) // init_waitqueue_head(&it6161->edid_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) /* set up mipirx restart work*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) INIT_DELAYED_WORK(&it6161->restart, mipirx_restart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) it6161->bridge.of_node = i2c_mipi_rx->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) it6161_parse_dt(it6161, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) it6161_gpio_init(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) it6161->regmap_mipi_rx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) devm_regmap_init_i2c(i2c_mipi_rx, &it6161_mipi_rx_bridge_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) if (IS_ERR(it6161->regmap_mipi_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) DRM_DEV_ERROR(dev, "regmap_mipi_rx i2c init failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) return PTR_ERR(it6161->regmap_mipi_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) if (device_property_read_u32(dev, "it6161-addr-hdmi-tx", &it6161->it6161_addr_hdmi_tx) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) it6161->it6161_addr_hdmi_tx = 0x4c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) it6161->i2c_hdmi_tx = i2c_new_dummy_device(i2c_mipi_rx->adapter, it6161->it6161_addr_hdmi_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) if (IS_ERR(it6161->i2c_hdmi_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) DRM_DEV_ERROR(dev, "Failed to register it6161 I2C device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) return PTR_ERR(it6161->i2c_hdmi_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) it6161->regmap_hdmi_tx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) devm_regmap_init_i2c(it6161->i2c_hdmi_tx, &it6161_hdmi_tx_bridge_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) if (IS_ERR(it6161->regmap_hdmi_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) DRM_DEV_ERROR(dev, "regmap_hdmi_tx i2c init failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) err = PTR_ERR(it6161->regmap_hdmi_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) goto err_hdmitx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) if (device_property_read_u32(dev, "it6161-addr-cec", &it6161->it6161_addr_cec) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) it6161->it6161_addr_cec = 0x4E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) it6161->i2c_cec = i2c_new_dummy_device(i2c_mipi_rx->adapter, it6161->it6161_addr_cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) if (IS_ERR(it6161->i2c_cec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) DRM_DEV_ERROR(dev, "i2c_cec init failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) err = PTR_ERR(it6161->i2c_cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) goto err_hdmitx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) it6161->regmap_cec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) devm_regmap_init_i2c(it6161->i2c_cec, &it6161_cec_bridge_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) if (IS_ERR(it6161->regmap_cec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) DRM_DEV_ERROR(dev, "regmap_cec i2c init failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) err = PTR_ERR(it6161->regmap_cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) goto err_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) if (!it6161_check_device_ready(it6161)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) goto err_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) it6161->enable_drv_hold = DEFAULT_DRV_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) it6161_set_interrupts_active_level(HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) intp_irq = i2c_mipi_rx->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) if (!intp_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) DRM_DEV_ERROR(dev, "it6112 failed to get INTP IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) goto err_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) err = devm_request_threaded_irq(&i2c_mipi_rx->dev, intp_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) /*it6161_intp_threaded_handler,*/it6161_intp_threaded_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) "it6161-intp", it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) DRM_DEV_ERROR(dev, "it6112 failed to request INTP threaded IRQ: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) goto err_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) i2c_set_clientdata(i2c_mipi_rx, it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) it6161->bridge.funcs = &it6161_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) drm_bridge_add(&it6161->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) err_cec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) i2c_unregister_device(it6161->i2c_cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) err_hdmitx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) i2c_unregister_device(it6161->i2c_hdmi_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) static int it6161_remove(struct i2c_client *i2c_mipi_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) struct it6161 *it6161 = i2c_get_clientdata(i2c_mipi_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) drm_connector_unregister(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) drm_connector_cleanup(&it6161->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) drm_bridge_remove(&it6161->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) // sysfs_remove_files(&i2c_mipi_rx->dev.kobj, it6161_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) // drm_dp_aux_unregister(&it6161->aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) // it6161_poweroff(it6161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) static const struct i2c_device_id it6161_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) { "it6161", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) MODULE_DEVICE_TABLE(i2c, it6161_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) static const struct of_device_id it6161_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) { .compatible = "ite,it6161" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) static struct i2c_driver it6161_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) .name = "it6161_mipirx_hdmitx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) .of_match_table = it6161_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) //.pm = &it6161_bridge_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) .probe = it6161_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) //.remove = it6161_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) //.shutdown = it6161_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) .id_table = it6161_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) module_i2c_driver(it6161_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) MODULE_AUTHOR("allen chen <allen.chen@ite.com.tw>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) MODULE_DESCRIPTION("it6161 HDMI Transmitter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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