^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Chrontel CH7033 Video Encoder Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019,2020 Lubomir Rintel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <drm/drm_edid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <drm/drm_of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <drm/drm_print.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Page 0, Register 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DRI_PD = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) IO_PD = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Page 0, Register 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DRI_PDDRI = GENMASK(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PDDAC = GENMASK(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PANEN = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Page 0, Register 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DPD = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GCKOFF = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TV_BP = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SCLPD = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SDPD = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VGA_PD = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) HDBKPD = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HDMI_PD = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Page 0, Register 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MEMINIT = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MEMIDLE = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MEMPD = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) STOP = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) LVDS_PD = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) HD_DVIB = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) HDCP_PD = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MCU_PD = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Page 0, Register 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IDF = GENMASK(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) INTEN = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SWAP = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BYTE_SWAP_RGB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BYTE_SWAP_RBG = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BYTE_SWAP_GRB = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BYTE_SWAP_GBR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BYTE_SWAP_BRG = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BYTE_SWAP_BGR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Page 0, Register 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HPO_I = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VPO_I = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEPO_I = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CRYS_EN = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GCLKFREQ = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Page 0, Register 0x2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) HFLIP = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) VFLIP = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEPO_O = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) HPO_O = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) VPO_O = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) TE = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Page 0, Register 0x2b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SWAPS = GENMASK(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VFMT = GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Page 0, Register 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) COMP_BP = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DAC_EN_T = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) HWO_HDMI_HI = GENMASK(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HOO_HDMI_HI = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Page 0, Register 0x57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FLDSEN = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) VWO_HDMI_HI = GENMASK(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) VOO_HDMI_HI = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Page 0, Register 0x7e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) HDMI_LVDS_SEL = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DE_GEN = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PWM_INDEX_HI = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) USE_DE = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) R_INT = GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Page 1, Register 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BPCKSEL = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DRI_CMFB_EN = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CEC_PUEN = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CEC_T = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CKINV = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CK_TVINV = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DRI_CKS2 = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Page 1, Register 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DACG = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DACKTST = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEDGEB = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SYO = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DRI_IT_LVDS = GENMASK(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DISPON = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Page 1, Register 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DRI_PLL_CP = GENMASK(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DRI_PLL_DIVSEL = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DRI_PLL_N1_1 = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DRI_PLL_N1_0 = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DRI_PLL_N3_1 = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DRI_PLL_N3_0 = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DRI_PLL_CKTSTEN = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Page 1, Register 0x6b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) VCO3CS = GENMASK(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ICPGBK2_0 = GENMASK(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DRI_VCO357SC = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PDPLL2 = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DRI_PD_SER = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Page 1, Register 0x6c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PLL2N11 = GENMASK(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PLL2N5_4 = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PLL2N5_TOP = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DRI_PLL_PD = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PD_I2CM = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Page 3, Register 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DIFF_EN = GENMASK(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CORREC_EN = GENMASK(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) VGACLK_BP = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) HM_LV_SEL = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) HD_VGA_SEL = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Page 3, Register 0x2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LVDSCLK_BP = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) HDTVCLK_BP = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) HDMICLK_BP = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) HDTV_BP = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) HDMI_BP = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) THRWL = GENMASK(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Page 4, Register 0x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PGM_ARSTB = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MCU_ARSTB = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MCU_RETB = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) RESETIB = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RESETDB = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ch7033_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct drm_bridge *next_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define conn_to_ch7033_priv(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) container_of(x, struct ch7033_priv, connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define bridge_to_ch7033_priv(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) container_of(x, struct ch7033_priv, bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static enum drm_connector_status ch7033_connector_detect(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct drm_connector *connector, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return drm_bridge_detect(priv->next_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct drm_connector_funcs ch7033_connector_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .reset = drm_atomic_helper_connector_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .fill_modes = drm_helper_probe_single_connector_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .detect = ch7033_connector_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .destroy = drm_connector_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ch7033_connector_get_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct edid *edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) edid = drm_bridge_get_edid(priv->next_bridge, connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) drm_connector_update_edid_property(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (edid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = drm_add_edid_modes(connector, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) kfree(edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = drm_add_modes_noedid(connector, 1920, 1080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) drm_set_preferred_mode(connector, 1024, 768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct drm_encoder *ch7033_connector_best_encoder(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return priv->bridge.encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .get_modes = ch7033_connector_get_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .best_encoder = ch7033_connector_best_encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void ch7033_hpd_event(void *arg, enum drm_connector_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ch7033_priv *priv = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (priv->bridge.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) drm_helper_hpd_irq_event(priv->connector.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int ch7033_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct drm_connector *connector = &priv->connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DRM_BRIDGE_ATTACH_NO_CONNECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) connector->polled = DRM_CONNECTOR_POLL_HPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) connector->polled = DRM_CONNECTOR_POLL_CONNECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DRM_CONNECTOR_POLL_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) drm_bridge_hpd_enable(priv->next_bridge, ch7033_hpd_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) drm_connector_helper_add(connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &ch7033_connector_helper_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = drm_connector_init_with_ddc(bridge->dev, &priv->connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) &ch7033_connector_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) priv->next_bridge->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) priv->next_bridge->ddc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DRM_ERROR("Failed to initialize connector\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return drm_connector_attach_encoder(&priv->connector, bridge->encoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void ch7033_bridge_detach(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) drm_bridge_hpd_disable(priv->next_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) drm_connector_cleanup(&priv->connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (mode->clock > 165000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return MODE_CLOCK_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (mode->hdisplay >= 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return MODE_BAD_HVALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (mode->vdisplay >= 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return MODE_BAD_VVALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void ch7033_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) regmap_write(priv->regmap, 0x03, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regmap_update_bits(priv->regmap, 0x52, RESETDB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void ch7033_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) regmap_write(priv->regmap, 0x03, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regmap_update_bits(priv->regmap, 0x52, RESETDB, RESETDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const struct drm_display_mode *adjusted_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int hbporch = mode->hsync_start - mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int hsynclen = mode->hsync_end - mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int vbporch = mode->vsync_start - mode->vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int vsynclen = mode->vsync_end - mode->vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Page 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) regmap_write(priv->regmap, 0x03, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Turn everything off to set all the registers to their defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) regmap_write(priv->regmap, 0x52, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Bring I/O block up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) regmap_write(priv->regmap, 0x52, RESETIB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Page 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) regmap_write(priv->regmap, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Bring up parts we need from the power down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) regmap_update_bits(priv->regmap, 0x07, DRI_PD | IO_PD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) regmap_update_bits(priv->regmap, 0x08, DRI_PDDRI | PDDAC | PANEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_update_bits(priv->regmap, 0x09, DPD | GCKOFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) HDMI_PD | VGA_PD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) regmap_update_bits(priv->regmap, 0x0a, HD_DVIB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Horizontal input timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (mode->hdisplay >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) regmap_write(priv->regmap, 0x0c, mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regmap_write(priv->regmap, 0x0d, mode->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (hbporch >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regmap_write(priv->regmap, 0x0f, hbporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) regmap_write(priv->regmap, 0x10, hsynclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Vertical input timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (mode->vdisplay >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) regmap_write(priv->regmap, 0x12, mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) regmap_write(priv->regmap, 0x13, mode->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (vbporch >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regmap_write(priv->regmap, 0x15, vbporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regmap_write(priv->regmap, 0x16, vsynclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Input color swap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Input clock and sync polarity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mode->clock >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regmap_write(priv->regmap, 0x1a, mode->clock >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regmap_write(priv->regmap, 0x1b, mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Horizontal output timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (mode->hdisplay >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regmap_write(priv->regmap, 0x20, mode->hdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regmap_write(priv->regmap, 0x21, mode->htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Vertical output timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (mode->vdisplay >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) regmap_write(priv->regmap, 0x26, mode->vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regmap_write(priv->regmap, 0x27, mode->vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* VGA channel bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) regmap_update_bits(priv->regmap, 0x2b, VFMT, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Output sync polarity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* HDMI horizontal output timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (hsynclen >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (hbporch >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_write(priv->regmap, 0x55, hbporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regmap_write(priv->regmap, 0x56, hsynclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* HDMI vertical output timing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) regmap_update_bits(priv->regmap, 0x57, VWO_HDMI_HI | VOO_HDMI_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) (vsynclen >> 8) << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) (vbporch >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regmap_write(priv->regmap, 0x58, vbporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) regmap_write(priv->regmap, 0x59, vsynclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Pick HDMI, not LVDS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regmap_update_bits(priv->regmap, 0x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Page 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regmap_write(priv->regmap, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* No idea what these do, but VGA is wobbly and blinky without them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) regmap_update_bits(priv->regmap, 0x07, CKINV, CKINV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) regmap_update_bits(priv->regmap, 0x08, DISPON, DISPON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* DRI PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (mode->clock <= 40000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DRI_PLL_N1_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DRI_PLL_N3_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DRI_PLL_N3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else if (mode->clock < 80000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DRI_PLL_N1_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DRI_PLL_N3_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DRI_PLL_N3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DRI_PLL_N3_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DRI_PLL_N1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) regmap_update_bits(priv->regmap, 0x0c, DRI_PLL_N1_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DRI_PLL_N1_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DRI_PLL_N3_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DRI_PLL_N3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DRI_PLL_N3_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DRI_PLL_N1_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* This seems to be color calibration for VGA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regmap_update_bits(priv->regmap, 0x6b, DRI_PD_SER, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) regmap_update_bits(priv->regmap, 0x6c, DRI_PLL_PD, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Page 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) regmap_write(priv->regmap, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* More bypasses and apparently another HDMI/LVDS selector. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regmap_update_bits(priv->regmap, 0x28, VGACLK_BP | HM_LV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) VGACLK_BP | HM_LV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) regmap_update_bits(priv->regmap, 0x2a, HDMICLK_BP | HDMI_BP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) HDMICLK_BP | HDMI_BP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Page 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_write(priv->regmap, 0x03, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Output clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) regmap_write(priv->regmap, 0x10, mode->clock >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regmap_write(priv->regmap, 0x11, mode->clock >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_write(priv->regmap, 0x12, mode->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct drm_bridge_funcs ch7033_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .attach = ch7033_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .detach = ch7033_bridge_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .mode_valid = ch7033_bridge_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .disable = ch7033_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .enable = ch7033_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mode_set = ch7033_bridge_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct regmap_config ch7033_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .max_register = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int ch7033_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ch7033_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &priv->next_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(&client->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = regmap_read(priv->regmap, 0x00, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(&client->dev, "error reading the model id: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if ((val & 0xf7) != 0x56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&client->dev, "the device is not a ch7033\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) regmap_write(priv->regmap, 0x03, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = regmap_read(priv->regmap, 0x51, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(&client->dev, "error reading the model id: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if ((val & 0x0f) != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(&client->dev, "unknown revision %u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) INIT_LIST_HEAD(&priv->bridge.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) priv->bridge.funcs = &ch7033_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) priv->bridge.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) drm_bridge_add(&priv->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_info(dev, "Chrontel CH7033 Video Encoder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int ch7033_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct ch7033_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) drm_bridge_remove(&priv->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct of_device_id ch7033_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { .compatible = "chrontel,ch7033", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DEVICE_TABLE(of, ch7033_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct i2c_device_id ch7033_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { "ch7033", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DEVICE_TABLE(i2c, ch7033_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct i2c_driver ch7033_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .probe = ch7033_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .remove = ch7033_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "ch7033",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .of_match_table = of_match_ptr(ch7033_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .id_table = ch7033_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) module_i2c_driver(ch7033_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_DESCRIPTION("Chrontel CH7033 Video Encoder Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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