^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright: 2017 Cadence Design Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Boris Brezillon <boris.brezillon@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <drm/drm_atomic_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <drm/drm_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <drm/drm_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <drm/drm_mipi_dsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_panel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_probe_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <video/mipi_display.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/phy/phy-mipi-dphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IP_CONF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDI_IFACE_32 BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INTERNAL_DATAPATH_32 (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define INTERNAL_DATAPATH_16 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define INTERNAL_DATAPATH_8 (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCTL_MAIN_DATA_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TE_MIPI_POLLING_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TE_HW_POLLING_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DISP_EOT_GEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HOST_EOT_GEN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DISP_GEN_CHECKSUM BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DISP_GEN_ECC BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BTA_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define READ_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_TE_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IF_TE_EN(x) BIT(8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TVG_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VID_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IF_VID_SELECT(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IF_VID_SELECT_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IF_VID_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LINK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCTL_MAIN_PHY_CTL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HS_INVERT_CLK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SWAP_PINS_CLK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HS_SKEWCAL_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WAIT_BURST_TIME(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DATA_ULPM_EN(x) BIT(6 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_ULPM_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_CONTINUOUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DATA_LANE_EN(x) BIT((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCTL_MAIN_EN 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DATA_FORCE_STOP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_FORCE_STOP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IF_EN(x) BIT(13 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_LANE_ULPM_REQ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DATA_LANE_START(x) BIT(4 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_LANE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLL_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCTL_DPHY_CFG0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DPHY_C_RSTB BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DPHY_PLL_PDN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DPHY_CMN_PDN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DPHY_C_PDN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DPHY_ALL_D_PDN GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DPHY_PLL_PSO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DPHY_CMN_PSO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCTL_DPHY_TIMEOUT1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HSTX_TIMEOUT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HSTX_TIMEOUT_MAX GENMASK(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_DIV(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_DIV_MAX GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCTL_DPHY_TIMEOUT2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LPRX_TIMEOUT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCTL_ULPOUT_TIME 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_LANE_ULPOUT_TIME(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCTL_3DVIDEO_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VID_VSYNC_3D_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VID_VSYNC_3D_LR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VID_VSYNC_3D_SECOND_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VID_VSYNC_3DFORMAT_LINE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VID_VSYNC_3DMODE_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VID_VSYNC_3DMODE_PORTRAIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VID_VSYNC_3DMODE_LANDSCAPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCTL_MAIN_STS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCTL_MAIN_STS_CTL 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCTL_MAIN_STS_CLR 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCTL_MAIN_STS_FLAG 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HS_SKEWCAL_DONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LPRX_TIMEOUT_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HSTX_TIMEOUT_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DATA_LANE_RDY(l) BIT(2 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_LANE_RDY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PLL_LOCKED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCTL_DPHY_ERR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCTL_DPHY_ERR_CTL1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCTL_DPHY_ERR_CLR 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCTL_DPHY_ERR_FLAG 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ERR_CONTROL(l) BIT(14 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ERR_SYNESC(l) BIT(10 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ERR_ESC(l) BIT(6 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCTL_DPHY_ERR_CTL2 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ERR_CONTROL_EDGE(l) BIT(8 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ERR_ESC_EDGE(l) BIT(0 + (l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCTL_LANE_STS 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PPI_C_TX_READY_HS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DPHY_PLL_LOCK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LANE_STATE_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LANE_STATE_IDLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LANE_STATE_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LANE_STATE_ULPM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LANE_STATE_READ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DATA_LANE_STATE(l, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_LANE_STATE_HS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DSC_MODE_CTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DSC_MODE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DSC_CMD_SEND 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DSC_SEND_PPS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DSC_EXECUTE_QUEUE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DSC_PPS_WRDAT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DSC_MODE_STS 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DSC_PPS_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DSC_EXEC_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMD_MODE_CTL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IF_LP_EN(x) BIT(9 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CMD_MODE_CTL2 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TE_TIMEOUT(x) ((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FILL_VALUE(x) ((x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ARB_ROUND_ROBIN_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMD_MODE_STS 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CMD_MODE_STS_CTL 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMD_MODE_STS_CLR 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CMD_MODE_STS_FLAG 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ERR_IF_UNDERRUN(x) BIT(4 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ERR_UNWANTED_READ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ERR_TE_MISS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ERR_NO_TE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CSM_RUNNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DIRECT_CMD_SEND 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DIRECT_CMD_MAIN_SETTINGS 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TRIGGER_VAL(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CMD_LP_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMD_SIZE(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CMD_VCHAN_ID(x) ((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMD_DATATYPE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMD_LONG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define WRITE_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define READ_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TE_REQ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TRIGGER_REQ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BTA_REQ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DIRECT_CMD_STS 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DIRECT_CMD_STS_CTL 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DIRECT_CMD_STS_CLR 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DIRECT_CMD_STS_FLAG 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RCVD_ACK_VAL(val) ((val) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define READ_COMPLETED_WITH_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BTA_FINISHED BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BTA_COMPLETED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TE_RCVD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TRIGGER_RCVD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ACK_WITH_ERR_RCVD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ACK_RCVD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define READ_COMPLETED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TRIGGER_COMPLETED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define WRITE_COMPLETED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SENDING_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DIRECT_CMD_STOP_READ 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DIRECT_CMD_WRDATA 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DIRECT_CMD_FIFO_RST 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DIRECT_CMD_RDDATA 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DIRECT_CMD_RD_PROPS 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RD_DCS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RD_SIZE(val) ((val) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DIRECT_CMD_RD_STS 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DIRECT_CMD_RD_STS_CTL 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DIRECT_CMD_RD_STS_CLR 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DIRECT_CMD_RD_STS_FLAG 0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ERR_EOT_WITH_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ERR_MISSING_EOT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ERR_WRONG_LENGTH BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ERR_OVERSIZE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ERR_RECEIVE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ERR_UNDECODABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ERR_CHECKSUM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ERR_UNCORRECTABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ERR_FIXED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VID_MAIN_CTL 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VID_IGNORE_MISS_VSYNC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VID_FIELD_SW BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define VID_INTERLACED_EN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define RECOVERY_MODE(x) ((x) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RECOVERY_MODE_NEXT_HSYNC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define RECOVERY_MODE_NEXT_STOP_POINT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RECOVERY_MODE_NEXT_VSYNC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define REG_BLKEOL_MODE(x) ((x) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define REG_BLKLINE_MODE(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define REG_BLK_MODE_NULL_PKT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define REG_BLK_MODE_BLANKING_PKT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define REG_BLK_MODE_LP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SYNC_PULSE_HORIZONTAL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SYNC_PULSE_ACTIVE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BURST_MODE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VID_PIXEL_MODE_MASK GENMASK(17, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VID_PIXEL_MODE_RGB565 (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define VID_PIXEL_MODE_RGB666 (2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define VID_PIXEL_MODE_RGB888 (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define VID_PIXEL_MODE_RGB101010 (4 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VID_PIXEL_MODE_RGB121212 (5 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VID_PIXEL_MODE_YUV420 (8 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define VID_PIXEL_MODE_YUV422 (10 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define VID_PIXEL_MODE_YUV422_24B (11 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define VID_PIXEL_MODE_DSC_COMP (12 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define VID_DATATYPE(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define STOP_MODE(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define START_MODE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define VID_VSIZE1 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define VFP_LEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define VBP_LEN(x) ((x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define VSA_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define VID_VSIZE2 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define VACT_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define VID_HSIZE1 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HBP_LEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HSA_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define VID_HSIZE2 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HFP_LEN(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HACT_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define VID_BLKSIZE1 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BLK_EOL_PKT_LEN(x) ((x) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define BLK_LINE_EVENT_PKT_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define VID_BLKSIZE2 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BLK_LINE_PULSE_PKT_LEN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define VID_PKT_TIME 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BLK_EOL_DURATION(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define VID_DPHY_TIME 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define REG_WAKEUP_TIME(x) ((x) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define REG_LINE_DURATION(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define VID_ERR_COLOR1 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define COL_GREEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define COL_RED(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define VID_ERR_COLOR2 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PAD_VAL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define COL_BLUE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define VID_VPOS 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define LINE_POS(val) ((val) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define VID_HPOS 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HORIZ_POS(val) ((val) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define VID_MODE_STS 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define VID_MODE_STS_CTL 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define VID_MODE_STS_CLR 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define VID_MODE_STS_FLAG 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define VSG_RECOVERY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ERR_VRS_WRONG_LEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ERR_LONG_READ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ERR_LINE_WRITE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ERR_BURST_WRITE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ERR_SMALL_HEIGHT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ERR_SMALL_LEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ERR_MISSING_VSYNC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ERR_MISSING_HSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ERR_MISSING_DATA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define VSG_RUNNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define VID_VCA_SETTING1 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BURST_LP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MAX_BURST_LIMIT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define VID_VCA_SETTING2 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MAX_LINE_LIMIT(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define EXACT_BURST_LIMIT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TVG_CTL 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TVG_STRIPE_SIZE(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TVG_MODE_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TVG_MODE_SINGLE_COLOR (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TVG_MODE_VSTRIPES (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TVG_MODE_HSTRIPES (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TVG_STOPMODE_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TVG_STOPMODE_EOF (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TVG_STOPMODE_EOL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TVG_STOPMODE_NOW (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TVG_RUN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TVG_IMG_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TVG_NBLINES(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TVG_LINE_SIZE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TVG_COLOR1 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TVG_COL1_GREEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TVG_COL1_RED(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TVG_COLOR1_BIS 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TVG_COL1_BLUE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TVG_COLOR2 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TVG_COL2_GREEN(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TVG_COL2_RED(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TVG_COLOR2_BIS 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TVG_COL2_BLUE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TVG_STS 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TVG_STS_CTL 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TVG_STS_CLR 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TVG_STS_FLAG 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TVG_STS_RUNNING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define STS_CTL_EDGE(e) ((e) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DPHY_LANES_MAP 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DPI_IRQ_EN 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DPI_IRQ_CLR 0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DPI_IRQ_STS 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PIXEL_BUF_OVERFLOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DPI_CFG 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TEST_GENERIC 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TEST_STATUS(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TEST_CTRL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define ID_REG 0x1fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define REV_MINOR(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DSI_OUTPUT_PORT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DSI_INPUT_PORT(inputid) (1 + (inputid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DSI_HBP_FRAME_OVERHEAD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DSI_HSA_FRAME_OVERHEAD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DSI_HFP_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DSI_BLANKING_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DSI_NULL_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DSI_EOT_PKT_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct cdns_dsi_output {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct mipi_dsi_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct drm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) union phy_configure_opts phy_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) enum cdns_dsi_input_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CDNS_SDI_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CDNS_DPI_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CDNS_DSC_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct cdns_dsi_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned int hfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int hsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int hbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct cdns_dsi_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum cdns_dsi_input_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct drm_bridge bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct cdns_dsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct mipi_dsi_host base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct cdns_dsi_input input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct cdns_dsi_output output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int direct_cmd_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int rx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct completion direct_cmd_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct clk *dsi_p_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct reset_control *dsi_p_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct clk *dsi_sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) bool link_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct phy *dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return container_of(input, struct cdns_dsi, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return container_of(host, struct cdns_dsi, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline struct cdns_dsi_input *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bridge_to_cdns_dsi_input(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return container_of(bridge, struct cdns_dsi_input, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bool mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return mode->hsync_start - mode->hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return mode->crtc_hsync_start - mode->crtc_hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int dpi_bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int dsi_pkt_overhead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int dsi_timing = DIV_ROUND_UP(dpi_timing * dpi_bpp, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (dsi_timing < dsi_pkt_overhead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dsi_timing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dsi_timing -= dsi_pkt_overhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return dsi_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct cdns_dsi_cfg *dsi_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bool mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bool sync_pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) memset(dsi_cfg, 0, sizeof(*dsi_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) sync_pulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tmp = mode->htotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (sync_pulse ? mode->hsync_end : mode->hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tmp = mode->crtc_htotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) (sync_pulse ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mode->crtc_hsync_end : mode->crtc_hsync_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (sync_pulse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) tmp = mode->hsync_end - mode->hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tmp = mode->crtc_hsync_end - mode->crtc_hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DSI_HSA_FRAME_OVERHEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mode->hdisplay : mode->crtc_hdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bpp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bpp, DSI_HFP_FRAME_OVERHEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct cdns_dsi_cfg *dsi_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct phy_configure_opts_mipi_dphy *phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bool mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned long long dlane_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned long adj_dsi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long dsi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned long dpi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long dpi_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int dsi_hfp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int lanes = output->dev->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dsi_htotal += dsi_cfg->hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * Make sure DSI htotal is aligned on a lane boundary when calculating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * the expected data rate. This is done by extending HFP in case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * misalignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) adj_dsi_htotal = dsi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (dsi_htotal % lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) adj_dsi_htotal += lanes - (dsi_htotal % lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* data rate in bytes/sec is not an integer, refuse the mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (do_div(dlane_bps, lanes * dpi_htotal))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* data rate was in bytes/sec, convert to bits/sec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) phy_cfg->hs_clk_rate = dlane_bps * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dsi_cfg->hfp += dsi_hfp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct cdns_dsi_cfg *dsi_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool mode_valid_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned long dsi_hss_hsa_hse_hbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int nlanes = output->dev->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mipi_dsi_pixel_format_to_bpp(output->dev->format),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) nlanes, phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * is empty before we start a receiving a new line on the DPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if ((u64)phy_cfg->hs_clk_rate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mode_to_dpi_hfp(mode, mode_valid_check) * nlanes <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) (u64)dsi_hss_hsa_hse_hbp *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int cdns_dsi_bridge_attach(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) enum drm_bridge_attach_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct cdns_dsi *dsi = input_to_dsi(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(dsi->base.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "cdns-dsi driver is only compatible with DRM devices supporting atomic updates");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return drm_bridge_attach(bridge->encoder, output->bridge, bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) const struct drm_display_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct cdns_dsi *dsi = input_to_dsi(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct cdns_dsi_cfg dsi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int bpp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * least 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (mode->vtotal - mode->vsync_end < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return MODE_V_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* VSA_DSI = VSA_DPI and must be at least 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (mode->vsync_end - mode->vsync_start < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return MODE_V_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* HACT must be 32-bits aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if ((mode->hdisplay * bpp) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return MODE_H_ILLEGAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return MODE_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return MODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct cdns_dsi *dsi = input_to_dsi(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val = readl(dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) val &= ~(IF_VID_SELECT_MASK | IF_VID_MODE | VID_EN | HOST_EOT_GEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) DISP_EOT_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(val, dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(val, dsi->regs + MCTL_MAIN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pm_runtime_put(dsi->base.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Power all internal DPHY blocks down and maintain their reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * asserted before changing the DPHY config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DPHY_CMN_PDN | DPHY_PLL_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dsi->regs + MCTL_DPHY_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) phy_init(dsi->dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) phy_configure(dsi->dphy, &output->phy_opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) phy_power_on(dsi->dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Activate the PLL and wait until it's locked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dsi->regs + MCTL_DPHY_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) status & PLL_LOCKED, 100, 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* De-assert data and clock reset lines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dsi->regs + MCTL_DPHY_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void cdns_dsi_init_link(struct cdns_dsi *dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned long sysclk_period, ulpout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (dsi->link_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for (i = 1; i < output->dev->lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val |= DATA_LANE_EN(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val |= CLK_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(val, dsi->regs + MCTL_MAIN_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* ULPOUT should be set to 1ms and is expressed in sysclk cycles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sysclk_period = NSEC_PER_SEC / clk_get_rate(dsi->dsi_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ulpout = DIV_ROUND_UP(NSEC_PER_MSEC, sysclk_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dsi->regs + MCTL_ULPOUT_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) val = CLK_LANE_EN | PLL_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) for (i = 0; i < output->dev->lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val |= DATA_LANE_START(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(val, dsi->regs + MCTL_MAIN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dsi->link_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct cdns_dsi *dsi = input_to_dsi(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct drm_display_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned long tx_byte_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct cdns_dsi_cfg dsi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 tmp, reg_wakeup, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mode = &bridge->encoder->crtc->state->adjusted_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) nlanes = output->dev->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) cdns_dsi_hs_init(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cdns_dsi_init_link(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dsi->regs + VID_HSIZE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dsi->regs + VID_HSIZE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dsi->regs + VID_VSIZE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel(mode->crtc_vdisplay, dsi->regs + VID_VSIZE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tmp = dsi_cfg.htotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) (dsi_cfg.hsa + DSI_BLANKING_FRAME_OVERHEAD +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DSI_HSA_FRAME_OVERHEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(BLK_LINE_PULSE_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dsi->regs + VID_VCA_SETTING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) tmp = dsi_cfg.htotal -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (DSI_HSS_VSS_VSE_FRAME_OVERHEAD + DSI_BLANKING_FRAME_OVERHEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) writel(BLK_LINE_EVENT_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!(output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dsi->regs + VID_VCA_SETTING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tmp = DIV_ROUND_UP(dsi_cfg.htotal, nlanes) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) DIV_ROUND_UP(dsi_cfg.hsa, nlanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!(output->dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tmp -= DIV_ROUND_UP(DSI_EOT_PKT_SIZE, nlanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) phy_cfg->hs_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dsi->regs + VID_DPHY_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * both should be set to at least the time it takes to transmit a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) tmp = NSEC_PER_SEC / drm_mode_vrefresh(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) tmp /= tx_byte_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) for (div = 0; div <= CLK_DIV_MAX; div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (tmp <= HSTX_TIMEOUT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) tmp >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (tmp > HSTX_TIMEOUT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tmp = HSTX_TIMEOUT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dsi->regs + MCTL_DPHY_TIMEOUT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) writel(LPRX_TIMEOUT(tmp), dsi->regs + MCTL_DPHY_TIMEOUT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) switch (output->dev->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case MIPI_DSI_FMT_RGB888:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) tmp = VID_PIXEL_MODE_RGB888 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case MIPI_DSI_FMT_RGB666:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tmp = VID_PIXEL_MODE_RGB666 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case MIPI_DSI_FMT_RGB666_PACKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tmp = VID_PIXEL_MODE_RGB666_PACKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case MIPI_DSI_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) tmp = VID_PIXEL_MODE_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(dsi->base.dev, "Unsupported DSI format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) tmp |= REG_BLKLINE_MODE(REG_BLK_MODE_BLANKING_PKT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) VID_IGNORE_MISS_VSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) writel(tmp, dsi->regs + VID_MAIN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) tmp = readl(dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tmp &= ~(IF_VID_SELECT_MASK | HOST_EOT_GEN | IF_VID_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!(output->dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) tmp |= HOST_EOT_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) tmp |= IF_VID_MODE | IF_VID_SELECT(input->id) | VID_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) writel(tmp, dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tmp = readl(dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) writel(tmp, dsi->regs + MCTL_MAIN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .attach = cdns_dsi_bridge_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .mode_valid = cdns_dsi_bridge_mode_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .disable = cdns_dsi_bridge_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .enable = cdns_dsi_bridge_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int cdns_dsi_attach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct mipi_dsi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct cdns_dsi *dsi = to_cdns_dsi(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct cdns_dsi_input *input = &dsi->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct drm_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct drm_panel *panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * We currently do not support connecting several DSI devices to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * same host. In order to support that we'd need the DRM bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * framework to allow dynamic reconfiguration of the bridge chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (output->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* We do not support burst mode yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * The host <-> device link might be described using an OF-graph
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * representation, in this case we extract the device of_node from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * this representation, otherwise we use dsidev->dev.of_node which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * should have been filled by the core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) np = of_graph_get_remote_node(dsi->base.dev->of_node, DSI_OUTPUT_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) np = of_node_get(dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) panel = of_drm_find_panel(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!IS_ERR(panel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) bridge = drm_panel_bridge_add_typed(panel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DRM_MODE_CONNECTOR_DSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bridge = of_drm_find_bridge(dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) bridge = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (IS_ERR(bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = PTR_ERR(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_err(host->dev, "failed to add DSI device %s (err = %d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) output->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) output->bridge = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) output->panel = panel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * The DSI output has been properly configured, we can now safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * register the input to the bridge framework so that it can take place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * in a display pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) drm_bridge_add(&input->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int cdns_dsi_detach(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct mipi_dsi_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct cdns_dsi *dsi = to_cdns_dsi(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct cdns_dsi_output *output = &dsi->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct cdns_dsi_input *input = &dsi->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) drm_bridge_remove(&input->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (output->panel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) drm_panel_bridge_remove(output->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static irqreturn_t cdns_dsi_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct cdns_dsi *dsi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 flag, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) flag = readl(dsi->regs + DIRECT_CMD_STS_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ctl = readl(dsi->regs + DIRECT_CMD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ctl &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) writel(ctl, dsi->regs + DIRECT_CMD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) complete(&dsi->direct_cmd_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) const struct mipi_dsi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct cdns_dsi *dsi = to_cdns_dsi(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct mipi_dsi_packet packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret, i, tx_len, rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = pm_runtime_resume_and_get(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) cdns_dsi_init_link(dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = mipi_dsi_create_packet(&packet, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) tx_len = msg->tx_buf ? msg->tx_len : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) rx_len = msg->rx_buf ? msg->rx_len : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* For read operations, the maximum TX len is 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (rx_len && tx_len > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* TX len is limited by the CMD FIFO depth. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (tx_len > dsi->direct_cmd_fifo_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* RX len is limited by the RX FIFO depth. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (rx_len > dsi->rx_fifo_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cmd = CMD_SIZE(tx_len) | CMD_VCHAN_ID(msg->channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) CMD_DATATYPE(msg->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (msg->flags & MIPI_DSI_MSG_USE_LPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) cmd |= CMD_LP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (mipi_dsi_packet_format_is_long(msg->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) cmd |= CMD_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (rx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) cmd |= READ_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) wait = READ_COMPLETED_WITH_ERR | READ_COMPLETED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ctl = READ_EN | BTA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) } else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) cmd |= BTA_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) wait = ACK_WITH_ERR_RCVD | ACK_RCVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ctl = BTA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) | ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) writel(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) for (i = 0; i < tx_len; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) const u8 *buf = msg->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) for (j = 0; j < 4 && j + i < tx_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) val |= (u32)buf[i + j] << (8 * j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) writel(val, dsi->regs + DIRECT_CMD_WRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Clear status flags before sending the command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) writel(wait, dsi->regs + DIRECT_CMD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) reinit_completion(&dsi->direct_cmd_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(0, dsi->regs + DIRECT_CMD_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) wait_for_completion_timeout(&dsi->direct_cmd_comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) sts = readl(dsi->regs + DIRECT_CMD_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* We did not receive the events we were waiting for. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!(sts & wait)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* 'READ' or 'WRITE with ACK' failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) for (i = 0; i < rx_len; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u8 *buf = msg->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) val = readl(dsi->regs + DIRECT_CMD_RDDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) for (j = 0; j < 4 && j + i < rx_len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) buf[i + j] = val >> (8 * j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pm_runtime_put(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct mipi_dsi_host_ops cdns_dsi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .attach = cdns_dsi_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .detach = cdns_dsi_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .transfer = cdns_dsi_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int __maybe_unused cdns_dsi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct cdns_dsi *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) reset_control_deassert(dsi->dsi_p_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) clk_prepare_enable(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) clk_prepare_enable(dsi->dsi_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int __maybe_unused cdns_dsi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct cdns_dsi *dsi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) clk_disable_unprepare(dsi->dsi_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) clk_disable_unprepare(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) reset_control_assert(dsi->dsi_p_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dsi->link_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int cdns_dsi_drm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct cdns_dsi *dsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct cdns_dsi_input *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (!dsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) platform_set_drvdata(pdev, dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) input = &dsi->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dsi->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(dsi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return PTR_ERR(dsi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dsi->dsi_p_clk = devm_clk_get(&pdev->dev, "dsi_p_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (IS_ERR(dsi->dsi_p_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return PTR_ERR(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dsi->dsi_p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "dsi_p_rst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (IS_ERR(dsi->dsi_p_rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return PTR_ERR(dsi->dsi_p_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dsi->dsi_sys_clk = devm_clk_get(&pdev->dev, "dsi_sys_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (IS_ERR(dsi->dsi_sys_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return PTR_ERR(dsi->dsi_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dsi->dphy = devm_phy_get(&pdev->dev, "dphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (IS_ERR(dsi->dphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return PTR_ERR(dsi->dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = clk_prepare_enable(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) val = readl(dsi->regs + ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (REV_VENDOR_ID(val) != 0xcad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_err(&pdev->dev, "invalid vendor id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) val = readl(dsi->regs + IP_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) init_completion(&dsi->direct_cmd_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) writel(0, dsi->regs + MCTL_MAIN_DATA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) writel(0, dsi->regs + MCTL_MAIN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) writel(0, dsi->regs + MCTL_MAIN_PHY_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * We only support the DPI input, so force input->id to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * CDNS_DPI_INPUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) input->id = CDNS_DPI_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) input->bridge.funcs = &cdns_dsi_bridge_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) input->bridge.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Mask all interrupts before registering the IRQ handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) writel(0, dsi->regs + MCTL_MAIN_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) writel(0, dsi->regs + MCTL_DPHY_ERR_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) writel(0, dsi->regs + CMD_MODE_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) writel(0, dsi->regs + DIRECT_CMD_RD_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) writel(0, dsi->regs + VID_MODE_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) writel(0, dsi->regs + TVG_STS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) writel(0, dsi->regs + DPI_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = devm_request_irq(&pdev->dev, irq, cdns_dsi_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_name(&pdev->dev), dsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dsi->base.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dsi->base.ops = &cdns_dsi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = mipi_dsi_host_register(&dsi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) goto err_disable_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) clk_disable_unprepare(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) err_disable_runtime_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) err_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) clk_disable_unprepare(dsi->dsi_p_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int cdns_dsi_drm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct cdns_dsi *dsi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mipi_dsi_host_unregister(&dsi->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct of_device_id cdns_dsi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { .compatible = "cdns,dsi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static struct platform_driver cdns_dsi_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .probe = cdns_dsi_drm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .remove = cdns_dsi_drm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .name = "cdns-dsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .of_match_table = cdns_dsi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .pm = &cdns_dsi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) module_platform_driver(cdns_dsi_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) MODULE_DESCRIPTION("Cadence DSI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) MODULE_ALIAS("platform:cdns-dsi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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