^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx Zynq GPIO device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRIVER_NAME "zynq-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Maximum banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZYNQ_GPIO_MAX_BANK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZYNQMP_GPIO_MAX_BANK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VERSAL_GPIO_MAX_BANK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PMC_GPIO_MAX_BANK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VERSAL_UNUSED_BANKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZYNQ_GPIO_BANK0_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZYNQ_GPIO_BANK1_NGPIO 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ZYNQ_GPIO_BANK2_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZYNQ_GPIO_BANK3_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZYNQMP_GPIO_BANK0_NGPIO 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZYNQMP_GPIO_BANK1_NGPIO 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZYNQMP_GPIO_BANK2_NGPIO 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZYNQMP_GPIO_BANK3_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZYNQMP_GPIO_BANK4_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZYNQMP_GPIO_BANK5_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZYNQ_GPIO_NR_GPIOS 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZYNQMP_GPIO_NR_GPIOS 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Register offsets for the GPIO device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* LSW Mask & Data -WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* MSW Mask & Data -WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Data Register-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Direction mode reg-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Output enable reg-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Interrupt mask reg-RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Interrupt enable reg-WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Interrupt disable reg-WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Interrupt status reg-RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Interrupt type reg-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Interrupt polarity reg-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Interrupt on any, reg-RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Disable all interrupts mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Mid pin number of a bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ZYNQ_GPIO_MID_PIN_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* GPIO upper 16 bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPIO_QUIRK_DATA_RO_BUG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPIO_QUIRK_VERSAL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 dirm[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 outen[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 int_en[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 int_type[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 int_any[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct zynq_gpio - gpio device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @base_addr: base address of the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @clk: clock resource for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @irq: interrupt for the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @p_data: pointer to platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @context: context registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @dirlock: lock used for direction in/out synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct zynq_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct zynq_platform_data *p_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct gpio_regs context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) spinlock_t dirlock; /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * struct zynq_platform_data - zynq gpio platform data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @label: string to store in gpio->label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @quirks: Flags is used to identify the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @ngpio: max number of gpio pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @max_bank: maximum number of gpio banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @bank_min: this array represents bank's min pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @bank_max: this array represents bank's max pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct zynq_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int max_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int bank_min[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int bank_max[ZYNQMP_GPIO_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct irq_chip zynq_gpio_level_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct irq_chip zynq_gpio_edge_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @gpio: Pointer to driver data struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Return: 0 if zynqmp, 1 if zynq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * gpio_data_ro_bug - test if HW bug exists or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @gpio: Pointer to driver data struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Return: 0 if bug doesnot exist, 1 if bug exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int gpio_data_ro_bug(struct zynq_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * for a given pin in the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @pin_num: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @bank_num: an output parameter used to return the bank number of the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @bank_pin_num: an output parameter used to return pin number within a bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * for the given gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @gpio: gpio device data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Returns the bank number and pin offset within the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int *bank_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int *bank_pin_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct zynq_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if ((pin_num >= gpio->p_data->bank_min[bank]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (pin_num <= gpio->p_data->bank_max[bank])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *bank_num = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *bank_pin_num = pin_num -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) gpio->p_data->bank_min[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bank = bank + VERSAL_UNUSED_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) WARN(true, "invalid GPIO pin number: %u", pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *bank_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *bank_pin_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @chip: gpio_chip instance to be worked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @pin: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * This function reads the state of the specified pin of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Return: 0 if the pin is low, 1 if pin is high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct zynq_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (gpio_data_ro_bug(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (zynq_gpio_is_zynq(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (bank_num <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) data = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) data = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ZYNQ_GPIO_DATA_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (bank_num <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) data = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) data = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ZYNQ_GPIO_DATA_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) data = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return (data >> bank_pin_num) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * zynq_gpio_set_value - Modify the state of the pin with specified value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @chip: gpio_chip instance to be worked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @pin: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @state: value used to modify the state of the specified pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * This function calculates the register offset (i.e to lower 16 bits or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * upper 16 bits) based on the given pin number and sets the state of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * gpio pin to the specified value. The state is either 0 or non-zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int reg_offset, bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct zynq_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* only 16 data bits in bit maskable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * get the 32 bit value to be written to the mask/data register where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * the upper 16 bits is the mask and lower 16 bits is the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) state = !!state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel_relaxed(state, gpio->base_addr + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @chip: gpio_chip instance to be worked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @pin: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * This function uses the read-modify-write sequence to set the direction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * the gpio pin as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct zynq_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * On zynq bank 0 pins 7 and 8 are special and cannot be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * as inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (bank_pin_num == 7 || bank_pin_num == 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* clear the bit in direction mode reg to set the pin as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_lock_irqsave(&gpio->dirlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) reg &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spin_unlock_irqrestore(&gpio->dirlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @chip: gpio_chip instance to be worked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @pin: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @state: value to be written to specified pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * This function sets the direction of specified GPIO pin as output, configures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * the Output Enable register for the pin and uses zynq_gpio_set to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * the state of the pin to the value specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct zynq_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* set the GPIO pin as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_lock_irqsave(&gpio->dirlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* configure the output enable reg for the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_unlock_irqrestore(&gpio->dirlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* set the state of the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) zynq_gpio_set_value(chip, pin, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @chip: gpio_chip instance to be worked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @pin: gpio pin number within the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * This function returns the direction of the specified GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct zynq_gpio *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (reg & BIT(bank_pin_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @irq_data: per irq and chip data passed down to chip functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * This function calculates gpio pin number from irq number and sets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * bit in the Interrupt Disable register of the corresponding bank to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * interrupts for that pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void zynq_gpio_irq_mask(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int device_pin_num, bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) device_pin_num = irq_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel_relaxed(BIT(bank_pin_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @irq_data: irq data containing irq number of gpio pin for the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * This function calculates the gpio pin number from irq number and sets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * bit in the Interrupt Enable register of the corresponding bank to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * interrupts for that pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int device_pin_num, bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) device_pin_num = irq_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel_relaxed(BIT(bank_pin_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @irq_data: irq data containing irq number of gpio pin for the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * to ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * This function calculates gpio pin number from irq number and sets the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void zynq_gpio_irq_ack(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int device_pin_num, bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) device_pin_num = irq_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writel_relaxed(BIT(bank_pin_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * @irq_data: irq data containing irq number of gpio pin for the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Clears the INTSTS bit and unmasks the given interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void zynq_gpio_irq_enable(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * The Zynq GPIO controller does not disable interrupt detection when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * the interrupt is masked and only disables the propagation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * interrupt. This means when the controller detects an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * condition while the interrupt is logically disabled it will propagate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * that interrupt event once the interrupt is enabled. This will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * the interrupt consumer to see spurious interrupts to prevent this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * first make sure that the interrupt is not asserted and then enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) zynq_gpio_irq_ack(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) zynq_gpio_irq_unmask(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @irq_data: irq data containing irq number of gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @type: interrupt type that is to be set for the gpio pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * This function gets the gpio pin number and its bank from the gpio pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Return: 0, negative error otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 int_type, int_pol, int_any;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int device_pin_num, bank_num, bank_pin_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) device_pin_num = irq_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int_type = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int_pol = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int_any = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ZYNQ_GPIO_INTANY_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * based on the type requested, configure the INT_TYPE, INT_POLARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * and INT_ANY registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int_type |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int_pol |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int_any &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int_type |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int_pol &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int_any &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int_type |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int_any |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int_type &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int_pol |= BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int_type &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int_pol &= ~BIT(bank_pin_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel_relaxed(int_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) writel_relaxed(int_pol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writel_relaxed(int_any,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) irq_set_chip_handler_name_locked(irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &zynq_gpio_level_irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) handle_fasteoi_irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) irq_set_chip_handler_name_locked(irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &zynq_gpio_edge_irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) handle_level_irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) irq_set_irq_wake(gpio->irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int zynq_gpio_irq_reqres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = pm_runtime_resume_and_get(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return gpiochip_reqres_irq(chip, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void zynq_gpio_irq_relres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) gpiochip_relres_irq(chip, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pm_runtime_put(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* irq chip descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct irq_chip zynq_gpio_level_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .irq_enable = zynq_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .irq_eoi = zynq_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .irq_mask = zynq_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .irq_unmask = zynq_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .irq_set_type = zynq_gpio_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .irq_set_wake = zynq_gpio_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .irq_request_resources = zynq_gpio_irq_reqres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .irq_release_resources = zynq_gpio_irq_relres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct irq_chip zynq_gpio_edge_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .irq_enable = zynq_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .irq_ack = zynq_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .irq_mask = zynq_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .irq_unmask = zynq_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .irq_set_type = zynq_gpio_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .irq_set_wake = zynq_gpio_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .irq_request_resources = zynq_gpio_irq_reqres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .irq_release_resources = zynq_gpio_irq_relres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int bank_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned long pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct irq_domain *irqdomain = gpio->chip.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for_each_set_bit(offset, &pending, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) generic_handle_irq(gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @desc: irq descriptor instance of the 'irq'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * This function reads the Interrupt Status Register of each bank to get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * gpio pin number which has triggered an interrupt. It then acks the triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * interrupt and calls the pin specific handler set by the higher layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * application for that pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * Note: A bug is reported if no handler is set for the gpio pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void zynq_gpio_irqhandler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 int_sts, int_enb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct zynq_gpio *gpio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gpiochip_get_data(irq_desc_get_handler_data(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int_sts = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int_enb = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) bank_num = bank_num + VERSAL_UNUSED_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void zynq_gpio_save_context(struct zynq_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) gpio->context.datalsw[bank_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) gpio->context.datamsw[bank_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) gpio->context.int_type[bank_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) gpio->context.int_polarity[bank_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) gpio->context.int_any[bank_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) readl_relaxed(gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ZYNQ_GPIO_INTANY_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) bank_num = bank_num + VERSAL_UNUSED_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel_relaxed(gpio->context.datalsw[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel_relaxed(gpio->context.datamsw[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) writel_relaxed(gpio->context.dirm[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ZYNQ_GPIO_DIRM_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel_relaxed(gpio->context.int_type[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writel_relaxed(gpio->context.int_polarity[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writel_relaxed(gpio->context.int_any[bank_num],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ZYNQ_GPIO_INTANY_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) writel_relaxed(~(gpio->context.int_en[bank_num]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ZYNQ_GPIO_INTEN_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) bank_num = bank_num + VERSAL_UNUSED_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int __maybe_unused zynq_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct zynq_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct irq_data *data = irq_get_irq_data(gpio->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(dev, "irq_get_irq_data() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (!device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) disable_irq(gpio->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!irqd_is_wakeup_set(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) zynq_gpio_save_context(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int __maybe_unused zynq_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct zynq_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct irq_data *data = irq_get_irq_data(gpio->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(dev, "irq_get_irq_data() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) enable_irq(gpio->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!irqd_is_wakeup_set(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) zynq_gpio_restore_context(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct zynq_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) clk_disable_unprepare(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct zynq_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return clk_prepare_enable(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = pm_runtime_get_sync(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * If the device is already active pm_runtime_get() will return 1 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * success, but gpio_request still needs to return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pm_runtime_put(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) zynq_gpio_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct zynq_platform_data versal_gpio_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .label = "versal_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .quirks = GPIO_QUIRK_VERSAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .ngpio = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .max_bank = VERSAL_GPIO_MAX_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .bank_min[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .bank_min[3] = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct zynq_platform_data pmc_gpio_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .label = "pmc_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .ngpio = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .max_bank = PMC_GPIO_MAX_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .bank_min[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .bank_min[1] = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .bank_min[3] = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .bank_min[4] = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const struct zynq_platform_data zynqmp_gpio_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .label = "zynqmp_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .quirks = GPIO_QUIRK_DATA_RO_BUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .ngpio = ZYNQMP_GPIO_NR_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .max_bank = ZYNQMP_GPIO_MAX_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct zynq_platform_data zynq_gpio_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .label = "zynq_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ngpio = ZYNQ_GPIO_NR_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .max_bank = ZYNQ_GPIO_MAX_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static const struct of_device_id zynq_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * zynq_gpio_probe - Initialization method for a zynq_gpio device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * @pdev: platform device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * This function allocates memory resources for the gpio device and registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * all the banks of the device. It will also set up interrupts for the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * Note: Interrupts are disabled for all the banks during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * Return: 0 on success, negative error otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int zynq_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int ret, bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct zynq_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(&pdev->dev, "of_match_node() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) gpio->p_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (IS_ERR(gpio->base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return PTR_ERR(gpio->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) gpio->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (gpio->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* configure the gpio chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) chip = &gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) chip->label = gpio->p_data->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) chip->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) chip->get = zynq_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) chip->set = zynq_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) chip->request = zynq_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) chip->free = zynq_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) chip->direction_input = zynq_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) chip->direction_output = zynq_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) chip->get_direction = zynq_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) chip->ngpio = gpio->p_data->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Retrieve GPIO clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) gpio->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (IS_ERR(gpio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = clk_prepare_enable(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&pdev->dev, "Unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_lock_init(&gpio->dirlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = pm_runtime_resume_and_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) goto err_pm_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* disable interrupts for all banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bank_num = bank_num + VERSAL_UNUSED_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Set up the GPIO irqchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) girq->chip = &zynq_gpio_edge_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) girq->parent_handler = zynq_gpio_irqhandler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) girq->parents[0] = gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* report a bug if gpio chip registration fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = gpiochip_add_data(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_err(&pdev->dev, "Failed to add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) err_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) err_pm_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) clk_disable_unprepare(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * zynq_gpio_remove - Driver removal function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * @pdev: platform device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int zynq_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct zynq_gpio *gpio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) gpiochip_remove(&gpio->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) clk_disable_unprepare(gpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) device_set_wakeup_capable(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static struct platform_driver zynq_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .pm = &zynq_gpio_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .of_match_table = zynq_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .probe = zynq_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .remove = zynq_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * zynq_gpio_init - Initial driver registration call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * Return: value from platform_driver_register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int __init zynq_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return platform_driver_register(&zynq_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) postcore_initcall(zynq_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static void __exit zynq_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) platform_driver_unregister(&zynq_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) module_exit(zynq_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) MODULE_AUTHOR("Xilinx Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) MODULE_DESCRIPTION("Zynq GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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