Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ZTE ZX296702 GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Jun Nie <jun.nie@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ZX_GPIO_DIR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ZX_GPIO_IVE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ZX_GPIO_IV	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ZX_GPIO_IEP	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ZX_GPIO_IEN	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ZX_GPIO_DI	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ZX_GPIO_DO1	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ZX_GPIO_DO0	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ZX_GPIO_DO	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ZX_GPIO_IM	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ZX_GPIO_IE	0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ZX_GPIO_MIS	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ZX_GPIO_IC	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ZX_GPIO_NR	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct zx_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	raw_spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct gpio_chip	gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u16 gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (offset >= gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	gpiodir &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u16 gpiodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (offset >= gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	gpiodir |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int zx_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int zx_irq_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u16 bit = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (offset < 0 || offset >= ZX_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		gpiois |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (trigger & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			gpioiev |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			gpioiev &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		gpiois &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		gpioi_epos |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		gpioi_eneg |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (trigger & IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			gpioi_epos |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			gpioi_eneg &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			gpioi_eneg |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			gpioi_epos &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void zx_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		for_each_set_bit(offset, &pending, ZX_GPIO_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			generic_handle_irq(irq_find_mapping(gc->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 							    offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void zx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u16 gpioie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	raw_spin_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	raw_spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void zx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct zx_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u16 gpioie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	raw_spin_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	raw_spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct irq_chip zx_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.name		= "zx-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.irq_mask	= zx_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.irq_unmask	= zx_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.irq_set_type	= zx_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int zx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct zx_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int irq, id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (IS_ERR(chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	id = of_alias_get_id(dev->of_node, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	raw_spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	chip->gc.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	chip->gc.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	chip->gc.direction_input = zx_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	chip->gc.direction_output = zx_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	chip->gc.get = zx_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	chip->gc.set = zx_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	chip->gc.base = ZX_GPIO_NR * id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	chip->gc.ngpio = ZX_GPIO_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	chip->gc.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	chip->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	chip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * irq_chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writew_relaxed(0, chip->base + ZX_GPIO_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	girq = &chip->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	girq->chip = &zx_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	girq->parent_handler = zx_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				     sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ret = gpiochip_add_data(&chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dev_info(dev, "ZX GPIO chip registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct of_device_id zx_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.compatible = "zte,zx296702-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct platform_driver zx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.probe		= zx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.name	= "zx_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.of_match_table = of_match_ptr(zx_gpio_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) builtin_platform_driver(zx_gpio_driver)