^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 TangoTec Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Baruch Siach <baruch@tkos.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Driver for the Xtensa LX4 GPIO32 Option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Documentation: Xtensa LX4 Microprocessor Data Book, Section 2.22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * GPIO32 is a standard optional extension to the Xtensa architecture core that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * provides preconfigured output and input ports for intra SoC signaling. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * output state called EXPSTATE, and 32bit input wire called IMPWIRE. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * driver treats input and output states as two distinct devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Access to GPIO32 specific instructions is controlled by the CPENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * (Coprocessor Enable Bits) register. By default Xtensa Linux startup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * disables access to all coprocessors. This driver sets the CPENABLE bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * corresponding to GPIO32 before any GPIO32 specific instruction, and restores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * CPENABLE state after that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * This driver is currently incompatible with SMP. The GPIO32 extension is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * guaranteed to be available in all cores. Moreover, each core controls a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * different set of IO wires. A theoretical SMP aware version of this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * would need to have a per core workqueue to do the actual GPIO manipulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/coprocessor.h> /* CPENABLE read/write macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifndef XCHAL_CP_ID_XTIOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #error GPIO32 option is not enabled for your xtensa core variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #if XCHAL_HAVE_CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline unsigned long enable_cp(unsigned long *cpenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *cpenable = xtensa_get_sr(cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void disable_cp(unsigned long flags, unsigned long cpenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) xtensa_set_sr(cpenable, cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline unsigned long enable_cp(unsigned long *cpenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *cpenable = 0; /* avoid uninitialized value warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void disable_cp(unsigned long flags, unsigned long cpenable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* XCHAL_HAVE_CP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return GPIO_LINE_DIRECTION_IN; /* input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags, saved_cpenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 impwire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) flags = enable_cp(&saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __asm__ __volatile__("read_impwire %0" : "=a" (impwire));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) disable_cp(flags, saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return !!(impwire & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void xtensa_impwire_set_value(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BUG(); /* output only; should never be called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return GPIO_LINE_DIRECTION_OUT; /* output only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long flags, saved_cpenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 expstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) flags = enable_cp(&saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __asm__ __volatile__("rur.expstate %0" : "=a" (expstate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) disable_cp(flags, saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return !!(expstate & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void xtensa_expstate_set_value(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long flags, saved_cpenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 val = value ? BIT(offset) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) flags = enable_cp(&saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __asm__ __volatile__("wrmsk_expstate %0, %1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) :: "a" (val), "a" (mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) disable_cp(flags, saved_cpenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct gpio_chip impwire_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .label = "impwire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ngpio = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .get_direction = xtensa_impwire_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .get = xtensa_impwire_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .set = xtensa_impwire_set_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct gpio_chip expstate_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .label = "expstate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .ngpio = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .get_direction = xtensa_expstate_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .get = xtensa_expstate_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .set = xtensa_expstate_set_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int xtensa_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = gpiochip_add_data(&impwire_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return gpiochip_add_data(&expstate_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct platform_driver xtensa_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "xtensa-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .probe = xtensa_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int __init xtensa_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pdev = platform_device_register_simple("xtensa-gpio", 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return platform_driver_register(&xtensa_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) device_initcall(xtensa_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DESCRIPTION("Xtensa LX4 GPIO32 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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