^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for EXAR XRA1403 16-bit GPIO expander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017, General Electric Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* XRA1403 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XRA_GSR 0x00 /* GPIO State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XRA_OCR 0x02 /* Output Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XRA_PIR 0x04 /* Input Polarity Inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XRA_GCR 0x06 /* GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XRA_PUR 0x08 /* Input Internal Pull-up Resistor Enable/Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XRA_IER 0x0A /* Input Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XRA_TSCR 0x0C /* Output Three-State Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XRA_ISR 0x0E /* Input Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XRA_REIR 0x10 /* Input Rising Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XRA_FEIR 0x12 /* Input Falling Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XRA_IFR 0x14 /* Input Filter Enable/Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XRA_LAST 0x15 /* Bounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct xra1403 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct regmap_config xra1403_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .reg_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pad_bits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .max_register = XRA_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned int to_reg(unsigned int reg, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return reg + (offset > 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int xra1403_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) BIT(offset % 8), BIT(offset % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int xra1403_direction_output(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BIT(offset % 8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) BIT(offset % 8), value ? BIT(offset % 8) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int xra1403_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = regmap_read(xra->regmap, to_reg(XRA_GCR, offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (val & BIT(offset % 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int xra1403_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = regmap_read(xra->regmap, to_reg(XRA_GSR, offset), &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return !!(val & BIT(offset % 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void xra1403_set(struct gpio_chip *chip, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = regmap_update_bits(xra->regmap, to_reg(XRA_OCR, offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) BIT(offset % 8), value ? BIT(offset % 8) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(chip->parent, "Failed to set pin: %d, ret: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void xra1403_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct xra1403 *xra = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int value[XRA_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int gcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int gsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) seq_puts(s, "xra reg:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (reg = 0; reg <= XRA_LAST; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) seq_printf(s, " %2.2x", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) seq_puts(s, "\n value:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) for (reg = 0; reg < XRA_LAST; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_read(xra->regmap, reg, &value[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) seq_printf(s, " %2.2x", value[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gcr = value[XRA_GCR + 1] << 8 | value[XRA_GCR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gsr = value[XRA_GSR + 1] << 8 | value[XRA_GSR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for_each_requested_gpio(chip, i, label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) seq_printf(s, " gpio-%-3d (%-12s) %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) chip->base + i, label,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (gcr & BIT(i)) ? "in" : "out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (gsr & BIT(i)) ? "hi" : "lo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define xra1403_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int xra1403_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct xra1403 *xra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) xra = devm_kzalloc(&spi->dev, sizeof(*xra), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!xra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* bring the chip out of reset if reset pin is provided*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_warn(&spi->dev, "Could not get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) xra->chip.direction_input = xra1403_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) xra->chip.direction_output = xra1403_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) xra->chip.get_direction = xra1403_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xra->chip.get = xra1403_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) xra->chip.set = xra1403_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) xra->chip.dbg_show = xra1403_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) xra->chip.ngpio = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) xra->chip.label = "xra1403";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xra->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xra->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xra->chip.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) xra->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) xra->regmap = devm_regmap_init_spi(spi, &xra1403_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(xra->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = PTR_ERR(xra->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(&spi->dev, "Failed to allocate regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = devm_gpiochip_add_data(&spi->dev, &xra->chip, xra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(&spi->dev, "Unable to register gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spi_set_drvdata(spi, xra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct spi_device_id xra1403_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { "xra1403" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_DEVICE_TABLE(spi, xra1403_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct of_device_id xra1403_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .compatible = "exar,xra1403" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DEVICE_TABLE(of, xra1403_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct spi_driver xra1403_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .probe = xra1403_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .id_table = xra1403_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "xra1403",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .of_match_table = of_match_ptr(xra1403_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) module_spi_driver(xra1403_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_AUTHOR("Nandor Han <nandor.han@ge.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_AUTHOR("Semi Malinen <semi.malinen@ge.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("GPIO expander driver for EXAR XRA1403");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags