Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2003-2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * XLP GPIO has multiple 32 bit registers for each feature where each register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * require 3 32-bit registers for each feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Here we only define offset of the first register for each feature. Offset of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * the registers for pins greater than 32 can be calculated as following(Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * GPIO_INT_STAT as example):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * offset = (gpio / XLP_GPIO_REGSZ) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * reg_addr = addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * where addr is base address of the that feature register and gpio is the pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GPIO_OUTPUT_EN		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GPIO_PADDRV		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GPIO_INT_EN00		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPIO_INT_EN10		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GPIO_INT_EN20		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GPIO_INT_EN30		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPIO_INT_POL		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GPIO_INT_TYPE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GPIO_INT_STAT		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GPIO_9XX_BYTESWAP	0X00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GPIO_9XX_CTRL		0X04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GPIO_9XX_OUTPUT_EN	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define GPIO_9XX_PADDRV		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * Only for 4 interrupt enable reg are defined for now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * total reg available are 12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define GPIO_9XX_INT_EN00	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GPIO_9XX_INT_EN10	0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GPIO_9XX_INT_EN20	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define GPIO_9XX_INT_EN30	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GPIO_9XX_INT_POL	0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define GPIO_9XX_INT_TYPE	0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GPIO_9XX_INT_STAT	0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GPIO_3XX_INT_EN00	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define GPIO_3XX_INT_EN10	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define GPIO_3XX_INT_EN20	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define GPIO_3XX_INT_EN30	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define GPIO_3XX_INT_POL	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define GPIO_3XX_INT_TYPE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define GPIO_3XX_INT_STAT	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Interrupt type register mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define XLP_GPIO_IRQ_TYPE_LVL	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define XLP_GPIO_IRQ_TYPE_EDGE	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Interrupt polarity register mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define XLP_GPIO_IRQ_POL_HIGH	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define XLP_GPIO_IRQ_POL_LOW	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define XLP_GPIO_REGSZ		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define XLP_GPIO_IRQ_BASE	768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define XLP_MAX_NR_GPIO		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* XLP variants supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	XLP_GPIO_VARIANT_XLP832 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	XLP_GPIO_VARIANT_XLP316,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	XLP_GPIO_VARIANT_XLP208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	XLP_GPIO_VARIANT_XLP980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	XLP_GPIO_VARIANT_XLP532,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	GPIO_VARIANT_VULCAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct xlp_gpio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	void __iomem *gpio_intr_en;	/* pointer to first intr enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	void __iomem *gpio_intr_stat;	/* pointer to first intr status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void __iomem *gpio_intr_type;	/* pointer to first intr type reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	void __iomem *gpio_intr_pol;	/* pointer to first intr polarity reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	void __iomem *gpio_out_en;	/* pointer to first output enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	void __iomem *gpio_paddrv;	/* pointer to first pad drive reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 pos, regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	pos = gpio % XLP_GPIO_REGSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	regset = (gpio / XLP_GPIO_REGSZ) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return !!(readl(addr + regset) & BIT(pos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 value, pos, regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	pos = gpio % XLP_GPIO_REGSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regset = (gpio / XLP_GPIO_REGSZ) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	value = readl(addr + regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		value |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		value &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	writel(value, addr + regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void xlp_gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void xlp_gpio_irq_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void xlp_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__set_bit(d->hwirq, priv->gpio_enabled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int pol, irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		pol = XLP_GPIO_IRQ_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		pol = XLP_GPIO_IRQ_POL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		pol = XLP_GPIO_IRQ_POL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		pol = XLP_GPIO_IRQ_POL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct irq_chip xlp_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.name		= "XLP-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.irq_mask_ack	= xlp_gpio_irq_mask_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.irq_disable	= xlp_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.irq_set_type	= xlp_gpio_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.irq_unmask	= xlp_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.flags		= IRQCHIP_ONESHOT_SAFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void xlp_gpio_generic_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int gpio, regoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 gpio_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	regoff = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	gpio_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (regoff != gpio / XLP_GPIO_REGSZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			regoff = gpio / XLP_GPIO_REGSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			generic_handle_irq(irq_find_mapping(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 						priv->chip.irq.domain, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	BUG_ON(gpio >= gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	BUG_ON(gpio >= gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	BUG_ON(gpio >= gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	BUG_ON(gpio >= gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id xlp_gpio_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.compatible = "netlogic,xlp832-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.data	    = (void *)XLP_GPIO_VARIANT_XLP832,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.compatible = "netlogic,xlp316-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.data	    = (void *)XLP_GPIO_VARIANT_XLP316,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.compatible = "netlogic,xlp208-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.data	    = (void *)XLP_GPIO_VARIANT_XLP208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.compatible = "netlogic,xlp980-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.data	    = (void *)XLP_GPIO_VARIANT_XLP980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.compatible = "netlogic,xlp532-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.data	    = (void *)XLP_GPIO_VARIANT_XLP532,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.compatible = "brcm,vulcan-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.data	    = (void *)GPIO_VARIANT_VULCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int xlp_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct xlp_gpio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int irq_base, irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u32 soc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	priv = devm_kzalloc(&pdev->dev,	sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	gpio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (IS_ERR(gpio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return PTR_ERR(gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 						&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (!acpi_id || !acpi_id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			dev_err(&pdev->dev, "Unable to match ACPI ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		soc_type = (uintptr_t) acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	switch (soc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	case XLP_GPIO_VARIANT_XLP832:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		ngpio = 41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	case XLP_GPIO_VARIANT_XLP208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	case XLP_GPIO_VARIANT_XLP316:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	case XLP_GPIO_VARIANT_XLP980:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	case XLP_GPIO_VARIANT_XLP532:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	case GPIO_VARIANT_VULCAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		if (soc_type == XLP_GPIO_VARIANT_XLP980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			ngpio = 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		else if (soc_type == XLP_GPIO_VARIANT_XLP532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			ngpio = 67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			ngpio = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		dev_err(&pdev->dev, "Unknown Processor type!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	gc = &priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	gc->label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	gc->base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	gc->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	gc->ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	gc->of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	gc->direction_output = xlp_gpio_dir_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	gc->direction_input = xlp_gpio_dir_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	gc->set = xlp_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	gc->get = xlp_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (soc_type != GPIO_VARIANT_VULCAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 						XLP_GPIO_IRQ_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 						gc->ngpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	girq->chip = &xlp_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	girq->parent_handler = xlp_gpio_generic_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				     sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	girq->first = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	err = gpiochip_add_data(gc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct acpi_device_id xlp_gpio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{ "BRCM9006", GPIO_VARIANT_VULCAN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{ "CAV9006",  GPIO_VARIANT_VULCAN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static struct platform_driver xlp_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.name	= "xlp-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.of_match_table = xlp_gpio_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.probe		= xlp_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_platform_driver(xlp_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_LICENSE("GPL v2");