Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Xilinx gpio driver for xps/axi_gpio IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2008 - 2013 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Register Offset Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define XGPIO_DATA_OFFSET   (0x0)	/* Data register  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define XGPIO_TRI_OFFSET    (0x4)	/* I/O direction register  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define XGPIO_CHANNEL_OFFSET	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Read/Write access to the GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) # define xgpio_readreg(offset)		readl(offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) # define xgpio_writereg(offset, val)	writel(val, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) # define xgpio_readreg(offset)		__raw_readl(offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) # define xgpio_writereg(offset, val)	__raw_writel(val, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * struct xgpio_instance - Stores information about GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @gc: GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @regs: register block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @gpio_width: GPIO width for every channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @gpio_state: GPIO state shadow register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @gpio_dir: GPIO direction shadow register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @gpio_lock: Lock used for synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct xgpio_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int gpio_width[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 gpio_state[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 gpio_dir[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	spinlock_t gpio_lock[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (gpio >= chip->gpio_width[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (xgpio_index(chip, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return XGPIO_CHANNEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (xgpio_index(chip, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return gpio - chip->gpio_width[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * xgpio_get - Read the specified signal of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @gc:     Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * @gpio:   GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * This function reads the specified signal of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * 0 if direction of GPIO signals is set as input otherwise it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * returns negative error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct xgpio_instance *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			    xgpio_regoffset(chip, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return !!(val & BIT(xgpio_offset(chip, gpio)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * xgpio_set - Write the specified signal of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @gc:     Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @gpio:   GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @val:    Value to be written to specified signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * This function writes the specified value in to the specified signal of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct xgpio_instance *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int index =  xgpio_index(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int offset =  xgpio_offset(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	spin_lock_irqsave(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Write to GPIO signal and set its direction to output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		chip->gpio_state[index] |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		chip->gpio_state[index] &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		       xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * xgpio_set_multiple - Write the specified signals of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * @gc:     Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * @mask:   Mask of the GPIOS to modify.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * @bits:   Value to be wrote on each GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * This function writes the specified values into the specified signals of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * GPIO devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			       unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct xgpio_instance *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int index = xgpio_index(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int offset, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spin_lock_irqsave(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* Write to GPIO signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (*mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/* Once finished with an index write it out to the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		if (index !=  xgpio_index(chip, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				       index * XGPIO_CHANNEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				       chip->gpio_state[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			index =  xgpio_index(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			spin_lock_irqsave(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		if (__test_and_clear_bit(i, mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			offset =  xgpio_offset(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			if (test_bit(i, bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				chip->gpio_state[index] |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				chip->gpio_state[index] &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		       index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * @gc:     Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * @gpio:   GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * 0 - if direction of GPIO signals is set as input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * otherwise it returns negative error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct xgpio_instance *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int index =  xgpio_index(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int offset =  xgpio_offset(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	spin_lock_irqsave(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Set the GPIO bit in shadow register and set direction as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	chip->gpio_dir[index] |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		       xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * @gc:     Pointer to gpio_chip device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * @gpio:   GPIO signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * @val:    Value to be written to specified signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * This function sets the direction of specified GPIO signal as output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * If all GPIO signals of GPIO chip is configured as input then it returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * error otherwise it returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct xgpio_instance *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int index =  xgpio_index(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int offset =  xgpio_offset(chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	spin_lock_irqsave(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Write state of GPIO signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		chip->gpio_state[index] |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		chip->gpio_state[index] &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* Clear the GPIO bit in shadow register and set direction as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	chip->gpio_dir[index] &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * xgpio_save_regs - Set initial values of GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * @chip: Pointer to GPIO instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void xgpio_save_regs(struct xgpio_instance *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET,	chip->gpio_state[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!chip->gpio_width[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		       chip->gpio_state[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		       chip->gpio_dir[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * xgpio_of_probe - Probe method for the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * @pdev: pointer to the platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * It returns 0, if the driver is bound to the GPIO device, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * a negative value if there is an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int xgpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct xgpio_instance *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u32 is_dual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* Update GPIO state shadow register with default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* Update GPIO direction shadow register with default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		chip->gpio_dir[0] = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * Check device node and parent device node for device width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * and assume default width of 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		chip->gpio_width[0] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	spin_lock_init(&chip->gpio_lock[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		is_dual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (is_dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		/* Update GPIO state shadow register with default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		of_property_read_u32(np, "xlnx,dout-default-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 				     &chip->gpio_state[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		/* Update GPIO direction shadow register with default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		if (of_property_read_u32(np, "xlnx,tri-default-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					 &chip->gpio_dir[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			chip->gpio_dir[1] = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		 * Check device node and parent device node for device width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		 * and assume default width of 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (of_property_read_u32(np, "xlnx,gpio2-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 					 &chip->gpio_width[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			chip->gpio_width[1] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		spin_lock_init(&chip->gpio_lock[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	chip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	chip->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	chip->gc.direction_input = xgpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	chip->gc.direction_output = xgpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	chip->gc.get = xgpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	chip->gc.set = xgpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	chip->gc.set_multiple = xgpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	chip->gc.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	chip->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(chip->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(&pdev->dev, "failed to ioremap memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return PTR_ERR(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	xgpio_save_regs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(&pdev->dev, "failed to add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct of_device_id xgpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ .compatible = "xlnx,xps-gpio-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ /* end of list */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DEVICE_TABLE(of, xgpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct platform_driver xgpio_plat_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.probe		= xgpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			.name = "gpio-xilinx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			.of_match_table	= xgpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int __init xgpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return platform_driver_register(&xgpio_plat_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) subsys_initcall(xgpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void __exit xgpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	platform_driver_unregister(&xgpio_plat_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) module_exit(xgpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_DESCRIPTION("Xilinx GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_LICENSE("GPL");