Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IPROC_CCA_INT_F_GPIOINT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IPROC_CCA_INT_STS		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IPROC_CCA_INT_MASK		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IPROC_GPIO_CCA_DIN		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IPROC_GPIO_CCA_DOUT		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IPROC_GPIO_CCA_OUT_EN		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IPROC_GPIO_CCA_INT_LEVEL	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IPROC_GPIO_CCA_INT_LEVEL_MASK	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IPROC_GPIO_CCA_INT_EVENT	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IPROC_GPIO_CCA_INT_EVENT_MASK	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IPROC_GPIO_CCA_INT_EDGE		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct iproc_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	void __iomem *intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static inline struct iproc_gpio_chip *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) to_iproc_gpio(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return container_of(gc, struct iproc_gpio_chip, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void iproc_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 irq_type, event_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	irq_type = irq_get_trigger_type(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (irq_type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		event_status |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		writel_relaxed(event_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			       chip->base + IPROC_GPIO_CCA_INT_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void iproc_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 int_mask, irq_type, event_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	irq_type = irq_get_trigger_type(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (irq_type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		event_mask |= 1 << pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		writel_relaxed(event_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			       chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		int_mask |= 1 << pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		writel_relaxed(int_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			       chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void iproc_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 irq_type, int_mask, event_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	irq_type = irq_get_trigger_type(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (irq_type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		event_mask &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		writel_relaxed(event_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			       chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		int_mask &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		writel_relaxed(int_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			       chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int pin = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 event_pol, int_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		event_pol &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		event_pol |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		int_pol &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		int_pol |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/* should not come here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	else if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static irqreturn_t iproc_gpio_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct gpio_chip *gc = (struct gpio_chip *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct iproc_gpio_chip *chip = to_iproc_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned long int_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* go through the entire GPIOs and handle all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (int_status & IPROC_CCA_INT_F_GPIOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		u32 event, level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/* Get level and edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		event =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		    readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		level &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		    readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		int_bits = level | event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		for_each_set_bit(bit, &int_bits, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return int_bits ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int iproc_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct iproc_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ret = bgpio_init(&chip->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			 chip->base + IPROC_GPIO_CCA_DIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			 chip->base + IPROC_GPIO_CCA_DOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			 chip->base + IPROC_GPIO_CCA_OUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dev_err(dev, "unable to init GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	chip->gc.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!of_property_read_u32(dn, "ngpios", &num_gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		chip->gc.ngpio = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		struct irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		irqc = &chip->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		irqc->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		irqc->irq_ack = iproc_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		irqc->irq_mask = iproc_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		irqc->irq_unmask = iproc_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		irqc->irq_set_type = iproc_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		chip->intr = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (IS_ERR(chip->intr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return PTR_ERR(chip->intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		/* Enable GPIO interrupts for CCA GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		val |= IPROC_CCA_INT_F_GPIOINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		 * Directly request the irq here instead of passing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 * a flow-handler because the irq is shared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				       IRQF_SHARED, chip->gc.label, &chip->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		girq = &chip->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		girq->chip = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = devm_gpiochip_add_data(dev, &chip->gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(dev, "unable to add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int iproc_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct iproc_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (chip->intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		val &= ~IPROC_CCA_INT_F_GPIOINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct of_device_id bcm_iproc_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ .compatible = "brcm,iproc-gpio-cca" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver bcm_iproc_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.name = "iproc-xgs-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.of_match_table = bcm_iproc_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.probe = iproc_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.remove = iproc_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) module_platform_driver(bcm_iproc_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_DESCRIPTION("XGS IPROC GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_LICENSE("GPL v2");