^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AppliedMicro X-Gene SoC GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Feng Kan <fkan@apm.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GPIO_SET_DR_OFFSET 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GPIO_DATA_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GPIO_BANK_STRIDE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XGENE_GPIOS_PER_BANK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XGENE_MAX_GPIO_BANKS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct xgene_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bit_offset = GPIO_BIT_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 setval, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) setval = ioread32(chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) setval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) setval &= ~BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) iowrite32(setval, chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __xgene_gpio_set(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long bank_offset, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bit_offset = GPIO_BIT_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long flags, bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 dirval, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bit_offset = GPIO_BIT_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dirval = ioread32(chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dirval |= BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) iowrite32(dirval, chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int xgene_gpio_dir_out(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct xgene_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long flags, bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 dirval, bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bit_offset = GPIO_BIT_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dirval = ioread32(chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dirval &= ~BIT(bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iowrite32(dirval, chip->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __xgene_gpio_set(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static __maybe_unused int xgene_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct xgene_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static __maybe_unused int xgene_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct xgene_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long bank_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int xgene_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct xgene_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (IS_ERR(gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PTR_ERR(gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gpio->chip.ngpio = XGENE_MAX_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spin_lock_init(&gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gpio->chip.get_direction = xgene_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) gpio->chip.direction_input = xgene_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) gpio->chip.direction_output = xgene_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) gpio->chip.get = xgene_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gpio->chip.set = xgene_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) gpio->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "failed to register gpiochip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct of_device_id xgene_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .compatible = "apm,xgene-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct acpi_device_id xgene_gpio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { "APMC0D14", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct platform_driver xgene_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "xgene-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .of_match_table = xgene_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pm = &xgene_gpio_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .probe = xgene_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) builtin_platform_driver(xgene_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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