^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO interface for Winbond Super I/O chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Currently, only W83627UHG (Nuvoton NCT6627UD) is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WB_GPIO_DRIVER_NAME KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WB_SIO_BASE 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WB_SIO_BASE_HIGH 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WB_SIO_EXT_ENTER_KEY 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WB_SIO_EXT_EXIT_KEY 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* global chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WB_SIO_REG_LOGICAL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WB_SIO_REG_CHIP_MSB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WB_SIO_REG_CHIP_LSB 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WB_SIO_CHIP_ID_W83627UHG 0xa230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WB_SIO_CHIP_ID_W83627UHG_MASK GENMASK(15, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WB_SIO_REG_DPD 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WB_SIO_REG_DPD_UARTA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WB_SIO_REG_DPD_UARTB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WB_SIO_REG_IDPD 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WB_SIO_REG_IDPD_UARTC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WB_SIO_REG_IDPD_UARTD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WB_SIO_REG_IDPD_UARTE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WB_SIO_REG_IDPD_UARTF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WB_SIO_REG_GLOBAL_OPT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WB_SIO_REG_GO_ENFDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WB_SIO_REG_OVTGPIO3456 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WB_SIO_REG_OG3456_G3PP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WB_SIO_REG_OG3456_G4PP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WB_SIO_REG_OG3456_G5PP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WB_SIO_REG_OG3456_G6PP 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WB_SIO_REG_I2C_PS 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WB_SIO_REG_I2CPS_I2CFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WB_SIO_REG_GPIO1_MF 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WB_SIO_REG_G1MF_G1PP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WB_SIO_REG_G1MF_G2PP 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WB_SIO_REG_G1MF_FS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WB_SIO_REG_G1MF_FS_IR_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WB_SIO_REG_G1MF_FS_IR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WB_SIO_REG_G1MF_FS_GPIO1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WB_SIO_REG_G1MF_FS_UARTB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* not an actual device number, just a value meaning 'no device' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WB_SIO_DEV_NONE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* registers with offsets >= 0x30 are specific for a particular device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* UART B logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WB_SIO_DEV_UARTB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WB_SIO_UARTB_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WB_SIO_UARTB_ENABLE_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* UART C logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WB_SIO_DEV_UARTC 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WB_SIO_UARTC_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WB_SIO_UARTC_ENABLE_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* GPIO3, GPIO4 logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WB_SIO_DEV_GPIO34 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WB_SIO_GPIO34_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WB_SIO_GPIO34_ENABLE_3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WB_SIO_GPIO34_ENABLE_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WB_SIO_GPIO34_REG_IO3 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WB_SIO_GPIO34_REG_DATA3 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WB_SIO_GPIO34_REG_INV3 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WB_SIO_GPIO34_REG_IO4 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WB_SIO_GPIO34_REG_DATA4 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WB_SIO_GPIO34_REG_INV4 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* WDTO, PLED, GPIO5, GPIO6 logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define WB_SIO_DEV_WDGPIO56 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define WB_SIO_WDGPIO56_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WB_SIO_WDGPIO56_ENABLE_5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WB_SIO_WDGPIO56_ENABLE_6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WB_SIO_WDGPIO56_REG_IO5 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WB_SIO_WDGPIO56_REG_DATA5 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WB_SIO_WDGPIO56_REG_INV5 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WB_SIO_WDGPIO56_REG_IO6 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WB_SIO_WDGPIO56_REG_DATA6 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WB_SIO_WDGPIO56_REG_INV6 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* GPIO1, GPIO2, SUSLED logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WB_SIO_DEV_GPIO12 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WB_SIO_GPIO12_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WB_SIO_GPIO12_ENABLE_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WB_SIO_GPIO12_ENABLE_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WB_SIO_GPIO12_REG_IO1 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WB_SIO_GPIO12_REG_DATA1 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WB_SIO_GPIO12_REG_INV1 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WB_SIO_GPIO12_REG_IO2 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WB_SIO_GPIO12_REG_DATA2 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WB_SIO_GPIO12_REG_INV2 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* UART D logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WB_SIO_DEV_UARTD 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WB_SIO_UARTD_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WB_SIO_UARTD_ENABLE_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* UART E logical device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WB_SIO_DEV_UARTE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WB_SIO_UARTE_REG_ENABLE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WB_SIO_UARTE_ENABLE_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * for a description what a particular field of this struct means please see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * a description of the relevant module parameter at the bottom of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct winbond_gpio_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long ppgpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long odgpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool pledgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool beepgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool i2cgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct winbond_gpio_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int winbond_sio_enter(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * datasheet says two successive writes of the "key" value are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * in order for chip to enter the "Extended Function Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(WB_SIO_EXT_ENTER_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) outb(WB_SIO_EXT_ENTER_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void winbond_sio_select_logical(unsigned long base, u8 dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) outb(WB_SIO_REG_LOGICAL, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outb(dev, base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void winbond_sio_leave(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) outb(WB_SIO_EXT_EXIT_KEY, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) release_region(base, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) outb(reg, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) outb(data, base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static u8 winbond_sio_reg_read(unsigned long base, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) outb(reg, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val = winbond_sio_reg_read(base, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) winbond_sio_reg_write(base, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = winbond_sio_reg_read(base, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) winbond_sio_reg_write(base, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return winbond_sio_reg_read(base, reg) & BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * struct winbond_gpio_port_conflict - possibly conflicting device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @name: device name (NULL means no conflicting device defined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @dev: Super I/O logical device number where the testreg register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * is located (or WB_SIO_DEV_NONE - don't select any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * logical device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @testreg: register number where the testbit bit is located
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @testbit: index of a bit to check whether an actual conflict exists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @warnonly: if set then a conflict isn't fatal (just warn about it),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * otherwise disable the particular GPIO port if a conflict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * is detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct winbond_gpio_port_conflict {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 testreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 testbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool warnonly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * struct winbond_gpio_info - information about a particular GPIO port (device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @dev: Super I/O logical device number of the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * specified below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @enablereg: port enable bit register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @enablebit: index of a port enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @outputreg: output driver mode bit register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @outputppbit: index of a push-pull output driver mode bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @ioreg: data direction register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @invreg: pin data inversion register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @datareg: pin data register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @conflict: description of a device that possibly conflicts with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct winbond_gpio_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 enablereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 enablebit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 outputreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 outputppbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 ioreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 invreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 datareg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct winbond_gpio_port_conflict conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct winbond_gpio_info winbond_gpio_infos[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .dev = WB_SIO_DEV_GPIO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .enablereg = WB_SIO_GPIO12_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .enablebit = WB_SIO_GPIO12_ENABLE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .outputreg = WB_SIO_REG_GPIO1_MF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .outputppbit = WB_SIO_REG_G1MF_G1PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .ioreg = WB_SIO_GPIO12_REG_IO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .invreg = WB_SIO_GPIO12_REG_INV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .datareg = WB_SIO_GPIO12_REG_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .conflict = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "UARTB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .dev = WB_SIO_DEV_UARTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .testreg = WB_SIO_UARTB_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .testbit = WB_SIO_UARTB_ENABLE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .warnonly = true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .dev = WB_SIO_DEV_GPIO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .enablereg = WB_SIO_GPIO12_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .enablebit = WB_SIO_GPIO12_ENABLE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .outputreg = WB_SIO_REG_GPIO1_MF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .outputppbit = WB_SIO_REG_G1MF_G2PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .ioreg = WB_SIO_GPIO12_REG_IO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .invreg = WB_SIO_GPIO12_REG_INV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .datareg = WB_SIO_GPIO12_REG_DATA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* special conflict handling so doesn't use conflict data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .dev = WB_SIO_DEV_GPIO34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .enablereg = WB_SIO_GPIO34_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .enablebit = WB_SIO_GPIO34_ENABLE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .outputreg = WB_SIO_REG_OVTGPIO3456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .outputppbit = WB_SIO_REG_OG3456_G3PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .ioreg = WB_SIO_GPIO34_REG_IO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .invreg = WB_SIO_GPIO34_REG_INV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .datareg = WB_SIO_GPIO34_REG_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .conflict = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "UARTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .dev = WB_SIO_DEV_UARTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .testreg = WB_SIO_UARTC_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .testbit = WB_SIO_UARTC_ENABLE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .warnonly = true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .dev = WB_SIO_DEV_GPIO34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .enablereg = WB_SIO_GPIO34_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .enablebit = WB_SIO_GPIO34_ENABLE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .outputreg = WB_SIO_REG_OVTGPIO3456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .outputppbit = WB_SIO_REG_OG3456_G4PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .ioreg = WB_SIO_GPIO34_REG_IO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .invreg = WB_SIO_GPIO34_REG_INV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .datareg = WB_SIO_GPIO34_REG_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .conflict = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "UARTD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .dev = WB_SIO_DEV_UARTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .testreg = WB_SIO_UARTD_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .testbit = WB_SIO_UARTD_ENABLE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .warnonly = true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .dev = WB_SIO_DEV_WDGPIO56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .enablebit = WB_SIO_WDGPIO56_ENABLE_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .outputreg = WB_SIO_REG_OVTGPIO3456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .outputppbit = WB_SIO_REG_OG3456_G5PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .ioreg = WB_SIO_WDGPIO56_REG_IO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .invreg = WB_SIO_WDGPIO56_REG_INV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .datareg = WB_SIO_WDGPIO56_REG_DATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .conflict = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "UARTE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .dev = WB_SIO_DEV_UARTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .testreg = WB_SIO_UARTE_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .testbit = WB_SIO_UARTE_ENABLE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .warnonly = true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .dev = WB_SIO_DEV_WDGPIO56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .enablereg = WB_SIO_WDGPIO56_REG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .enablebit = WB_SIO_WDGPIO56_ENABLE_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .outputreg = WB_SIO_REG_OVTGPIO3456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .outputppbit = WB_SIO_REG_OG3456_G6PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .ioreg = WB_SIO_WDGPIO56_REG_IO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .invreg = WB_SIO_WDGPIO56_REG_INV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .datareg = WB_SIO_WDGPIO56_REG_DATA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .conflict = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "FDC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .dev = WB_SIO_DEV_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .testreg = WB_SIO_REG_GLOBAL_OPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .testbit = WB_SIO_REG_GO_ENFDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .warnonly = false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* returns whether changing a pin is allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static bool winbond_gpio_get_info(unsigned int *gpio_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct winbond_gpio_info **info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bool allow_changing = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (*gpio_num < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *gpio_num -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *info = &winbond_gpio_infos[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * GPIO2 (the second port) shares some pins with a basic PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * functionality, which is very likely controlled by the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Don't allow changing these pins by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (i == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (*gpio_num == 0 && !params.pledgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) allow_changing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else if (*gpio_num == 1 && !params.beepgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) allow_changing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else if ((*gpio_num == 5 || *gpio_num == 6) && !params.i2cgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) allow_changing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return allow_changing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int winbond_gpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long *base = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const struct winbond_gpio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) bool val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) winbond_gpio_get_info(&offset, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val = winbond_sio_enter(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) winbond_sio_select_logical(*base, info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val = winbond_sio_reg_btest(*base, info->datareg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (winbond_sio_reg_btest(*base, info->invreg, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) winbond_sio_leave(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int winbond_gpio_direction_in(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long *base = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const struct winbond_gpio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!winbond_gpio_get_info(&offset, &info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = winbond_sio_enter(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) winbond_sio_select_logical(*base, info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) winbond_sio_reg_bset(*base, info->ioreg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) winbond_sio_leave(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int winbond_gpio_direction_out(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long *base = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) const struct winbond_gpio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!winbond_gpio_get_info(&offset, &info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = winbond_sio_enter(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) winbond_sio_select_logical(*base, info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) winbond_sio_reg_bclear(*base, info->ioreg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (winbond_sio_reg_btest(*base, info->invreg, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val = !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) winbond_sio_reg_bset(*base, info->datareg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) winbond_sio_reg_bclear(*base, info->datareg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) winbond_sio_leave(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void winbond_gpio_set(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long *base = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct winbond_gpio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!winbond_gpio_get_info(&offset, &info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (winbond_sio_enter(*base) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) winbond_sio_select_logical(*base, info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (winbond_sio_reg_btest(*base, info->invreg, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val = !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) winbond_sio_reg_bset(*base, info->datareg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) winbond_sio_reg_bclear(*base, info->datareg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) winbond_sio_leave(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct gpio_chip winbond_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .label = WB_GPIO_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .get = winbond_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .direction_input = winbond_gpio_direction_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .set = winbond_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .direction_output = winbond_gpio_direction_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void winbond_gpio_configure_port0_pins(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((val & WB_SIO_REG_G1MF_FS_MASK) == WB_SIO_REG_G1MF_FS_GPIO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pr_warn("GPIO1 pins were connected to something else (%.2x), fixing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val &= ~WB_SIO_REG_G1MF_FS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) val |= WB_SIO_REG_G1MF_FS_GPIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void winbond_gpio_configure_port1_check_i2c(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) WB_SIO_REG_I2CPS_I2CFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!params.i2cgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pr_warn("disabling GPIO2.5 and GPIO2.6 as I2C is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const struct winbond_gpio_info *info = &winbond_gpio_infos[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const struct winbond_gpio_port_conflict *conflict = &info->conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* is there a possible conflicting device defined? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (conflict->name != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (conflict->dev != WB_SIO_DEV_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) winbond_sio_select_logical(base, conflict->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (winbond_sio_reg_btest(base, conflict->testreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) conflict->testbit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (conflict->warnonly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pr_warn("enabled GPIO%u share pins with active %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) idx + 1, conflict->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pr_warn("disabling GPIO%u as %s is enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) idx + 1, conflict->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* GPIO1 and GPIO2 need some (additional) special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) winbond_gpio_configure_port0_pins(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else if (idx == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) winbond_gpio_configure_port1_check_i2c(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) winbond_sio_select_logical(base, info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) winbond_sio_reg_bset(base, info->enablereg, info->enablebit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (params.ppgpios & BIT(idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) winbond_sio_reg_bset(base, info->outputreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) info->outputppbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else if (params.odgpios & BIT(idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) winbond_sio_reg_bclear(base, info->outputreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) info->outputppbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pr_notice("GPIO%u pins are %s\n", idx + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) winbond_sio_reg_btest(base, info->outputreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) info->outputppbit) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "push-pull" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "open drain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int winbond_gpio_configure(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) for_each_set_bit(i, ¶ms.gpios, BITS_PER_LONG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!winbond_gpio_configure_port(base, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __clear_bit(i, ¶ms.gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!params.gpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pr_err("please use 'gpios' module parameter to select some active GPIO ports to enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int winbond_gpio_check_chip(unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = winbond_sio_enter(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pr_notice("chip ID at %lx is %.4x\n", base, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if ((chip & WB_SIO_CHIP_ID_W83627UHG_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) WB_SIO_CHIP_ID_W83627UHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pr_err("not an our chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) winbond_sio_leave(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int winbond_gpio_imatch(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long gpios_rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) gpios_rem = params.gpios & ~GENMASK(ARRAY_SIZE(winbond_gpio_infos) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (gpios_rem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pr_warn("unknown ports (%lx) enabled in GPIO ports bitmask\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) gpios_rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) params.gpios &= ~gpios_rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (params.ppgpios & params.odgpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pr_err("some GPIO ports are set both to push-pull and open drain mode at the same time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (params.base != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return winbond_gpio_check_chip(params.base) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * if the 'base' module parameter is unset probe two chip default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * I/O port bases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) params.base = WB_SIO_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = winbond_gpio_check_chip(params.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ret != -ENODEV && ret != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) params.base = WB_SIO_BASE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return winbond_gpio_check_chip(params.base) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int winbond_gpio_iprobe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (params.base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = winbond_sio_enter(params.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = winbond_gpio_configure(params.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) winbond_sio_leave(params.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Add 8 gpios for every GPIO port that was enabled in gpios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * module parameter (that wasn't disabled earlier in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * winbond_gpio_configure() & co. due to, for example, a pin conflict).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) winbond_gpio_chip.ngpio = hweight_long(params.gpios) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * GPIO6 port has only 5 pins, so if it is enabled we have to adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * the total count appropriately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (params.gpios & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) winbond_gpio_chip.ngpio -= (8 - 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) winbond_gpio_chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct isa_driver winbond_gpio_idriver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .name = WB_GPIO_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .match = winbond_gpio_imatch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .probe = winbond_gpio_iprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) module_isa_driver(winbond_gpio_idriver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) module_param_named(base, params.base, ulong, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MODULE_PARM_DESC(base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "I/O port base (when unset - probe chip default ones)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* This parameter sets which GPIO devices (ports) we enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) module_param_named(gpios, params.gpios, ulong, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MODULE_PARM_DESC(gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "bitmask of GPIO ports to enable (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * These two parameters below set how we configure GPIO ports output drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * It can't be a one bitmask since we need three values per port: push-pull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * open-drain and keep as-is (this is the default).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) module_param_named(ppgpios, params.ppgpios, ulong, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MODULE_PARM_DESC(ppgpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "bitmask of GPIO ports to set to push-pull mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) module_param_named(odgpios, params.odgpios, ulong, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MODULE_PARM_DESC(odgpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "bitmask of GPIO ports to set to open drain mode (bit 0 - GPIO1, bit 1 - GPIO2, etc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * GPIO2.0 and GPIO2.1 control a basic PC functionality that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * don't allow tinkering with by default (it is very likely that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * firmware owns these pins).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * These two parameters below allow overriding these prohibitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) module_param_named(pledgpio, params.pledgpio, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MODULE_PARM_DESC(pledgpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "enable changing value of GPIO2.0 bit (Power LED), default no.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) module_param_named(beepgpio, params.beepgpio, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MODULE_PARM_DESC(beepgpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "enable changing value of GPIO2.1 bit (BEEP), default no.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MODULE_AUTHOR("Maciej S. Szmigiero <mail@maciej.szmigiero.name>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MODULE_DESCRIPTION("GPIO interface for Winbond Super I/O chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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