^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Whiskey Cove PMIC GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver is written based on gpio-crystalcove.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2016 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/intel_soc_pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Bank 0: Pin 0 - 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Bank 1: Pin 7 - 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Bank 2: Pin 11 - 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Each pin has one output control register and one input control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BANK0_NR_PINS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BANK1_NR_PINS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BANK2_NR_PINS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WCOVE_VGPIO_NUM 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPIO_OUT_CTRL_BASE 0x4e44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_IN_CTRL_BASE 0x4e51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * GPIO interrupts are organized in two groups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Group 0: Bank 0 pins (Pin 0 - 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Each group has two registers (one bit per pin): status and mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GROUP0_NR_IRQS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GROUP1_NR_IRQS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_MASK_BASE 0x4e19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IRQ_STATUS_BASE 0x4e0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_IRQ0_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_IRQ1_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UPDATE_IRQ_TYPE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UPDATE_IRQ_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CTLI_INTCNT_DIS (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTLI_INTCNT_NE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CTLI_INTCNT_PE (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CTLI_INTCNT_BE (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CTLO_DIR_IN (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CTLO_DIR_OUT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CTLO_DRV_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CTLO_DRV_OD (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTLO_DRV_CMOS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CTLO_DRV_REN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CTLO_RVAL_2KDOWN (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CTLO_RVAL_2KUP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CTLO_RVAL_50KDOWN (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CTLO_RVAL_50KUP (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum ctrl_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CTRL_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CTRL_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * struct wcove_gpio - Whiskey Cove GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @buslock: for bus lock/sync and unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @chip: the abstract gpio_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @dev: the gpio device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @regmap: the regmap from the parent device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @regmap_irq_chip: the regmap of the gpio irq chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @update: pending IRQ setting update, to be written to the chip upon unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @intcnt: the Interrupt Detect value to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct wcove_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mutex buslock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct regmap_irq_chip_data *regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int intcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool set_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline int to_reg(int gpio, enum ctrl_register reg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (gpio >= WCOVE_GPIO_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (reg_type == CTRL_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg = GPIO_IN_CTRL_BASE + gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg = GPIO_OUT_CTRL_BASE + gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (gpio < GROUP0_NR_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg = IRQ_MASK_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mask = BIT(gpio % GROUP0_NR_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = IRQ_MASK_BASE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (wg->set_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_update_bits(wg->regmap, reg, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_update_bits(wg->regmap, reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int reg = to_reg(gpio, CTRL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret, reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_read(wg->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (val & CTLO_DIR_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret, reg = to_reg(gpio, CTRL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = regmap_read(wg->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return val & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_update_bits(wg->regmap, reg, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) regmap_update_bits(wg->regmap, reg, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CTLO_DRV_OD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CTLO_DRV_CMOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int wcove_irq_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (data->hwirq >= WCOVE_GPIO_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) wg->intcnt = CTLI_INTCNT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) wg->intcnt = CTLI_INTCNT_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wg->intcnt = CTLI_INTCNT_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) wg->intcnt = CTLI_INTCNT_NE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wg->update |= UPDATE_IRQ_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void wcove_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mutex_lock(&wg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void wcove_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int gpio = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (wg->update & UPDATE_IRQ_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wcove_update_irq_ctrl(wg, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (wg->update & UPDATE_IRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) wcove_update_irq_mask(wg, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) wg->update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mutex_unlock(&wg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void wcove_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (data->hwirq >= WCOVE_GPIO_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) wg->set_irq_mask = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wg->update |= UPDATE_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void wcove_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (data->hwirq >= WCOVE_GPIO_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) wg->set_irq_mask = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) wg->update |= UPDATE_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct irq_chip wcove_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "Whiskey Cove",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .irq_mask = wcove_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .irq_unmask = wcove_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .irq_set_type = wcove_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .irq_bus_lock = wcove_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .irq_bus_sync_unlock = wcove_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct wcove_gpio *wg = (struct wcove_gpio *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int pending, virq, gpio, mask, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 p[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(wg->dev, "Failed to read irq status register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Iterate until no interrupt is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* One iteration is for all pending bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) for_each_set_bit(gpio, (const unsigned long *)&pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WCOVE_GPIO_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) virq = irq_find_mapping(wg->chip.irq.domain, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) handle_nested_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Next iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(wg->dev, "Failed to read irq status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void wcove_gpio_dbg_show(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int ctlo, ctli, irq_mask, irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct wcove_gpio *wg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int gpio, offset, group, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) group = gpio < GROUP0_NR_IRQS ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) &irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) &irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) offset = gpio % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ctli & 0x1 ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ctli & CTLI_INTCNT_NE ? "fall" : " ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctli & CTLI_INTCNT_PE ? "rise" : " ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ctlo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) irq_mask & BIT(offset) ? "mask " : "unmask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) irq_status & BIT(offset) ? "pending" : " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int wcove_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct intel_soc_pmic *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct wcove_gpio *wg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int virq, ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * This gpio platform device is created by a mfd device (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * shared by all sub-devices created by the mfd device, the regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * pointer for instance, is stored as driver data of the mfd device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pmic = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!wg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) wg->regmap_irq_chip = pmic->irq_chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) platform_set_drvdata(pdev, wg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mutex_init(&wg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) wg->chip.label = KBUILD_MODNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) wg->chip.direction_input = wcove_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) wg->chip.direction_output = wcove_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) wg->chip.get_direction = wcove_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) wg->chip.get = wcove_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wg->chip.set = wcove_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) wg->chip.set_config = wcove_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) wg->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) wg->chip.ngpio = WCOVE_VGPIO_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) wg->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) wg->chip.parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) wg->chip.dbg_show = wcove_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) wg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) wg->regmap = pmic->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (virq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(dev, "Failed to get virq by irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) girq = &wg->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) girq->chip = &wcove_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) IRQF_ONESHOT, pdev->name, wg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(dev, "Failed to request irq %d\n", virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "Failed to add gpiochip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Enable GPIO0 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Enable GPIO1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Whiskey Cove PMIC itself is a analog device(but with digital control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * interface) providing power management support for other devices in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct platform_driver wcove_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "bxt_wcove_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .probe = wcove_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) module_platform_driver(wcove_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_ALIAS("platform:bxt_wcove_gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags