^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Linux GPIOlib driver for the VIA VX855 integrated southbridge GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 VIA Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 One Laptop per Child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Harald Welte <HaraldWelte@viatech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MODULE_NAME "vx855_gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* The VX855 south bridge has the following GPIO pins:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * GPI 0...13 General Purpose Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GPO 0...12 General Purpose Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * GPIO 0...14 General Purpose I/O (Open-Drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NR_VX855_GPI 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NR_VX855_GPO 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NR_VX855_GPIO 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NR_VX855_GPInO (NR_VX855_GPI + NR_VX855_GPO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NR_VX855_GP (NR_VX855_GPI + NR_VX855_GPO + NR_VX855_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct vx855_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 io_gpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 io_gpo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* resolve a GPIx into the corresponding bit position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline u_int32_t gpi_i_bit(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (i < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 1 << (i + 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline u_int32_t gpo_o_bit(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (i < 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 1 << (i + 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline u_int32_t gpio_i_bit(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (i < 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 1 << (i + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 1 << (i + 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline u_int32_t gpio_o_bit(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (i < 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 1 << (i + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 1 << (i + 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Mapping between numeric GPIO ID and the actual GPIO hardware numbering:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 0..13 GPI 0..13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 14..26 GPO 0..12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 27..41 GPIO 0..14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int vx855gpio_direction_input(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct vx855_gpio *vg = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u_int32_t reg_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Real GPI bits are always in input direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (nr < NR_VX855_GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Real GPO bits cannot be put in output direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (nr < NR_VX855_GPInO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Open Drain GPIO have to be set to one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_lock_irqsave(&vg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg_out = inl(vg->io_gpo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) outl(reg_out, vg->io_gpo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spin_unlock_irqrestore(&vg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int vx855gpio_get(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct vx855_gpio *vg = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u_int32_t reg_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (nr < NR_VX855_GPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg_in = inl(vg->io_gpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (reg_in & gpi_i_bit(nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else if (nr < NR_VX855_GPInO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* GPO don't have an input bit, we need to read it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * back from the output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg_in = inl(vg->io_gpo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (reg_in & gpo_o_bit(nr - NR_VX855_GPI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg_in = inl(vg->io_gpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (reg_in & gpio_i_bit(nr - NR_VX855_GPInO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void vx855gpio_set(struct gpio_chip *gpio, unsigned int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct vx855_gpio *vg = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u_int32_t reg_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* True GPI cannot be switched to output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (nr < NR_VX855_GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_irqsave(&vg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg_out = inl(vg->io_gpo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (nr < NR_VX855_GPInO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg_out |= gpo_o_bit(nr - NR_VX855_GPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg_out &= ~gpo_o_bit(nr - NR_VX855_GPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg_out |= gpio_o_bit(nr - NR_VX855_GPInO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg_out &= ~gpio_o_bit(nr - NR_VX855_GPInO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outl(reg_out, vg->io_gpo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spin_unlock_irqrestore(&vg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int vx855gpio_direction_output(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* True GPI cannot be switched to output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (nr < NR_VX855_GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* True GPO don't need to be switched to output mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * and GPIO are open-drain, i.e. also need no switching,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * so all we do is set the level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) vx855gpio_set(gpio, nr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int vx855gpio_set_config(struct gpio_chip *gpio, unsigned int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum pin_config_param param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* The GPI cannot be single-ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (nr < NR_VX855_GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* The GPO's are push-pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (nr < NR_VX855_GPInO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (param != PIN_CONFIG_DRIVE_PUSH_PULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* The GPIO's are open drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const char *vx855gpio_names[NR_VX855_GP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "VX855_GPI0", "VX855_GPI1", "VX855_GPI2", "VX855_GPI3", "VX855_GPI4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "VX855_GPI5", "VX855_GPI6", "VX855_GPI7", "VX855_GPI8", "VX855_GPI9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "VX855_GPI10", "VX855_GPI11", "VX855_GPI12", "VX855_GPI13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "VX855_GPO0", "VX855_GPO1", "VX855_GPO2", "VX855_GPO3", "VX855_GPO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "VX855_GPO5", "VX855_GPO6", "VX855_GPO7", "VX855_GPO8", "VX855_GPO9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "VX855_GPO10", "VX855_GPO11", "VX855_GPO12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "VX855_GPIO0", "VX855_GPIO1", "VX855_GPIO2", "VX855_GPIO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "VX855_GPIO4", "VX855_GPIO5", "VX855_GPIO6", "VX855_GPIO7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "VX855_GPIO8", "VX855_GPIO9", "VX855_GPIO10", "VX855_GPIO11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "VX855_GPIO12", "VX855_GPIO13", "VX855_GPIO14"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void vx855gpio_gpio_setup(struct vx855_gpio *vg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct gpio_chip *c = &vg->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) c->label = "VX855 South Bridge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) c->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) c->direction_input = vx855gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) c->direction_output = vx855gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) c->get = vx855gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) c->set = vx855gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) c->set_config = vx855gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) c->dbg_show = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) c->base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) c->ngpio = NR_VX855_GP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) c->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) c->names = vx855gpio_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* This platform device is ordinarily registered by the vx855 mfd driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int vx855gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct resource *res_gpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct resource *res_gpo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct vx855_gpio *vg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) res_gpi = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) res_gpo = platform_get_resource(pdev, IORESOURCE_IO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!res_gpi || !res_gpo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!vg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) platform_set_drvdata(pdev, vg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_info(&pdev->dev, "found VX855 GPIO controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vg->io_gpi = res_gpi->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vg->io_gpo = res_gpo->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spin_lock_init(&vg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * A single byte is used to control various GPIO ports on the VX855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * and in the case of the OLPC XO-1.5, some of those ports are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * for switches that are interpreted and exposed through ACPI. ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * will have reserved the region, so our own reservation will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * succeed. Ignore and continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!devm_request_region(&pdev->dev, res_gpi->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) resource_size(res_gpi), MODULE_NAME "_gpi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "GPI I/O resource busy, probably claimed by ACPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!devm_request_region(&pdev->dev, res_gpo->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) resource_size(res_gpo), MODULE_NAME "_gpo"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "GPO I/O resource busy, probably claimed by ACPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) vx855gpio_gpio_setup(vg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return devm_gpiochip_add_data(&pdev->dev, &vg->gpio, vg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct platform_driver vx855gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .probe = vx855gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(vx855gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_AUTHOR("Harald Welte <HaraldWelte@viatech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_DESCRIPTION("GPIO driver for the VIA VX855 chipset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MODULE_ALIAS("platform:vx855_gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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