^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale vf610 GPIO support through PORT and GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Toradex AG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Stefan Agner <stefan@agner.ch>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VF610_GPIO_PER_PORT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct fsl_gpio_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* SoCs has a Port Data Direction Register (PDDR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bool have_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct vf610_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct irq_chip ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct fsl_gpio_soc_data *sdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 irqc[VF610_GPIO_PER_PORT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *clk_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk *clk_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_PDOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_PSOR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_PCOR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_PTOR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_PDIR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_PDDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PORT_PCR(n) ((n) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PORT_PCR_IRQC_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PORT_ISFR 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PORT_DFER 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PORT_DFCR 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PORT_DFWR 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PORT_INT_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PORT_INT_LOGIC_ZERO 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PORT_INT_RISING_EDGE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PORT_INT_FALLING_EDGE 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PORT_INT_EITHER_EDGE 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PORT_INT_LOGIC_ONE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct fsl_gpio_soc_data imx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .have_paddr = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct of_device_id vf610_gpio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .compatible = "fsl,vf610-gpio", .data = NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel_relaxed(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline u32 vf610_gpio_readl(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct vf610_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long mask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long offset = GPIO_PDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (port->sdata && port->sdata->have_paddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) offset = GPIO_PDOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct vf610_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long mask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) vf610_gpio_writel(mask, port->gpio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct vf610_gpio_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long mask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (port->sdata && port->sdata->have_paddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return pinctrl_gpio_direction_input(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct vf610_gpio_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long mask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (port->sdata && port->sdata->have_paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) vf610_gpio_set(chip, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return pinctrl_gpio_direction_output(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void vf610_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gpiochip_get_data(irq_desc_get_handler_data(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long irq_isfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void vf610_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irqc = PORT_INT_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) irqc = PORT_INT_FALLING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) irqc = PORT_INT_EITHER_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irqc = PORT_INT_LOGIC_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) irqc = PORT_INT_LOGIC_ONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) port->irqc[d->hwirq] = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void vf610_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) vf610_gpio_writel(0, pcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void vf610_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct vf610_gpio_port *port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) disable_irq_wake(port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void vf610_gpio_disable_clk(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int vf610_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct vf610_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct irq_chip *ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) port->sdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) port->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (IS_ERR(port->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return PTR_ERR(port->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(port->gpio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return PTR_ERR(port->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) port->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (port->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) port->clk_port = devm_clk_get(dev, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = PTR_ERR_OR_ZERO(port->clk_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = clk_prepare_enable(port->clk_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) port->clk_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Percolate deferrals, for anything else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * just live without the clocking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) port->clk_gpio = devm_clk_get(dev, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = PTR_ERR_OR_ZERO(port->clk_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = clk_prepare_enable(port->clk_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) port->clk_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gc = &port->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gc->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) gc->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) gc->label = "vf610-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) gc->ngpio = VF610_GPIO_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) gc->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) gc->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) gc->direction_input = vf610_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gc->get = vf610_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) gc->direction_output = vf610_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gc->set = vf610_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ic = &port->ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ic->name = "gpio-vf610";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ic->irq_ack = vf610_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ic->irq_mask = vf610_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ic->irq_unmask = vf610_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ic->irq_set_type = vf610_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ic->irq_set_wake = vf610_gpio_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Mask all GPIO interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < gc->ngpio; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) vf610_gpio_writel(0, port->base + PORT_PCR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Clear the interrupt status register for all GPIO's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) vf610_gpio_writel(~0, port->base + PORT_ISFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) girq->chip = ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) girq->parent_handler = vf610_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) girq->parents[0] = port->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return devm_gpiochip_add_data(dev, gc, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct platform_driver vf610_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "gpio-vf610",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .of_match_table = vf610_gpio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .probe = vf610_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) builtin_platform_driver(vf610_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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