Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2017 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/gpio/uniphier-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define UNIPHIER_GPIO_IRQ_MAX_NUM	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define UNIPHIER_GPIO_IRQ_MODE		0x94	/* irq mode (1: both edge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define UNIPHIER_GPIO_IRQ_FLT_EN	0x98	/* noise filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define UNIPHIER_GPIO_IRQ_FLT_CYC	0x9c	/* noise filter clock cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct uniphier_gpio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 saved_vals[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	reg = (bank + 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 * Unfortunately, the GPIO port registers are not contiguous because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (reg >= UNIPHIER_GPIO_IRQ_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		reg += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					    unsigned int *bank, u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				     unsigned int reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	tmp = readl(priv->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	tmp |= mask & val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writel(tmp, priv->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				     unsigned int reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				 mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static void uniphier_gpio_offset_write(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				       unsigned int offset, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				       int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int uniphier_gpio_offset_read(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				     unsigned int offset, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int bank, reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return !!(readl(priv->regs + reg_offset) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int uniphier_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				       unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int uniphier_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					 unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int uniphier_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					  unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void uniphier_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			      unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				       unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long i, bank, bank_mask, bank_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		bank_bits = bitmap_get_value8(bits, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					 bank_mask, bank_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * temporarily. Anyway, ->irq_set_type() will override it later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return irq_create_fwspec_mapping(&fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void uniphier_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct uniphier_gpio_priv *priv = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	irq_chip_mask_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void uniphier_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct uniphier_gpio_priv *priv = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	irq_chip_unmask_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct uniphier_gpio_priv *priv = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u32 mask = BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (type == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		type = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* To enable both edge detection, the noise filter must be enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return irq_chip_set_type_parent(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					      unsigned int hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct device_node *np = priv->chip.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	const __be32 *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 base, parent_base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	range = of_get_property(np, "socionext,interrupt-ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	len /= sizeof(*range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (; len >= 3; len -= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		base = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		parent_base = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		size = be32_to_cpu(*range++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (base <= hwirq && hwirq < base + size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			return hwirq - base + parent_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 					      struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					      unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					      unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (WARN_ON(fwspec->param_count < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	*out_hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 					  unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					  unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct uniphier_gpio_priv *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (WARN_ON(nr_irqs != 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* parent is UniPhier AIDET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	parent_fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	parent_fwspec.param[0] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 						IRQ_TYPE_EDGE_FALLING : type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 					    &priv->irq_chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					     struct irq_data *data, bool early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct uniphier_gpio_priv *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct gpio_chip *chip = &priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 						struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct uniphier_gpio_priv *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct gpio_chip *chip = &priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.alloc = uniphier_gpio_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.activate = uniphier_gpio_irq_domain_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.deactivate = uniphier_gpio_irq_domain_deactivate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.translate = uniphier_gpio_irq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 * Due to the hardware design, the noise filter must be enabled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	 * detect both edge interrupts.  This filter is intended to remove the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 * noise from the irq lines.  It does not work for GPIO input, so GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 * debounce is not supported.  Unfortunately, the filter period is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 * shared among all irq lines.  Just choose a sensible period here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int uniphier_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	struct device_node *parent_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct uniphier_gpio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	unsigned int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u32 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	parent_np = of_irq_find_parent(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (!parent_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	parent_domain = irq_find_host(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	of_node_put(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	priv->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (IS_ERR(priv->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return PTR_ERR(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	chip = &priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	chip->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	chip->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	chip->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	chip->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	chip->get_direction = uniphier_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	chip->direction_input = uniphier_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	chip->direction_output = uniphier_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	chip->get = uniphier_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	chip->set = uniphier_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	chip->set_multiple = uniphier_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	chip->to_irq = uniphier_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	chip->ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	irq_chip = &priv->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	irq_chip->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	irq_chip->irq_mask = uniphier_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	irq_chip->irq_eoi = irq_chip_eoi_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	uniphier_gpio_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	ret = devm_gpiochip_add_data(dev, chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	priv->domain = irq_domain_create_hierarchy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 					parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 					UNIPHIER_GPIO_IRQ_MAX_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 					of_node_to_fwnode(dev->of_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 					&uniphier_gpio_irq_domain_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (!priv->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int uniphier_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	u32 *val = priv->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	for (i = 0; i < nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		reg = uniphier_gpio_bank_to_reg(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int __maybe_unused uniphier_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	const u32 *val = priv->saved_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	for (i = 0; i < nbanks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		reg = uniphier_gpio_bank_to_reg(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	uniphier_gpio_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct dev_pm_ops uniphier_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 				     uniphier_gpio_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct of_device_id uniphier_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	{ .compatible = "socionext,uniphier-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct platform_driver uniphier_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.probe = uniphier_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	.remove = uniphier_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		.name = "uniphier-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		.of_match_table = uniphier_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		.pm = &uniphier_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) module_platform_driver(uniphier_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_DESCRIPTION("UniPhier GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_LICENSE("GPL v2");