^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TQ-Systems TQMx86 PLD GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on vendor driver by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TQMX86_NGPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TQMX86_NGPO 4 /* 0-3 - output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TQMX86_NGPI 4 /* 4-7 - input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TQMX86_GPIOD 1 /* GPIO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TQMX86_GPII_FALLING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TQMX86_GPII_RISING BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TQMX86_GPII_MASK (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TQMX86_GPII_BITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct tqmx86_gpio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) raw_spinlock_t spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 irq_type[TQMX86_NGPI];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ioread8(gd->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) iowrite8(val, gd->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) raw_spin_lock_irqsave(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = tqmx86_gpio_read(gpio, TQMX86_GPIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tqmx86_gpio_write(gpio, val, TQMX86_GPIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Direction cannot be changed. Validate is an input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Direction cannot be changed, validate is an output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tqmx86_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (TQMX86_DIR_INPUT_MASK & BIT(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void tqmx86_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int offset = (data->hwirq - TQMX86_NGPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tqmx86_gpio_data *gpio = gpiochip_get_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 gpiic, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) raw_spin_lock_irqsave(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gpiic &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void tqmx86_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int offset = (data->hwirq - TQMX86_NGPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct tqmx86_gpio_data *gpio = gpiochip_get_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 gpiic, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) raw_spin_lock_irqsave(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gpiic &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tqmx86_gpio_data *gpio = gpiochip_get_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int offset = (data->hwirq - TQMX86_NGPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int edge_type = type & IRQF_TRIGGER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 new_type, gpiic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch (edge_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) new_type = TQMX86_GPII_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) new_type = TQMX86_GPII_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -EINVAL; /* not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gpio->irq_type[offset] = new_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) raw_spin_lock_irqsave(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) gpiic |= new_type << (offset * TQMX86_GPII_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct irq_chip *irq_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long irq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i = 0, child_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) chained_irq_enter(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irq_bits = irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) child_irq = irq_find_mapping(gpio->chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) i + TQMX86_NGPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) generic_handle_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) chained_irq_exit(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Minimal runtime PM is needed by the IRQ subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tqmx86_gpio_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long *valid_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Only GPIOs 4-7 are valid for interrupts. Clear the others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clear_bit(0, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clear_bit(1, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clear_bit(2, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clear_bit(3, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int tqmx86_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct tqmx86_gpio_data *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (irq < 0 && irq != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&pdev->dev, "Cannot get I/O\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) raw_spin_lock_init(&gpio->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) gpio->io_base = io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) chip = &gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) chip->label = "gpio-tqmx86";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chip->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chip->direction_input = tqmx86_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) chip->direction_output = tqmx86_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) chip->get_direction = tqmx86_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) chip->get = tqmx86_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) chip->set = tqmx86_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) chip->ngpio = TQMX86_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) chip->parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct irq_chip *irq_chip = &gpio->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) irq_chip->name = chip->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) irq_chip->parent_device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) irq_chip->irq_mask = tqmx86_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) girq->chip = irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) girq->parent_handler = tqmx86_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto out_pm_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) girq->init_valid_mask = tqmx86_init_irq_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = devm_gpiochip_add_data(dev, chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(dev, "Could not register GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto out_pm_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_info(dev, "GPIO functionality initialized with %d pins\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) out_pm_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_driver tqmx86_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "tqmx86-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .pm = &tqmx86_gpio_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .probe = tqmx86_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) module_platform_driver(tqmx86_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_ALIAS("platform:tqmx86-gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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